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4 Commits

Author SHA1 Message Date
D.R.racer 4d3a5433ad Implement read/write registers for M707/M708 2022-09-16 10:23:47 +02:00
D.R.racer 2f0ceabce5 Upgrade protocol to v2.1 - read/write registers + CRC 2022-09-16 10:22:38 +02:00
VintagePC 9a20c85a5d First pass, improving the error recovery. 2022-09-16 10:22:38 +02:00
D.R.racer 2e293e90a0 MMU2 interface overhaul 
First port of the new MMU2-printer interface into 8bit FW.
 2022-09-16 10:21:53 +02:00