diff --git a/analog.c b/analog.c
index f012292..00924b9 100644
--- a/analog.c
+++ b/analog.c
@@ -77,9 +77,6 @@ void analog_init() {
 	This is where we read our analog value and store it in an array for later retrieval
 */
 ISR(ADC_vect, ISR_NOBLOCK) {
-	// save status register
-	uint8_t sreg_save = SREG;
-
 	// emulate free-running mode but be more deterministic about exactly which result we have, since this project has long-running interrupts
 	if (analog_mask > 0) { // at least one temp sensor uses an analog channel
 		// store next result
@@ -104,10 +101,6 @@ ISR(ADC_vect, ISR_NOBLOCK) {
 		// After the mux has been set, start a new conversion 
 		ADCSRA |= MASK(ADSC);
 	}
-
-	// restore status register
-	MEMORY_BARRIER();
-	SREG = sreg_save;
 }
 
 /*! Read analog value from saved result array
diff --git a/intercom.c b/intercom.c
index 32c3816..4235750 100644
--- a/intercom.c
+++ b/intercom.c
@@ -140,9 +140,6 @@ ISR(USART1_RX_vect)
 ISR(USART_RX_vect)
 #endif
 {
-	// save status register
-	uint8_t sreg_save = SREG;
-
 	// pull character
 	static uint8_t c;
 
@@ -200,10 +197,6 @@ ISR(USART_RX_vect)
 			#endif
 		}
 	}
-
-	// restore status register
-	MEMORY_BARRIER();
-	SREG = sreg_save;
 }
 
 // finished transmitting interrupt- only enabled at end of packet
@@ -213,9 +206,6 @@ ISR(USART1_TX_vect)
 ISR(USART_TX_vect)
 #endif
 {
-	// save status register
-	uint8_t sreg_save = SREG;
-
 	if (packet_pointer >= sizeof(intercom_packet_t)) {
 		disable_transmit();
 		packet_pointer = 0;
@@ -226,10 +216,6 @@ ISR(USART_TX_vect)
 			UCSR0B &= ~MASK(TXCIE0);
 		#endif
 	}
-
-	// restore status register
-	MEMORY_BARRIER();
-	SREG = sreg_save;
 }
 
 // tx queue empty interrupt- send next byte
@@ -239,9 +225,6 @@ ISR(USART1_UDRE_vect)
 ISR(USART_UDRE_vect)
 #endif
 {
-	// save status register
-	uint8_t sreg_save = SREG;
-
 	#ifdef	MOTHERBOARD
 	UDR1 = _tx.data[packet_pointer++];
 	#else
@@ -257,10 +240,6 @@ ISR(USART_UDRE_vect)
 			UCSR0B |= MASK(TXCIE0);
 		#endif
 	}
-
-	// restore status register
-	MEMORY_BARRIER();
-	SREG = sreg_save;
 }
 
 #endif	/* TEMP_INTERCOM */
diff --git a/serial.c b/serial.c
index 4bce2bf..5c1411e 100644
--- a/serial.c
+++ b/serial.c
@@ -113,9 +113,6 @@ ISR(USART_RX_vect)
 ISR(USART0_RX_vect)
 #endif
 {
-	// save status register
-	uint8_t sreg_save = SREG;
-
 	if (buf_canwrite(rx))
 		buf_push(rx, UDR0);
 	else {
@@ -137,10 +134,6 @@ ISR(USART0_RX_vect)
 		UCSR0B |= MASK(UDRIE0);
 	}
 	#endif
-
-	// restore status register
-	MEMORY_BARRIER();
-	SREG = sreg_save;
 }
 #pragma GCC diagnostic pop
 
@@ -153,9 +146,6 @@ ISR(USART_UDRE_vect)
 ISR(USART0_UDRE_vect)
 #endif
 {
-	// save status register
-	uint8_t sreg_save = SREG;
-
 	#ifdef	XONXOFF
 	if (flowflags & FLOWFLAG_SEND_XON) {
 		UDR0 = ASCII_XON;
@@ -171,10 +161,6 @@ ISR(USART0_UDRE_vect)
 		buf_pop(tx, UDR0);
 	else
 		UCSR0B &= ~MASK(UDRIE0);
-
-	// restore status register
-	MEMORY_BARRIER();
-	SREG = sreg_save;
 }
 
 /*
diff --git a/timer.c b/timer.c
index 934eb93..1a20d78 100644
--- a/timer.c
+++ b/timer.c
@@ -42,9 +42,6 @@ volatile uint8_t	clock_flag_1s = 0;
 
 /// comparator B is the system clock, happens every TICK_TIME
 ISR(TIMER1_COMPB_vect) {
-	// save status register
-	uint8_t sreg_save = SREG;
-
 	// set output compare register to the next clock tick
 	OCR1B = (OCR1B + TICK_TIME) & 0xFFFF;
 
@@ -70,19 +67,12 @@ ISR(TIMER1_COMPB_vect) {
 	}
 
   dda_clock();
-
-	// restore status register
-	MEMORY_BARRIER();
-	SREG = sreg_save;
 }
 
 #ifdef	MOTHERBOARD
 
 /// comparator A is the step timer. It has higher priority then B.
 ISR(TIMER1_COMPA_vect) {
-	// save status register
-	uint8_t sreg_save = SREG;
-
 	// Check if this is a real step, or just a next_step_time "overflow"
 	if (next_step_time < 65536) {
 		// step!
@@ -114,10 +104,6 @@ ISR(TIMER1_COMPA_vect) {
 		next_step_time += 10000;
 	}
 	// leave OCR1A as it was
-
-	// restore status register
-	MEMORY_BARRIER();
-	SREG = sreg_save;
 }
 #endif /* ifdef MOTHERBOARD */
 
diff --git a/watchdog.c b/watchdog.c
index c1d15ff..b4feb9c 100644
--- a/watchdog.c
+++ b/watchdog.c
@@ -32,17 +32,10 @@ volatile uint8_t	wd_flag = 0;
 // }
 
 ISR(WDT_vect) {
-	// save status register
-	uint8_t sreg_save = SREG;
-
 	// watchdog has tripped- no main loop activity for 0.5s, probably a bad thing
 	// if watchdog fires again, we will reset
 	// perhaps we should do something more intelligent in this interrupt?
 	wd_flag |= 1;
-
-	// restore status register
-	MEMORY_BARRIER();
-	SREG = sreg_save;
 }
 
 /// intialise watchdog