diff --git a/cmsis-system_stm32f4xx.c b/cmsis-system_stm32f4xx.c
index b3e04b5..aa7f978 100644
--- a/cmsis-system_stm32f4xx.c
+++ b/cmsis-system_stm32f4xx.c
@@ -342,10 +342,22 @@ void SetSysClock(void)
   // PLLN_6/7:    VCO output clock = 384 MHz (2 MHz * 192)
   // PLLP_0:      PLLCLK = 96 MHz (384 MHz / 4)
   // PLLQ_3:      USB clock = 48 MHz (384 MHz / 8) --> 48MHz is best choice for USB
+  #if __SYSTEM_CLOCK == 96000000
   RCC->PLLCFGR =  RCC_PLLCFGR_PLLSRC_HSE | RCC_PLLCFGR_PLLM_2 | \
                   RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | \
                   RCC_PLLCFGR_PLLP_0 | \
                   RCC_PLLCFGR_PLLQ_3;
+  #elif __SYSTEM_CLOCK == 100000000
+  RCC->PLLCFGR =  RCC_PLLCFGR_PLLSRC_HSE | RCC_PLLCFGR_PLLM_2 | \
+                  RCC_PLLCFGR_PLLN_3 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | \
+                  RCC_PLLCFGR_PLLP_0 | \
+                  RCC_PLLCFGR_PLLQ_3;
+  #elif __SYSTEM_CLOCK == 108000000
+  RCC->PLLCFGR =  RCC_PLLCFGR_PLLSRC_HSE | RCC_PLLCFGR_PLLM_2 | \
+                  RCC_PLLCFGR_PLLN_3 | RCC_PLLCFGR_PLLN_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | \
+                  RCC_PLLCFGR_PLLP_0 | \
+                  RCC_PLLCFGR_PLLQ_0 | RCC_PLLCFGR_PLLQ_3;
+  #endif
 
   /* Enable the main PLL. */
   RCC->CR |= RCC_CR_PLLON;
diff --git a/cmsis-system_stm32f4xx.h b/cmsis-system_stm32f4xx.h
index acceb80..6b7ad9e 100644
--- a/cmsis-system_stm32f4xx.h
+++ b/cmsis-system_stm32f4xx.h
@@ -62,7 +62,9 @@
  extern "C" {
 #endif
 
-#define __SYSTEM_CLOCK 96000000
+// #define __SYSTEM_CLOCK 96000000
+#define __SYSTEM_CLOCK 100000000
+// #define __SYSTEM_CLOCK 108000000 // Overclocking is not recommended!
 /** @addtogroup STM32F4xx_System_Includes
   * @{
   */