diff --git a/Makefile-ARM b/Makefile-ARM
index f16f0b4..19bbc0c 100644
--- a/Makefile-ARM
+++ b/Makefile-ARM
@@ -139,6 +139,7 @@ else ifeq ($(MCU), stm32f411)
   CFLAGS += -mfloat-abi=hard
   CFLAGS += -mlittle-endian
   CFLAGS += -D__FPU_PRESENT=1
+  CFLAGS += -fomit-frame-pointer
 endif
 # Other options ...
 CFLAGS += -Wall
diff --git a/arduino_stm32f411.h b/arduino_stm32f411.h
index 672eb0f..994ddf8 100644
--- a/arduino_stm32f411.h
+++ b/arduino_stm32f411.h
@@ -20,18 +20,36 @@
 
 #include "cmsis-stm32f4xx.h"
 
-#define F_CPU __SYSTEM_CLOCK
-
 /** Pins for UART, the serial port.
 */
 #define RXD             PA_3
 #define TXD             PA_2
 
+/** Clock setup for APB1 and APB2 clock.
+*/
+#define F_CPU __SYSTEM_CLOCK
+
+#define PPRE1_DIV (RCC_CFGR_PPRE1_DIV2) // 0x1000
+#define PPRE2_DIV (RCC_CFGR_PPRE2_DIV1) // 0x0000
+
+#if PPRE1_DIV > 0
+  #define APB1_DIV (1 << ((PPRE1_DIV >> 10) - 3))
+#else
+  #define APB1_DIV (1)
+#endif
+#if PPRE2_DIV > 0
+  #define APB2_DIV (1 << ((PPRE2_DIV >> 13) - 3))
+#else
+  #define APB2_DIV (1)
+#endif
+
+#define _APB1_CLOCK (__SYSTEM_CLOCK/APB1_DIV)
+#define _APB2_CLOCK (__SYSTEM_CLOCK/APB2_DIV)
+
 /**
   We define only pins available on the Nucleo F411RE here.
   Use alphas for PORT and numerics for PIN, close to the design.
 */
-
 #define NO_TIMER        ((TIM_TypeDef *) 0)
 
 #define PA_0_PIN      0
diff --git a/cmsis-stm32f4xx.h b/cmsis-stm32f4xx.h
index 69e8511..69cb392 100644
--- a/cmsis-stm32f4xx.h
+++ b/cmsis-stm32f4xx.h
@@ -67,10 +67,6 @@
 #ifndef __STM32F4xx_H
 #define __STM32F4xx_H
 
-#ifdef __cplusplus
- extern "C" {
-#endif /* __cplusplus */
-
 /** @addtogroup Library_configuration_section
   * @{
   */
@@ -727,17 +723,17 @@ USB_OTG_HostChannelTypeDef;
 /**
   * @brief Peripheral_memory_map
   */
-#define FLASH_BASE            ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region                         */
-#define CCMDATARAM_BASE       ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region  */
-#define SRAM1_BASE            ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region                             */
-#define SRAM2_BASE            ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region                              */
-#define PERIPH_BASE           ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region                                */
-#define BKPSRAM_BASE          ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region                         */
-#define SRAM1_BB_BASE         ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region                             */
-#define SRAM2_BB_BASE         ((uint32_t)0x22380000) /*!< SRAM2(16 KB) base address in the bit-band region                              */
-#define PERIPH_BB_BASE        ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region                                */
-#define BKPSRAM_BB_BASE       ((uint32_t)0x42480000) /*!< Backup SRAM(4 KB) base address in the bit-band region                         */
-#define FLASH_END             ((uint32_t)0x0807FFFF) /*!< FLASH end address */
+#define FLASH_BASE            (0x08000000UL) /*!< FLASH(up to 1 MB) base address in the alias region                         */
+#define CCMDATARAM_BASE       (0x10000000UL) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region  */
+#define SRAM1_BASE            (0x20000000UL) /*!< SRAM1(112 KB) base address in the alias region                             */
+#define SRAM2_BASE            (0x2001C000UL) /*!< SRAM2(16 KB) base address in the alias region                              */
+#define PERIPH_BASE           (0x40000000UL) /*!< Peripheral base address in the alias region                                */
+#define BKPSRAM_BASE          (0x40024000UL) /*!< Backup SRAM(4 KB) base address in the alias region                         */
+#define SRAM1_BB_BASE         (0x22000000UL) /*!< SRAM1(112 KB) base address in the bit-band region                             */
+#define SRAM2_BB_BASE         (0x22380000UL) /*!< SRAM2(16 KB) base address in the bit-band region                              */
+#define PERIPH_BB_BASE        (0x42000000UL) /*!< Peripheral base address in the bit-band region                                */
+#define BKPSRAM_BB_BASE       (0x42480000UL) /*!< Backup SRAM(4 KB) base address in the bit-band region                         */
+#define FLASH_END             (0x0807FFFFUL) /*!< FLASH end address */
 
 /* Legacy defines */
 #define SRAM_BASE             SRAM1_BASE
@@ -814,23 +810,23 @@ USB_OTG_HostChannelTypeDef;
 #define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8)
 
 /* Debug MCU registers base address */
-#define DBGMCU_BASE           ((uint32_t )0xE0042000)
+#define DBGMCU_BASE           (0xE0042000UL)
 
 /*!< USB registers base address */
-#define USB_OTG_FS_PERIPH_BASE               ((uint32_t )0x50000000)
+#define USB_OTG_FS_PERIPH_BASE               (0x50000000UL)
 
-#define USB_OTG_GLOBAL_BASE                  ((uint32_t )0x000)
-#define USB_OTG_DEVICE_BASE                  ((uint32_t )0x800)
-#define USB_OTG_IN_ENDPOINT_BASE             ((uint32_t )0x900)
-#define USB_OTG_OUT_ENDPOINT_BASE            ((uint32_t )0xB00)
-#define USB_OTG_EP_REG_SIZE                  ((uint32_t )0x20)
-#define USB_OTG_HOST_BASE                    ((uint32_t )0x400)
-#define USB_OTG_HOST_PORT_BASE               ((uint32_t )0x440)
-#define USB_OTG_HOST_CHANNEL_BASE            ((uint32_t )0x500)
-#define USB_OTG_HOST_CHANNEL_SIZE            ((uint32_t )0x20)
-#define USB_OTG_PCGCCTL_BASE                 ((uint32_t )0xE00)
-#define USB_OTG_FIFO_BASE                    ((uint32_t )0x1000)
-#define USB_OTG_FIFO_SIZE                    ((uint32_t )0x1000)
+#define USB_OTG_GLOBAL_BASE                  (0x000UL)
+#define USB_OTG_DEVICE_BASE                  (0x800UL)
+#define USB_OTG_IN_ENDPOINT_BASE             (0x900UL)
+#define USB_OTG_OUT_ENDPOINT_BASE            (0xB00UL)
+#define USB_OTG_EP_REG_SIZE                  (0x20UL)
+#define USB_OTG_HOST_BASE                    (0x400UL)
+#define USB_OTG_HOST_PORT_BASE               (0x440UL)
+#define USB_OTG_HOST_CHANNEL_BASE            (0x500UL)
+#define USB_OTG_HOST_CHANNEL_SIZE            (0x20UL)
+#define USB_OTG_PCGCCTL_BASE                 (0xE00UL)
+#define USB_OTG_FIFO_BASE                    (0x1000UL)
+#define USB_OTG_FIFO_SIZE                    (0x1000UL)
 
 /**
   * @}
@@ -923,360 +919,360 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for ADC_SR register  ********************/
-#define  ADC_SR_AWD                          ((uint32_t)0x00000001)       /*!<Analog watchdog flag */
-#define  ADC_SR_EOC                          ((uint32_t)0x00000002)       /*!<End of conversion */
-#define  ADC_SR_JEOC                         ((uint32_t)0x00000004)       /*!<Injected channel end of conversion */
-#define  ADC_SR_JSTRT                        ((uint32_t)0x00000008)       /*!<Injected channel Start flag */
-#define  ADC_SR_STRT                         ((uint32_t)0x00000010)       /*!<Regular channel Start flag */
-#define  ADC_SR_OVR                          ((uint32_t)0x00000020)       /*!<Overrun flag */
+#define  ADC_SR_AWD                          (0x00000001UL)       /*!<Analog watchdog flag */
+#define  ADC_SR_EOC                          (0x00000002UL)       /*!<End of conversion */
+#define  ADC_SR_JEOC                         (0x00000004UL)       /*!<Injected channel end of conversion */
+#define  ADC_SR_JSTRT                        (0x00000008UL)       /*!<Injected channel Start flag */
+#define  ADC_SR_STRT                         (0x00000010UL)       /*!<Regular channel Start flag */
+#define  ADC_SR_OVR                          (0x00000020UL)       /*!<Overrun flag */
 
 /*******************  Bit definition for ADC_CR1 register  ********************/
-#define  ADC_CR1_AWDCH                       ((uint32_t)0x0000001F)        /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define  ADC_CR1_AWDCH_0                     ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  ADC_CR1_AWDCH_1                     ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  ADC_CR1_AWDCH_2                     ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  ADC_CR1_AWDCH_3                     ((uint32_t)0x00000008)        /*!<Bit 3 */
-#define  ADC_CR1_AWDCH_4                     ((uint32_t)0x00000010)        /*!<Bit 4 */
-#define  ADC_CR1_EOCIE                       ((uint32_t)0x00000020)        /*!<Interrupt enable for EOC */
-#define  ADC_CR1_AWDIE                       ((uint32_t)0x00000040)        /*!<AAnalog Watchdog interrupt enable */
-#define  ADC_CR1_JEOCIE                      ((uint32_t)0x00000080)        /*!<Interrupt enable for injected channels */
-#define  ADC_CR1_SCAN                        ((uint32_t)0x00000100)        /*!<Scan mode */
-#define  ADC_CR1_AWDSGL                      ((uint32_t)0x00000200)        /*!<Enable the watchdog on a single channel in scan mode */
-#define  ADC_CR1_JAUTO                       ((uint32_t)0x00000400)        /*!<Automatic injected group conversion */
-#define  ADC_CR1_DISCEN                      ((uint32_t)0x00000800)        /*!<Discontinuous mode on regular channels */
-#define  ADC_CR1_JDISCEN                     ((uint32_t)0x00001000)        /*!<Discontinuous mode on injected channels */
-#define  ADC_CR1_DISCNUM                     ((uint32_t)0x0000E000)        /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
-#define  ADC_CR1_DISCNUM_0                   ((uint32_t)0x00002000)        /*!<Bit 0 */
-#define  ADC_CR1_DISCNUM_1                   ((uint32_t)0x00004000)        /*!<Bit 1 */
-#define  ADC_CR1_DISCNUM_2                   ((uint32_t)0x00008000)        /*!<Bit 2 */
-#define  ADC_CR1_JAWDEN                      ((uint32_t)0x00400000)        /*!<Analog watchdog enable on injected channels */
-#define  ADC_CR1_AWDEN                       ((uint32_t)0x00800000)        /*!<Analog watchdog enable on regular channels */
-#define  ADC_CR1_RES                         ((uint32_t)0x03000000)        /*!<RES[2:0] bits (Resolution) */
-#define  ADC_CR1_RES_0                       ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  ADC_CR1_RES_1                       ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  ADC_CR1_OVRIE                       ((uint32_t)0x04000000)         /*!<overrun interrupt enable */
+#define  ADC_CR1_AWDCH                       (0x0000001FUL)        /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define  ADC_CR1_AWDCH_0                     (0x00000001UL)        /*!<Bit 0 */
+#define  ADC_CR1_AWDCH_1                     (0x00000002UL)        /*!<Bit 1 */
+#define  ADC_CR1_AWDCH_2                     (0x00000004UL)        /*!<Bit 2 */
+#define  ADC_CR1_AWDCH_3                     (0x00000008UL)        /*!<Bit 3 */
+#define  ADC_CR1_AWDCH_4                     (0x00000010UL)        /*!<Bit 4 */
+#define  ADC_CR1_EOCIE                       (0x00000020UL)        /*!<Interrupt enable for EOC */
+#define  ADC_CR1_AWDIE                       (0x00000040UL)        /*!<AAnalog Watchdog interrupt enable */
+#define  ADC_CR1_JEOCIE                      (0x00000080UL)        /*!<Interrupt enable for injected channels */
+#define  ADC_CR1_SCAN                        (0x00000100UL)        /*!<Scan mode */
+#define  ADC_CR1_AWDSGL                      (0x00000200UL)        /*!<Enable the watchdog on a single channel in scan mode */
+#define  ADC_CR1_JAUTO                       (0x00000400UL)        /*!<Automatic injected group conversion */
+#define  ADC_CR1_DISCEN                      (0x00000800UL)        /*!<Discontinuous mode on regular channels */
+#define  ADC_CR1_JDISCEN                     (0x00001000UL)        /*!<Discontinuous mode on injected channels */
+#define  ADC_CR1_DISCNUM                     (0x0000E000UL)        /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define  ADC_CR1_DISCNUM_0                   (0x00002000UL)        /*!<Bit 0 */
+#define  ADC_CR1_DISCNUM_1                   (0x00004000UL)        /*!<Bit 1 */
+#define  ADC_CR1_DISCNUM_2                   (0x00008000UL)        /*!<Bit 2 */
+#define  ADC_CR1_JAWDEN                      (0x00400000UL)        /*!<Analog watchdog enable on injected channels */
+#define  ADC_CR1_AWDEN                       (0x00800000UL)        /*!<Analog watchdog enable on regular channels */
+#define  ADC_CR1_RES                         (0x03000000UL)        /*!<RES[2:0] bits (Resolution) */
+#define  ADC_CR1_RES_0                       (0x01000000UL)        /*!<Bit 0 */
+#define  ADC_CR1_RES_1                       (0x02000000UL)        /*!<Bit 1 */
+#define  ADC_CR1_OVRIE                       (0x04000000UL)         /*!<overrun interrupt enable */
 
 /*******************  Bit definition for ADC_CR2 register  ********************/
-#define  ADC_CR2_ADON                        ((uint32_t)0x00000001)        /*!<A/D Converter ON / OFF */
-#define  ADC_CR2_CONT                        ((uint32_t)0x00000002)        /*!<Continuous Conversion */
-#define  ADC_CR2_DMA                         ((uint32_t)0x00000100)        /*!<Direct Memory access mode */
-#define  ADC_CR2_DDS                         ((uint32_t)0x00000200)        /*!<DMA disable selection (Single ADC) */
-#define  ADC_CR2_EOCS                        ((uint32_t)0x00000400)        /*!<End of conversion selection */
-#define  ADC_CR2_ALIGN                       ((uint32_t)0x00000800)        /*!<Data Alignment */
-#define  ADC_CR2_JEXTSEL                     ((uint32_t)0x000F0000)        /*!<JEXTSEL[3:0] bits (External event select for injected group) */
-#define  ADC_CR2_JEXTSEL_0                   ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  ADC_CR2_JEXTSEL_1                   ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  ADC_CR2_JEXTSEL_2                   ((uint32_t)0x00040000)        /*!<Bit 2 */
-#define  ADC_CR2_JEXTSEL_3                   ((uint32_t)0x00080000)        /*!<Bit 3 */
-#define  ADC_CR2_JEXTEN                      ((uint32_t)0x00300000)        /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
-#define  ADC_CR2_JEXTEN_0                    ((uint32_t)0x00100000)        /*!<Bit 0 */
-#define  ADC_CR2_JEXTEN_1                    ((uint32_t)0x00200000)        /*!<Bit 1 */
-#define  ADC_CR2_JSWSTART                    ((uint32_t)0x00400000)        /*!<Start Conversion of injected channels */
-#define  ADC_CR2_EXTSEL                      ((uint32_t)0x0F000000)        /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
-#define  ADC_CR2_EXTSEL_0                    ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  ADC_CR2_EXTSEL_1                    ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  ADC_CR2_EXTSEL_2                    ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  ADC_CR2_EXTSEL_3                    ((uint32_t)0x08000000)        /*!<Bit 3 */
-#define  ADC_CR2_EXTEN                       ((uint32_t)0x30000000)        /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
-#define  ADC_CR2_EXTEN_0                     ((uint32_t)0x10000000)        /*!<Bit 0 */
-#define  ADC_CR2_EXTEN_1                     ((uint32_t)0x20000000)        /*!<Bit 1 */
-#define  ADC_CR2_SWSTART                     ((uint32_t)0x40000000)        /*!<Start Conversion of regular channels */
+#define  ADC_CR2_ADON                        (0x00000001UL)        /*!<A/D Converter ON / OFF */
+#define  ADC_CR2_CONT                        (0x00000002UL)        /*!<Continuous Conversion */
+#define  ADC_CR2_DMA                         (0x00000100UL)        /*!<Direct Memory access mode */
+#define  ADC_CR2_DDS                         (0x00000200UL)        /*!<DMA disable selection (Single ADC) */
+#define  ADC_CR2_EOCS                        (0x00000400UL)        /*!<End of conversion selection */
+#define  ADC_CR2_ALIGN                       (0x00000800UL)        /*!<Data Alignment */
+#define  ADC_CR2_JEXTSEL                     (0x000F0000UL)        /*!<JEXTSEL[3:0] bits (External event select for injected group) */
+#define  ADC_CR2_JEXTSEL_0                   (0x00010000UL)        /*!<Bit 0 */
+#define  ADC_CR2_JEXTSEL_1                   (0x00020000UL)        /*!<Bit 1 */
+#define  ADC_CR2_JEXTSEL_2                   (0x00040000UL)        /*!<Bit 2 */
+#define  ADC_CR2_JEXTSEL_3                   (0x00080000UL)        /*!<Bit 3 */
+#define  ADC_CR2_JEXTEN                      (0x00300000UL)        /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
+#define  ADC_CR2_JEXTEN_0                    (0x00100000UL)        /*!<Bit 0 */
+#define  ADC_CR2_JEXTEN_1                    (0x00200000UL)        /*!<Bit 1 */
+#define  ADC_CR2_JSWSTART                    (0x00400000UL)        /*!<Start Conversion of injected channels */
+#define  ADC_CR2_EXTSEL                      (0x0F000000UL)        /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
+#define  ADC_CR2_EXTSEL_0                    (0x01000000UL)        /*!<Bit 0 */
+#define  ADC_CR2_EXTSEL_1                    (0x02000000UL)        /*!<Bit 1 */
+#define  ADC_CR2_EXTSEL_2                    (0x04000000UL)        /*!<Bit 2 */
+#define  ADC_CR2_EXTSEL_3                    (0x08000000UL)        /*!<Bit 3 */
+#define  ADC_CR2_EXTEN                       (0x30000000UL)        /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
+#define  ADC_CR2_EXTEN_0                     (0x10000000UL)        /*!<Bit 0 */
+#define  ADC_CR2_EXTEN_1                     (0x20000000UL)        /*!<Bit 1 */
+#define  ADC_CR2_SWSTART                     (0x40000000UL)        /*!<Start Conversion of regular channels */
 
 /******************  Bit definition for ADC_SMPR1 register  *******************/
-#define  ADC_SMPR1_SMP10                     ((uint32_t)0x00000007)        /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
-#define  ADC_SMPR1_SMP10_0                   ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP10_1                   ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP10_2                   ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP11                     ((uint32_t)0x00000038)        /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
-#define  ADC_SMPR1_SMP11_0                   ((uint32_t)0x00000008)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP11_1                   ((uint32_t)0x00000010)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP11_2                   ((uint32_t)0x00000020)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP12                     ((uint32_t)0x000001C0)        /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
-#define  ADC_SMPR1_SMP12_0                   ((uint32_t)0x00000040)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP12_1                   ((uint32_t)0x00000080)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP12_2                   ((uint32_t)0x00000100)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP13                     ((uint32_t)0x00000E00)        /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
-#define  ADC_SMPR1_SMP13_0                   ((uint32_t)0x00000200)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP13_1                   ((uint32_t)0x00000400)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP13_2                   ((uint32_t)0x00000800)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP14                     ((uint32_t)0x00007000)        /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
-#define  ADC_SMPR1_SMP14_0                   ((uint32_t)0x00001000)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP14_1                   ((uint32_t)0x00002000)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP14_2                   ((uint32_t)0x00004000)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP15                     ((uint32_t)0x00038000)        /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
-#define  ADC_SMPR1_SMP15_0                   ((uint32_t)0x00008000)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP15_1                   ((uint32_t)0x00010000)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP15_2                   ((uint32_t)0x00020000)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP16                     ((uint32_t)0x001C0000)        /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
-#define  ADC_SMPR1_SMP16_0                   ((uint32_t)0x00040000)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP16_1                   ((uint32_t)0x00080000)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP16_2                   ((uint32_t)0x00100000)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP17                     ((uint32_t)0x00E00000)        /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
-#define  ADC_SMPR1_SMP17_0                   ((uint32_t)0x00200000)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP17_1                   ((uint32_t)0x00400000)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP17_2                   ((uint32_t)0x00800000)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP18                     ((uint32_t)0x07000000)        /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
-#define  ADC_SMPR1_SMP18_0                   ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP18_1                   ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP18_2                   ((uint32_t)0x04000000)        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP10                     (0x00000007UL)        /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define  ADC_SMPR1_SMP10_0                   (0x00000001UL)        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP10_1                   (0x00000002UL)        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP10_2                   (0x00000004UL)        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP11                     (0x00000038UL)        /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define  ADC_SMPR1_SMP11_0                   (0x00000008UL)        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP11_1                   (0x00000010UL)        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP11_2                   (0x00000020UL)        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP12                     (0x000001C0UL)        /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define  ADC_SMPR1_SMP12_0                   (0x00000040UL)        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP12_1                   (0x00000080UL)        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP12_2                   (0x00000100UL)        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP13                     (0x00000E00UL)        /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define  ADC_SMPR1_SMP13_0                   (0x00000200UL)        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP13_1                   (0x00000400UL)        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP13_2                   (0x00000800UL)        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP14                     (0x00007000UL)        /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define  ADC_SMPR1_SMP14_0                   (0x00001000UL)        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP14_1                   (0x00002000UL)        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP14_2                   (0x00004000UL)        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP15                     (0x00038000UL)        /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define  ADC_SMPR1_SMP15_0                   (0x00008000UL)        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP15_1                   (0x00010000UL)        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP15_2                   (0x00020000UL)        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP16                     (0x001C0000UL)        /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define  ADC_SMPR1_SMP16_0                   (0x00040000UL)        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP16_1                   (0x00080000UL)        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP16_2                   (0x00100000UL)        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP17                     (0x00E00000UL)        /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define  ADC_SMPR1_SMP17_0                   (0x00200000UL)        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP17_1                   (0x00400000UL)        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP17_2                   (0x00800000UL)        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP18                     (0x07000000UL)        /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
+#define  ADC_SMPR1_SMP18_0                   (0x01000000UL)        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP18_1                   (0x02000000UL)        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP18_2                   (0x04000000UL)        /*!<Bit 2 */
 
 /******************  Bit definition for ADC_SMPR2 register  *******************/
-#define  ADC_SMPR2_SMP0                      ((uint32_t)0x00000007)        /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
-#define  ADC_SMPR2_SMP0_0                    ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP0_1                    ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP0_2                    ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP1                      ((uint32_t)0x00000038)        /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
-#define  ADC_SMPR2_SMP1_0                    ((uint32_t)0x00000008)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP1_1                    ((uint32_t)0x00000010)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP1_2                    ((uint32_t)0x00000020)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP2                      ((uint32_t)0x000001C0)        /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
-#define  ADC_SMPR2_SMP2_0                    ((uint32_t)0x00000040)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP2_1                    ((uint32_t)0x00000080)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP2_2                    ((uint32_t)0x00000100)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP3                      ((uint32_t)0x00000E00)        /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
-#define  ADC_SMPR2_SMP3_0                    ((uint32_t)0x00000200)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP3_1                    ((uint32_t)0x00000400)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP3_2                    ((uint32_t)0x00000800)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP4                      ((uint32_t)0x00007000)        /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
-#define  ADC_SMPR2_SMP4_0                    ((uint32_t)0x00001000)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP4_1                    ((uint32_t)0x00002000)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP4_2                    ((uint32_t)0x00004000)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP5                      ((uint32_t)0x00038000)        /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
-#define  ADC_SMPR2_SMP5_0                    ((uint32_t)0x00008000)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP5_1                    ((uint32_t)0x00010000)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP5_2                    ((uint32_t)0x00020000)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP6                      ((uint32_t)0x001C0000)        /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
-#define  ADC_SMPR2_SMP6_0                    ((uint32_t)0x00040000)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP6_1                    ((uint32_t)0x00080000)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP6_2                    ((uint32_t)0x00100000)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP7                      ((uint32_t)0x00E00000)        /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
-#define  ADC_SMPR2_SMP7_0                    ((uint32_t)0x00200000)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP7_1                    ((uint32_t)0x00400000)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP7_2                    ((uint32_t)0x00800000)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP8                      ((uint32_t)0x07000000)        /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
-#define  ADC_SMPR2_SMP8_0                    ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP8_1                    ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP8_2                    ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP9                      ((uint32_t)0x38000000)        /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
-#define  ADC_SMPR2_SMP9_0                    ((uint32_t)0x08000000)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP9_1                    ((uint32_t)0x10000000)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP9_2                    ((uint32_t)0x20000000)        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP0                      (0x00000007UL)        /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define  ADC_SMPR2_SMP0_0                    (0x00000001UL)        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP0_1                    (0x00000002UL)        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP0_2                    (0x00000004UL)        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP1                      (0x00000038UL)        /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define  ADC_SMPR2_SMP1_0                    (0x00000008UL)        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP1_1                    (0x00000010UL)        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP1_2                    (0x00000020UL)        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP2                      (0x000001C0UL)        /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define  ADC_SMPR2_SMP2_0                    (0x00000040UL)        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP2_1                    (0x00000080UL)        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP2_2                    (0x00000100UL)        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP3                      (0x00000E00UL)        /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define  ADC_SMPR2_SMP3_0                    (0x00000200UL)        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP3_1                    (0x00000400UL)        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP3_2                    (0x00000800UL)        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP4                      (0x00007000UL)        /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define  ADC_SMPR2_SMP4_0                    (0x00001000UL)        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP4_1                    (0x00002000UL)        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP4_2                    (0x00004000UL)        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP5                      (0x00038000UL)        /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define  ADC_SMPR2_SMP5_0                    (0x00008000UL)        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP5_1                    (0x00010000UL)        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP5_2                    (0x00020000UL)        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP6                      (0x001C0000UL)        /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define  ADC_SMPR2_SMP6_0                    (0x00040000UL)        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP6_1                    (0x00080000UL)        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP6_2                    (0x00100000UL)        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP7                      (0x00E00000UL)        /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define  ADC_SMPR2_SMP7_0                    (0x00200000UL)        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP7_1                    (0x00400000UL)        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP7_2                    (0x00800000UL)        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP8                      (0x07000000UL)        /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define  ADC_SMPR2_SMP8_0                    (0x01000000UL)        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP8_1                    (0x02000000UL)        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP8_2                    (0x04000000UL)        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP9                      (0x38000000UL)        /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define  ADC_SMPR2_SMP9_0                    (0x08000000UL)        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP9_1                    (0x10000000UL)        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP9_2                    (0x20000000UL)        /*!<Bit 2 */
 
 /******************  Bit definition for ADC_JOFR1 register  *******************/
-#define  ADC_JOFR1_JOFFSET1                  ((uint32_t)0x0FFF)            /*!<Data offset for injected channel 1 */
+#define  ADC_JOFR1_JOFFSET1                  (0x0FFFUL)            /*!<Data offset for injected channel 1 */
 
 /******************  Bit definition for ADC_JOFR2 register  *******************/
-#define  ADC_JOFR2_JOFFSET2                  ((uint32_t)0x0FFF)            /*!<Data offset for injected channel 2 */
+#define  ADC_JOFR2_JOFFSET2                  (0x0FFFUL)            /*!<Data offset for injected channel 2 */
 
 /******************  Bit definition for ADC_JOFR3 register  *******************/
-#define  ADC_JOFR3_JOFFSET3                  ((uint32_t)0x0FFF)            /*!<Data offset for injected channel 3 */
+#define  ADC_JOFR3_JOFFSET3                  (0x0FFFUL)            /*!<Data offset for injected channel 3 */
 
 /******************  Bit definition for ADC_JOFR4 register  *******************/
-#define  ADC_JOFR4_JOFFSET4                  ((uint32_t)0x0FFF)            /*!<Data offset for injected channel 4 */
+#define  ADC_JOFR4_JOFFSET4                  (0x0FFFUL)            /*!<Data offset for injected channel 4 */
 
 /*******************  Bit definition for ADC_HTR register  ********************/
-#define  ADC_HTR_HT                          ((uint32_t)0x0FFF)            /*!<Analog watchdog high threshold */
+#define  ADC_HTR_HT                          (0x0FFFUL)            /*!<Analog watchdog high threshold */
 
 /*******************  Bit definition for ADC_LTR register  ********************/
-#define  ADC_LTR_LT                          ((uint32_t)0x0FFF)            /*!<Analog watchdog low threshold */
+#define  ADC_LTR_LT                          (0x0FFFUL)            /*!<Analog watchdog low threshold */
 
 /*******************  Bit definition for ADC_SQR1 register  *******************/
-#define  ADC_SQR1_SQ13                       ((uint32_t)0x0000001F)        /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
-#define  ADC_SQR1_SQ13_0                     ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  ADC_SQR1_SQ13_1                     ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  ADC_SQR1_SQ13_2                     ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  ADC_SQR1_SQ13_3                     ((uint32_t)0x00000008)        /*!<Bit 3 */
-#define  ADC_SQR1_SQ13_4                     ((uint32_t)0x00000010)        /*!<Bit 4 */
-#define  ADC_SQR1_SQ14                       ((uint32_t)0x000003E0)        /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
-#define  ADC_SQR1_SQ14_0                     ((uint32_t)0x00000020)        /*!<Bit 0 */
-#define  ADC_SQR1_SQ14_1                     ((uint32_t)0x00000040)        /*!<Bit 1 */
-#define  ADC_SQR1_SQ14_2                     ((uint32_t)0x00000080)        /*!<Bit 2 */
-#define  ADC_SQR1_SQ14_3                     ((uint32_t)0x00000100)        /*!<Bit 3 */
-#define  ADC_SQR1_SQ14_4                     ((uint32_t)0x00000200)        /*!<Bit 4 */
-#define  ADC_SQR1_SQ15                       ((uint32_t)0x00007C00)        /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
-#define  ADC_SQR1_SQ15_0                     ((uint32_t)0x00000400)        /*!<Bit 0 */
-#define  ADC_SQR1_SQ15_1                     ((uint32_t)0x00000800)        /*!<Bit 1 */
-#define  ADC_SQR1_SQ15_2                     ((uint32_t)0x00001000)        /*!<Bit 2 */
-#define  ADC_SQR1_SQ15_3                     ((uint32_t)0x00002000)        /*!<Bit 3 */
-#define  ADC_SQR1_SQ15_4                     ((uint32_t)0x00004000)        /*!<Bit 4 */
-#define  ADC_SQR1_SQ16                       ((uint32_t)0x000F8000)        /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
-#define  ADC_SQR1_SQ16_0                     ((uint32_t)0x00008000)        /*!<Bit 0 */
-#define  ADC_SQR1_SQ16_1                     ((uint32_t)0x00010000)        /*!<Bit 1 */
-#define  ADC_SQR1_SQ16_2                     ((uint32_t)0x00020000)        /*!<Bit 2 */
-#define  ADC_SQR1_SQ16_3                     ((uint32_t)0x00040000)        /*!<Bit 3 */
-#define  ADC_SQR1_SQ16_4                     ((uint32_t)0x00080000)        /*!<Bit 4 */
-#define  ADC_SQR1_L                          ((uint32_t)0x00F00000)        /*!<L[3:0] bits (Regular channel sequence length) */
-#define  ADC_SQR1_L_0                        ((uint32_t)0x00100000)        /*!<Bit 0 */
-#define  ADC_SQR1_L_1                        ((uint32_t)0x00200000)        /*!<Bit 1 */
-#define  ADC_SQR1_L_2                        ((uint32_t)0x00400000)        /*!<Bit 2 */
-#define  ADC_SQR1_L_3                        ((uint32_t)0x00800000)        /*!<Bit 3 */
+#define  ADC_SQR1_SQ13                       (0x0000001FUL)        /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
+#define  ADC_SQR1_SQ13_0                     (0x00000001UL)        /*!<Bit 0 */
+#define  ADC_SQR1_SQ13_1                     (0x00000002UL)        /*!<Bit 1 */
+#define  ADC_SQR1_SQ13_2                     (0x00000004UL)        /*!<Bit 2 */
+#define  ADC_SQR1_SQ13_3                     (0x00000008UL)        /*!<Bit 3 */
+#define  ADC_SQR1_SQ13_4                     (0x00000010UL)        /*!<Bit 4 */
+#define  ADC_SQR1_SQ14                       (0x000003E0UL)        /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
+#define  ADC_SQR1_SQ14_0                     (0x00000020UL)        /*!<Bit 0 */
+#define  ADC_SQR1_SQ14_1                     (0x00000040UL)        /*!<Bit 1 */
+#define  ADC_SQR1_SQ14_2                     (0x00000080UL)        /*!<Bit 2 */
+#define  ADC_SQR1_SQ14_3                     (0x00000100UL)        /*!<Bit 3 */
+#define  ADC_SQR1_SQ14_4                     (0x00000200UL)        /*!<Bit 4 */
+#define  ADC_SQR1_SQ15                       (0x00007C00UL)        /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
+#define  ADC_SQR1_SQ15_0                     (0x00000400UL)        /*!<Bit 0 */
+#define  ADC_SQR1_SQ15_1                     (0x00000800UL)        /*!<Bit 1 */
+#define  ADC_SQR1_SQ15_2                     (0x00001000UL)        /*!<Bit 2 */
+#define  ADC_SQR1_SQ15_3                     (0x00002000UL)        /*!<Bit 3 */
+#define  ADC_SQR1_SQ15_4                     (0x00004000UL)        /*!<Bit 4 */
+#define  ADC_SQR1_SQ16                       (0x000F8000UL)        /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
+#define  ADC_SQR1_SQ16_0                     (0x00008000UL)        /*!<Bit 0 */
+#define  ADC_SQR1_SQ16_1                     (0x00010000UL)        /*!<Bit 1 */
+#define  ADC_SQR1_SQ16_2                     (0x00020000UL)        /*!<Bit 2 */
+#define  ADC_SQR1_SQ16_3                     (0x00040000UL)        /*!<Bit 3 */
+#define  ADC_SQR1_SQ16_4                     (0x00080000UL)        /*!<Bit 4 */
+#define  ADC_SQR1_L                          (0x00F00000UL)        /*!<L[3:0] bits (Regular channel sequence length) */
+#define  ADC_SQR1_L_0                        (0x00100000UL)        /*!<Bit 0 */
+#define  ADC_SQR1_L_1                        (0x00200000UL)        /*!<Bit 1 */
+#define  ADC_SQR1_L_2                        (0x00400000UL)        /*!<Bit 2 */
+#define  ADC_SQR1_L_3                        (0x00800000UL)        /*!<Bit 3 */
 
 /*******************  Bit definition for ADC_SQR2 register  *******************/
-#define  ADC_SQR2_SQ7                        ((uint32_t)0x0000001F)        /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
-#define  ADC_SQR2_SQ7_0                      ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ7_1                      ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ7_2                      ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ7_3                      ((uint32_t)0x00000008)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ7_4                      ((uint32_t)0x00000010)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ8                        ((uint32_t)0x000003E0)        /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
-#define  ADC_SQR2_SQ8_0                      ((uint32_t)0x00000020)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ8_1                      ((uint32_t)0x00000040)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ8_2                      ((uint32_t)0x00000080)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ8_3                      ((uint32_t)0x00000100)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ8_4                      ((uint32_t)0x00000200)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ9                        ((uint32_t)0x00007C00)        /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
-#define  ADC_SQR2_SQ9_0                      ((uint32_t)0x00000400)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ9_1                      ((uint32_t)0x00000800)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ9_2                      ((uint32_t)0x00001000)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ9_3                      ((uint32_t)0x00002000)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ9_4                      ((uint32_t)0x00004000)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ10                       ((uint32_t)0x000F8000)        /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
-#define  ADC_SQR2_SQ10_0                     ((uint32_t)0x00008000)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ10_1                     ((uint32_t)0x00010000)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ10_2                     ((uint32_t)0x00020000)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ10_3                     ((uint32_t)0x00040000)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ10_4                     ((uint32_t)0x00080000)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ11                       ((uint32_t)0x01F00000)        /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
-#define  ADC_SQR2_SQ11_0                     ((uint32_t)0x00100000)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ11_1                     ((uint32_t)0x00200000)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ11_2                     ((uint32_t)0x00400000)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ11_3                     ((uint32_t)0x00800000)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ11_4                     ((uint32_t)0x01000000)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ12                       ((uint32_t)0x3E000000)        /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
-#define  ADC_SQR2_SQ12_0                     ((uint32_t)0x02000000)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ12_1                     ((uint32_t)0x04000000)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ12_2                     ((uint32_t)0x08000000)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ12_3                     ((uint32_t)0x10000000)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ12_4                     ((uint32_t)0x20000000)        /*!<Bit 4 */
+#define  ADC_SQR2_SQ7                        (0x0000001FUL)        /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
+#define  ADC_SQR2_SQ7_0                      (0x00000001UL)        /*!<Bit 0 */
+#define  ADC_SQR2_SQ7_1                      (0x00000002UL)        /*!<Bit 1 */
+#define  ADC_SQR2_SQ7_2                      (0x00000004UL)        /*!<Bit 2 */
+#define  ADC_SQR2_SQ7_3                      (0x00000008UL)        /*!<Bit 3 */
+#define  ADC_SQR2_SQ7_4                      (0x00000010UL)        /*!<Bit 4 */
+#define  ADC_SQR2_SQ8                        (0x000003E0UL)        /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
+#define  ADC_SQR2_SQ8_0                      (0x00000020UL)        /*!<Bit 0 */
+#define  ADC_SQR2_SQ8_1                      (0x00000040UL)        /*!<Bit 1 */
+#define  ADC_SQR2_SQ8_2                      (0x00000080UL)        /*!<Bit 2 */
+#define  ADC_SQR2_SQ8_3                      (0x00000100UL)        /*!<Bit 3 */
+#define  ADC_SQR2_SQ8_4                      (0x00000200UL)        /*!<Bit 4 */
+#define  ADC_SQR2_SQ9                        (0x00007C00UL)        /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
+#define  ADC_SQR2_SQ9_0                      (0x00000400UL)        /*!<Bit 0 */
+#define  ADC_SQR2_SQ9_1                      (0x00000800UL)        /*!<Bit 1 */
+#define  ADC_SQR2_SQ9_2                      (0x00001000UL)        /*!<Bit 2 */
+#define  ADC_SQR2_SQ9_3                      (0x00002000UL)        /*!<Bit 3 */
+#define  ADC_SQR2_SQ9_4                      (0x00004000UL)        /*!<Bit 4 */
+#define  ADC_SQR2_SQ10                       (0x000F8000UL)        /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
+#define  ADC_SQR2_SQ10_0                     (0x00008000UL)        /*!<Bit 0 */
+#define  ADC_SQR2_SQ10_1                     (0x00010000UL)        /*!<Bit 1 */
+#define  ADC_SQR2_SQ10_2                     (0x00020000UL)        /*!<Bit 2 */
+#define  ADC_SQR2_SQ10_3                     (0x00040000UL)        /*!<Bit 3 */
+#define  ADC_SQR2_SQ10_4                     (0x00080000UL)        /*!<Bit 4 */
+#define  ADC_SQR2_SQ11                       (0x01F00000UL)        /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
+#define  ADC_SQR2_SQ11_0                     (0x00100000UL)        /*!<Bit 0 */
+#define  ADC_SQR2_SQ11_1                     (0x00200000UL)        /*!<Bit 1 */
+#define  ADC_SQR2_SQ11_2                     (0x00400000UL)        /*!<Bit 2 */
+#define  ADC_SQR2_SQ11_3                     (0x00800000UL)        /*!<Bit 3 */
+#define  ADC_SQR2_SQ11_4                     (0x01000000UL)        /*!<Bit 4 */
+#define  ADC_SQR2_SQ12                       (0x3E000000UL)        /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
+#define  ADC_SQR2_SQ12_0                     (0x02000000UL)        /*!<Bit 0 */
+#define  ADC_SQR2_SQ12_1                     (0x04000000UL)        /*!<Bit 1 */
+#define  ADC_SQR2_SQ12_2                     (0x08000000UL)        /*!<Bit 2 */
+#define  ADC_SQR2_SQ12_3                     (0x10000000UL)        /*!<Bit 3 */
+#define  ADC_SQR2_SQ12_4                     (0x20000000UL)        /*!<Bit 4 */
 
 /*******************  Bit definition for ADC_SQR3 register  *******************/
-#define  ADC_SQR3_SQ1                        ((uint32_t)0x0000001F)        /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
-#define  ADC_SQR3_SQ1_0                      ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ1_1                      ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ1_2                      ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ1_3                      ((uint32_t)0x00000008)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ1_4                      ((uint32_t)0x00000010)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ2                        ((uint32_t)0x000003E0)        /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
-#define  ADC_SQR3_SQ2_0                      ((uint32_t)0x00000020)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ2_1                      ((uint32_t)0x00000040)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ2_2                      ((uint32_t)0x00000080)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ2_3                      ((uint32_t)0x00000100)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ2_4                      ((uint32_t)0x00000200)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ3                        ((uint32_t)0x00007C00)        /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
-#define  ADC_SQR3_SQ3_0                      ((uint32_t)0x00000400)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ3_1                      ((uint32_t)0x00000800)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ3_2                      ((uint32_t)0x00001000)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ3_3                      ((uint32_t)0x00002000)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ3_4                      ((uint32_t)0x00004000)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ4                        ((uint32_t)0x000F8000)        /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
-#define  ADC_SQR3_SQ4_0                      ((uint32_t)0x00008000)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ4_1                      ((uint32_t)0x00010000)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ4_2                      ((uint32_t)0x00020000)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ4_3                      ((uint32_t)0x00040000)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ4_4                      ((uint32_t)0x00080000)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ5                        ((uint32_t)0x01F00000)        /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
-#define  ADC_SQR3_SQ5_0                      ((uint32_t)0x00100000)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ5_1                      ((uint32_t)0x00200000)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ5_2                      ((uint32_t)0x00400000)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ5_3                      ((uint32_t)0x00800000)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ5_4                      ((uint32_t)0x01000000)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ6                        ((uint32_t)0x3E000000)        /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
-#define  ADC_SQR3_SQ6_0                      ((uint32_t)0x02000000)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ6_1                      ((uint32_t)0x04000000)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ6_2                      ((uint32_t)0x08000000)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ6_3                      ((uint32_t)0x10000000)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ6_4                      ((uint32_t)0x20000000)        /*!<Bit 4 */
+#define  ADC_SQR3_SQ1                        (0x0000001FUL)        /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
+#define  ADC_SQR3_SQ1_0                      (0x00000001UL)        /*!<Bit 0 */
+#define  ADC_SQR3_SQ1_1                      (0x00000002UL)        /*!<Bit 1 */
+#define  ADC_SQR3_SQ1_2                      (0x00000004UL)        /*!<Bit 2 */
+#define  ADC_SQR3_SQ1_3                      (0x00000008UL)        /*!<Bit 3 */
+#define  ADC_SQR3_SQ1_4                      (0x00000010UL)        /*!<Bit 4 */
+#define  ADC_SQR3_SQ2                        (0x000003E0UL)        /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define  ADC_SQR3_SQ2_0                      (0x00000020UL)        /*!<Bit 0 */
+#define  ADC_SQR3_SQ2_1                      (0x00000040UL)        /*!<Bit 1 */
+#define  ADC_SQR3_SQ2_2                      (0x00000080UL)        /*!<Bit 2 */
+#define  ADC_SQR3_SQ2_3                      (0x00000100UL)        /*!<Bit 3 */
+#define  ADC_SQR3_SQ2_4                      (0x00000200UL)        /*!<Bit 4 */
+#define  ADC_SQR3_SQ3                        (0x00007C00UL)        /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define  ADC_SQR3_SQ3_0                      (0x00000400UL)        /*!<Bit 0 */
+#define  ADC_SQR3_SQ3_1                      (0x00000800UL)        /*!<Bit 1 */
+#define  ADC_SQR3_SQ3_2                      (0x00001000UL)        /*!<Bit 2 */
+#define  ADC_SQR3_SQ3_3                      (0x00002000UL)        /*!<Bit 3 */
+#define  ADC_SQR3_SQ3_4                      (0x00004000UL)        /*!<Bit 4 */
+#define  ADC_SQR3_SQ4                        (0x000F8000UL)        /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
+#define  ADC_SQR3_SQ4_0                      (0x00008000UL)        /*!<Bit 0 */
+#define  ADC_SQR3_SQ4_1                      (0x00010000UL)        /*!<Bit 1 */
+#define  ADC_SQR3_SQ4_2                      (0x00020000UL)        /*!<Bit 2 */
+#define  ADC_SQR3_SQ4_3                      (0x00040000UL)        /*!<Bit 3 */
+#define  ADC_SQR3_SQ4_4                      (0x00080000UL)        /*!<Bit 4 */
+#define  ADC_SQR3_SQ5                        (0x01F00000UL)        /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
+#define  ADC_SQR3_SQ5_0                      (0x00100000UL)        /*!<Bit 0 */
+#define  ADC_SQR3_SQ5_1                      (0x00200000UL)        /*!<Bit 1 */
+#define  ADC_SQR3_SQ5_2                      (0x00400000UL)        /*!<Bit 2 */
+#define  ADC_SQR3_SQ5_3                      (0x00800000UL)        /*!<Bit 3 */
+#define  ADC_SQR3_SQ5_4                      (0x01000000UL)        /*!<Bit 4 */
+#define  ADC_SQR3_SQ6                        (0x3E000000UL)        /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
+#define  ADC_SQR3_SQ6_0                      (0x02000000UL)        /*!<Bit 0 */
+#define  ADC_SQR3_SQ6_1                      (0x04000000UL)        /*!<Bit 1 */
+#define  ADC_SQR3_SQ6_2                      (0x08000000UL)        /*!<Bit 2 */
+#define  ADC_SQR3_SQ6_3                      (0x10000000UL)        /*!<Bit 3 */
+#define  ADC_SQR3_SQ6_4                      (0x20000000UL)        /*!<Bit 4 */
 
 /*******************  Bit definition for ADC_JSQR register  *******************/
-#define  ADC_JSQR_JSQ1                       ((uint32_t)0x0000001F)        /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
-#define  ADC_JSQR_JSQ1_0                     ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ1_1                     ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ1_2                     ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ1_3                     ((uint32_t)0x00000008)        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ1_4                     ((uint32_t)0x00000010)        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ2                       ((uint32_t)0x000003E0)        /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ2_0                     ((uint32_t)0x00000020)        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ2_1                     ((uint32_t)0x00000040)        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ2_2                     ((uint32_t)0x00000080)        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ2_3                     ((uint32_t)0x00000100)        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ2_4                     ((uint32_t)0x00000200)        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ3                       ((uint32_t)0x00007C00)        /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ3_0                     ((uint32_t)0x00000400)        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ3_1                     ((uint32_t)0x00000800)        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ3_2                     ((uint32_t)0x00001000)        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ3_3                     ((uint32_t)0x00002000)        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ3_4                     ((uint32_t)0x00004000)        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ4                       ((uint32_t)0x000F8000)        /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
-#define  ADC_JSQR_JSQ4_0                     ((uint32_t)0x00008000)        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ4_1                     ((uint32_t)0x00010000)        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ4_2                     ((uint32_t)0x00020000)        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ4_3                     ((uint32_t)0x00040000)        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ4_4                     ((uint32_t)0x00080000)        /*!<Bit 4 */
-#define  ADC_JSQR_JL                         ((uint32_t)0x00300000)        /*!<JL[1:0] bits (Injected Sequence length) */
-#define  ADC_JSQR_JL_0                       ((uint32_t)0x00100000)        /*!<Bit 0 */
-#define  ADC_JSQR_JL_1                       ((uint32_t)0x00200000)        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ1                       (0x0000001FUL)        /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
+#define  ADC_JSQR_JSQ1_0                     (0x00000001UL)        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ1_1                     (0x00000002UL)        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ1_2                     (0x00000004UL)        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ1_3                     (0x00000008UL)        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ1_4                     (0x00000010UL)        /*!<Bit 4 */
+#define  ADC_JSQR_JSQ2                       (0x000003E0UL)        /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define  ADC_JSQR_JSQ2_0                     (0x00000020UL)        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ2_1                     (0x00000040UL)        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ2_2                     (0x00000080UL)        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ2_3                     (0x00000100UL)        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ2_4                     (0x00000200UL)        /*!<Bit 4 */
+#define  ADC_JSQR_JSQ3                       (0x00007C00UL)        /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define  ADC_JSQR_JSQ3_0                     (0x00000400UL)        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ3_1                     (0x00000800UL)        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ3_2                     (0x00001000UL)        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ3_3                     (0x00002000UL)        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ3_4                     (0x00004000UL)        /*!<Bit 4 */
+#define  ADC_JSQR_JSQ4                       (0x000F8000UL)        /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define  ADC_JSQR_JSQ4_0                     (0x00008000UL)        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ4_1                     (0x00010000UL)        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ4_2                     (0x00020000UL)        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ4_3                     (0x00040000UL)        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ4_4                     (0x00080000UL)        /*!<Bit 4 */
+#define  ADC_JSQR_JL                         (0x00300000UL)        /*!<JL[1:0] bits (Injected Sequence length) */
+#define  ADC_JSQR_JL_0                       (0x00100000UL)        /*!<Bit 0 */
+#define  ADC_JSQR_JL_1                       (0x00200000UL)        /*!<Bit 1 */
 
 /*******************  Bit definition for ADC_JDR1 register  *******************/
-#define  ADC_JDR1_JDATA                      ((uint32_t)0xFFFF)            /*!<Injected data */
+#define  ADC_JDR1_JDATA                      (0xFFFFUL)            /*!<Injected data */
 
 /*******************  Bit definition for ADC_JDR2 register  *******************/
-#define  ADC_JDR2_JDATA                      ((uint32_t)0xFFFF)            /*!<Injected data */
+#define  ADC_JDR2_JDATA                      (0xFFFFUL)            /*!<Injected data */
 
 /*******************  Bit definition for ADC_JDR3 register  *******************/
-#define  ADC_JDR3_JDATA                      ((uint32_t)0xFFFF)            /*!<Injected data */
+#define  ADC_JDR3_JDATA                      (0xFFFFUL)            /*!<Injected data */
 
 /*******************  Bit definition for ADC_JDR4 register  *******************/
-#define  ADC_JDR4_JDATA                      ((uint32_t)0xFFFF)            /*!<Injected data */
+#define  ADC_JDR4_JDATA                      (0xFFFFUL)            /*!<Injected data */
 
 /********************  Bit definition for ADC_DR register  ********************/
-#define  ADC_DR_DATA                         ((uint32_t)0x0000FFFF)        /*!<Regular data */
-#define  ADC_DR_ADC2DATA                     ((uint32_t)0xFFFF0000)        /*!<ADC2 data */
+#define  ADC_DR_DATA                         (0x0000FFFFUL)        /*!<Regular data */
+#define  ADC_DR_ADC2DATA                     (0xFFFF0000UL)        /*!<ADC2 data */
 
 /*******************  Bit definition for ADC_CSR register  ********************/
-#define  ADC_CSR_AWD1                        ((uint32_t)0x00000001)        /*!<ADC1 Analog watchdog flag */
-#define  ADC_CSR_EOC1                        ((uint32_t)0x00000002)        /*!<ADC1 End of conversion */
-#define  ADC_CSR_JEOC1                       ((uint32_t)0x00000004)        /*!<ADC1 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT1                      ((uint32_t)0x00000008)        /*!<ADC1 Injected channel Start flag */
-#define  ADC_CSR_STRT1                       ((uint32_t)0x00000010)        /*!<ADC1 Regular channel Start flag */
-#define  ADC_CSR_DOVR1                       ((uint32_t)0x00000020)        /*!<ADC1 DMA overrun  flag */
-#define  ADC_CSR_AWD2                        ((uint32_t)0x00000100)        /*!<ADC2 Analog watchdog flag */
-#define  ADC_CSR_EOC2                        ((uint32_t)0x00000200)        /*!<ADC2 End of conversion */
-#define  ADC_CSR_JEOC2                       ((uint32_t)0x00000400)        /*!<ADC2 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT2                      ((uint32_t)0x00000800)        /*!<ADC2 Injected channel Start flag */
-#define  ADC_CSR_STRT2                       ((uint32_t)0x00001000)        /*!<ADC2 Regular channel Start flag */
-#define  ADC_CSR_DOVR2                       ((uint32_t)0x00002000)        /*!<ADC2 DMA overrun  flag */
-#define  ADC_CSR_AWD3                        ((uint32_t)0x00010000)        /*!<ADC3 Analog watchdog flag */
-#define  ADC_CSR_EOC3                        ((uint32_t)0x00020000)        /*!<ADC3 End of conversion */
-#define  ADC_CSR_JEOC3                       ((uint32_t)0x00040000)        /*!<ADC3 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT3                      ((uint32_t)0x00080000)        /*!<ADC3 Injected channel Start flag */
-#define  ADC_CSR_STRT3                       ((uint32_t)0x00100000)        /*!<ADC3 Regular channel Start flag */
-#define  ADC_CSR_DOVR3                       ((uint32_t)0x00200000)        /*!<ADC3 DMA overrun  flag */
+#define  ADC_CSR_AWD1                        (0x00000001UL)        /*!<ADC1 Analog watchdog flag */
+#define  ADC_CSR_EOC1                        (0x00000002UL)        /*!<ADC1 End of conversion */
+#define  ADC_CSR_JEOC1                       (0x00000004UL)        /*!<ADC1 Injected channel end of conversion */
+#define  ADC_CSR_JSTRT1                      (0x00000008UL)        /*!<ADC1 Injected channel Start flag */
+#define  ADC_CSR_STRT1                       (0x00000010UL)        /*!<ADC1 Regular channel Start flag */
+#define  ADC_CSR_DOVR1                       (0x00000020UL)        /*!<ADC1 DMA overrun  flag */
+#define  ADC_CSR_AWD2                        (0x00000100UL)        /*!<ADC2 Analog watchdog flag */
+#define  ADC_CSR_EOC2                        (0x00000200UL)        /*!<ADC2 End of conversion */
+#define  ADC_CSR_JEOC2                       (0x00000400UL)        /*!<ADC2 Injected channel end of conversion */
+#define  ADC_CSR_JSTRT2                      (0x00000800UL)        /*!<ADC2 Injected channel Start flag */
+#define  ADC_CSR_STRT2                       (0x00001000UL)        /*!<ADC2 Regular channel Start flag */
+#define  ADC_CSR_DOVR2                       (0x00002000UL)        /*!<ADC2 DMA overrun  flag */
+#define  ADC_CSR_AWD3                        (0x00010000UL)        /*!<ADC3 Analog watchdog flag */
+#define  ADC_CSR_EOC3                        (0x00020000UL)        /*!<ADC3 End of conversion */
+#define  ADC_CSR_JEOC3                       (0x00040000UL)        /*!<ADC3 Injected channel end of conversion */
+#define  ADC_CSR_JSTRT3                      (0x00080000UL)        /*!<ADC3 Injected channel Start flag */
+#define  ADC_CSR_STRT3                       (0x00100000UL)        /*!<ADC3 Regular channel Start flag */
+#define  ADC_CSR_DOVR3                       (0x00200000UL)        /*!<ADC3 DMA overrun  flag */
 
 /*******************  Bit definition for ADC_CCR register  ********************/
-#define  ADC_CCR_MULTI                       ((uint32_t)0x0000001F)        /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
-#define  ADC_CCR_MULTI_0                     ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  ADC_CCR_MULTI_1                     ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  ADC_CCR_MULTI_2                     ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  ADC_CCR_MULTI_3                     ((uint32_t)0x00000008)        /*!<Bit 3 */
-#define  ADC_CCR_MULTI_4                     ((uint32_t)0x00000010)        /*!<Bit 4 */
-#define  ADC_CCR_DELAY                       ((uint32_t)0x00000F00)        /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
-#define  ADC_CCR_DELAY_0                     ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  ADC_CCR_DELAY_1                     ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  ADC_CCR_DELAY_2                     ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  ADC_CCR_DELAY_3                     ((uint32_t)0x00000800)        /*!<Bit 3 */
-#define  ADC_CCR_DDS                         ((uint32_t)0x00002000)        /*!<DMA disable selection (Multi-ADC mode) */
-#define  ADC_CCR_DMA                         ((uint32_t)0x0000C000)        /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
-#define  ADC_CCR_DMA_0                       ((uint32_t)0x00004000)        /*!<Bit 0 */
-#define  ADC_CCR_DMA_1                       ((uint32_t)0x00008000)        /*!<Bit 1 */
-#define  ADC_CCR_ADCPRE                      ((uint32_t)0x00030000)        /*!<ADCPRE[1:0] bits (ADC prescaler) */
-#define  ADC_CCR_ADCPRE_0                    ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  ADC_CCR_ADCPRE_1                    ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  ADC_CCR_VBATE                       ((uint32_t)0x00400000)        /*!<VBAT Enable */
-#define  ADC_CCR_TSVREFE                     ((uint32_t)0x00800000)        /*!<Temperature Sensor and VREFINT Enable */
+#define  ADC_CCR_MULTI                       (0x0000001FUL)        /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
+#define  ADC_CCR_MULTI_0                     (0x00000001UL)        /*!<Bit 0 */
+#define  ADC_CCR_MULTI_1                     (0x00000002UL)        /*!<Bit 1 */
+#define  ADC_CCR_MULTI_2                     (0x00000004UL)        /*!<Bit 2 */
+#define  ADC_CCR_MULTI_3                     (0x00000008UL)        /*!<Bit 3 */
+#define  ADC_CCR_MULTI_4                     (0x00000010UL)        /*!<Bit 4 */
+#define  ADC_CCR_DELAY                       (0x00000F00UL)        /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
+#define  ADC_CCR_DELAY_0                     (0x00000100UL)        /*!<Bit 0 */
+#define  ADC_CCR_DELAY_1                     (0x00000200UL)        /*!<Bit 1 */
+#define  ADC_CCR_DELAY_2                     (0x00000400UL)        /*!<Bit 2 */
+#define  ADC_CCR_DELAY_3                     (0x00000800UL)        /*!<Bit 3 */
+#define  ADC_CCR_DDS                         (0x00002000UL)        /*!<DMA disable selection (Multi-ADC mode) */
+#define  ADC_CCR_DMA                         (0x0000C000UL)        /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
+#define  ADC_CCR_DMA_0                       (0x00004000UL)        /*!<Bit 0 */
+#define  ADC_CCR_DMA_1                       (0x00008000UL)        /*!<Bit 1 */
+#define  ADC_CCR_ADCPRE                      (0x00030000UL)        /*!<ADCPRE[1:0] bits (ADC prescaler) */
+#define  ADC_CCR_ADCPRE_0                    (0x00010000UL)        /*!<Bit 0 */
+#define  ADC_CCR_ADCPRE_1                    (0x00020000UL)        /*!<Bit 1 */
+#define  ADC_CCR_VBATE                       (0x00400000UL)        /*!<VBAT Enable */
+#define  ADC_CCR_TSVREFE                     (0x00800000UL)        /*!<Temperature Sensor and VREFINT Enable */
 
 /*******************  Bit definition for ADC_CDR register  ********************/
-#define  ADC_CDR_DATA1                      ((uint32_t)0x0000FFFF)         /*!<1st data of a pair of regular conversions */
-#define  ADC_CDR_DATA2                      ((uint32_t)0xFFFF0000)         /*!<2nd data of a pair of regular conversions */
+#define  ADC_CDR_DATA1                      (0x0000FFFFUL)         /*!<1st data of a pair of regular conversions */
+#define  ADC_CDR_DATA2                      (0xFFFF0000UL)         /*!<2nd data of a pair of regular conversions */
 
 /******************************************************************************/
 /*                                                                            */
@@ -1284,15 +1280,15 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for CRC_DR register  *********************/
-#define  CRC_DR_DR                           ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
+#define  CRC_DR_DR                           (0xFFFFFFFFUL) /*!< Data register bits */
 
 
 /*******************  Bit definition for CRC_IDR register  ********************/
-#define  CRC_IDR_IDR                         ((uint32_t)0xFF)        /*!< General-purpose 8-bit data register bits */
+#define  CRC_IDR_IDR                         (0xFFUL)        /*!< General-purpose 8-bit data register bits */
 
 
 /********************  Bit definition for CRC_CR register  ********************/
-#define  CRC_CR_RESET                        ((uint32_t)0x01)        /*!< RESET bit */
+#define  CRC_CR_RESET                        (0x01UL)        /*!< RESET bit */
 
 /******************************************************************************/
 /*                                                                            */
@@ -1306,159 +1302,159 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bits definition for DMA_SxCR register  *****************/
-#define DMA_SxCR_CHSEL                       ((uint32_t)0x0E000000)
-#define DMA_SxCR_CHSEL_0                     ((uint32_t)0x02000000)
-#define DMA_SxCR_CHSEL_1                     ((uint32_t)0x04000000)
-#define DMA_SxCR_CHSEL_2                     ((uint32_t)0x08000000)
-#define DMA_SxCR_MBURST                      ((uint32_t)0x01800000)
-#define DMA_SxCR_MBURST_0                    ((uint32_t)0x00800000)
-#define DMA_SxCR_MBURST_1                    ((uint32_t)0x01000000)
-#define DMA_SxCR_PBURST                      ((uint32_t)0x00600000)
-#define DMA_SxCR_PBURST_0                    ((uint32_t)0x00200000)
-#define DMA_SxCR_PBURST_1                    ((uint32_t)0x00400000)
-#define DMA_SxCR_ACK                         ((uint32_t)0x00100000)
-#define DMA_SxCR_CT                          ((uint32_t)0x00080000)
-#define DMA_SxCR_DBM                         ((uint32_t)0x00040000)
-#define DMA_SxCR_PL                          ((uint32_t)0x00030000)
-#define DMA_SxCR_PL_0                        ((uint32_t)0x00010000)
-#define DMA_SxCR_PL_1                        ((uint32_t)0x00020000)
-#define DMA_SxCR_PINCOS                      ((uint32_t)0x00008000)
-#define DMA_SxCR_MSIZE                       ((uint32_t)0x00006000)
-#define DMA_SxCR_MSIZE_0                     ((uint32_t)0x00002000)
-#define DMA_SxCR_MSIZE_1                     ((uint32_t)0x00004000)
-#define DMA_SxCR_PSIZE                       ((uint32_t)0x00001800)
-#define DMA_SxCR_PSIZE_0                     ((uint32_t)0x00000800)
-#define DMA_SxCR_PSIZE_1                     ((uint32_t)0x00001000)
-#define DMA_SxCR_MINC                        ((uint32_t)0x00000400)
-#define DMA_SxCR_PINC                        ((uint32_t)0x00000200)
-#define DMA_SxCR_CIRC                        ((uint32_t)0x00000100)
-#define DMA_SxCR_DIR                         ((uint32_t)0x000000C0)
-#define DMA_SxCR_DIR_0                       ((uint32_t)0x00000040)
-#define DMA_SxCR_DIR_1                       ((uint32_t)0x00000080)
-#define DMA_SxCR_PFCTRL                      ((uint32_t)0x00000020)
-#define DMA_SxCR_TCIE                        ((uint32_t)0x00000010)
-#define DMA_SxCR_HTIE                        ((uint32_t)0x00000008)
-#define DMA_SxCR_TEIE                        ((uint32_t)0x00000004)
-#define DMA_SxCR_DMEIE                       ((uint32_t)0x00000002)
-#define DMA_SxCR_EN                          ((uint32_t)0x00000001)
+#define DMA_SxCR_CHSEL                       (0x0E000000UL)
+#define DMA_SxCR_CHSEL_0                     (0x02000000UL)
+#define DMA_SxCR_CHSEL_1                     (0x04000000UL)
+#define DMA_SxCR_CHSEL_2                     (0x08000000UL)
+#define DMA_SxCR_MBURST                      (0x01800000UL)
+#define DMA_SxCR_MBURST_0                    (0x00800000UL)
+#define DMA_SxCR_MBURST_1                    (0x01000000UL)
+#define DMA_SxCR_PBURST                      (0x00600000UL)
+#define DMA_SxCR_PBURST_0                    (0x00200000UL)
+#define DMA_SxCR_PBURST_1                    (0x00400000UL)
+#define DMA_SxCR_ACK                         (0x00100000UL)
+#define DMA_SxCR_CT                          (0x00080000UL)
+#define DMA_SxCR_DBM                         (0x00040000UL)
+#define DMA_SxCR_PL                          (0x00030000UL)
+#define DMA_SxCR_PL_0                        (0x00010000UL)
+#define DMA_SxCR_PL_1                        (0x00020000UL)
+#define DMA_SxCR_PINCOS                      (0x00008000UL)
+#define DMA_SxCR_MSIZE                       (0x00006000UL)
+#define DMA_SxCR_MSIZE_0                     (0x00002000UL)
+#define DMA_SxCR_MSIZE_1                     (0x00004000UL)
+#define DMA_SxCR_PSIZE                       (0x00001800UL)
+#define DMA_SxCR_PSIZE_0                     (0x00000800UL)
+#define DMA_SxCR_PSIZE_1                     (0x00001000UL)
+#define DMA_SxCR_MINC                        (0x00000400UL)
+#define DMA_SxCR_PINC                        (0x00000200UL)
+#define DMA_SxCR_CIRC                        (0x00000100UL)
+#define DMA_SxCR_DIR                         (0x000000C0UL)
+#define DMA_SxCR_DIR_0                       (0x00000040UL)
+#define DMA_SxCR_DIR_1                       (0x00000080UL)
+#define DMA_SxCR_PFCTRL                      (0x00000020UL)
+#define DMA_SxCR_TCIE                        (0x00000010UL)
+#define DMA_SxCR_HTIE                        (0x00000008UL)
+#define DMA_SxCR_TEIE                        (0x00000004UL)
+#define DMA_SxCR_DMEIE                       (0x00000002UL)
+#define DMA_SxCR_EN                          (0x00000001UL)
 
 /********************  Bits definition for DMA_SxCNDTR register  **************/
-#define DMA_SxNDT                            ((uint32_t)0x0000FFFF)
-#define DMA_SxNDT_0                          ((uint32_t)0x00000001)
-#define DMA_SxNDT_1                          ((uint32_t)0x00000002)
-#define DMA_SxNDT_2                          ((uint32_t)0x00000004)
-#define DMA_SxNDT_3                          ((uint32_t)0x00000008)
-#define DMA_SxNDT_4                          ((uint32_t)0x00000010)
-#define DMA_SxNDT_5                          ((uint32_t)0x00000020)
-#define DMA_SxNDT_6                          ((uint32_t)0x00000040)
-#define DMA_SxNDT_7                          ((uint32_t)0x00000080)
-#define DMA_SxNDT_8                          ((uint32_t)0x00000100)
-#define DMA_SxNDT_9                          ((uint32_t)0x00000200)
-#define DMA_SxNDT_10                         ((uint32_t)0x00000400)
-#define DMA_SxNDT_11                         ((uint32_t)0x00000800)
-#define DMA_SxNDT_12                         ((uint32_t)0x00001000)
-#define DMA_SxNDT_13                         ((uint32_t)0x00002000)
-#define DMA_SxNDT_14                         ((uint32_t)0x00004000)
-#define DMA_SxNDT_15                         ((uint32_t)0x00008000)
+#define DMA_SxNDT                            (0x0000FFFFUL)
+#define DMA_SxNDT_0                          (0x00000001UL)
+#define DMA_SxNDT_1                          (0x00000002UL)
+#define DMA_SxNDT_2                          (0x00000004UL)
+#define DMA_SxNDT_3                          (0x00000008UL)
+#define DMA_SxNDT_4                          (0x00000010UL)
+#define DMA_SxNDT_5                          (0x00000020UL)
+#define DMA_SxNDT_6                          (0x00000040UL)
+#define DMA_SxNDT_7                          (0x00000080UL)
+#define DMA_SxNDT_8                          (0x00000100UL)
+#define DMA_SxNDT_9                          (0x00000200UL)
+#define DMA_SxNDT_10                         (0x00000400UL)
+#define DMA_SxNDT_11                         (0x00000800UL)
+#define DMA_SxNDT_12                         (0x00001000UL)
+#define DMA_SxNDT_13                         (0x00002000UL)
+#define DMA_SxNDT_14                         (0x00004000UL)
+#define DMA_SxNDT_15                         (0x00008000UL)
 
 /********************  Bits definition for DMA_SxFCR register  ****************/
-#define DMA_SxFCR_FEIE                       ((uint32_t)0x00000080)
-#define DMA_SxFCR_FS                         ((uint32_t)0x00000038)
-#define DMA_SxFCR_FS_0                       ((uint32_t)0x00000008)
-#define DMA_SxFCR_FS_1                       ((uint32_t)0x00000010)
-#define DMA_SxFCR_FS_2                       ((uint32_t)0x00000020)
-#define DMA_SxFCR_DMDIS                      ((uint32_t)0x00000004)
-#define DMA_SxFCR_FTH                        ((uint32_t)0x00000003)
-#define DMA_SxFCR_FTH_0                      ((uint32_t)0x00000001)
-#define DMA_SxFCR_FTH_1                      ((uint32_t)0x00000002)
+#define DMA_SxFCR_FEIE                       (0x00000080UL)
+#define DMA_SxFCR_FS                         (0x00000038UL)
+#define DMA_SxFCR_FS_0                       (0x00000008UL)
+#define DMA_SxFCR_FS_1                       (0x00000010UL)
+#define DMA_SxFCR_FS_2                       (0x00000020UL)
+#define DMA_SxFCR_DMDIS                      (0x00000004UL)
+#define DMA_SxFCR_FTH                        (0x00000003UL)
+#define DMA_SxFCR_FTH_0                      (0x00000001UL)
+#define DMA_SxFCR_FTH_1                      (0x00000002UL)
 
 /********************  Bits definition for DMA_LISR register  *****************/
-#define DMA_LISR_TCIF3                       ((uint32_t)0x08000000)
-#define DMA_LISR_HTIF3                       ((uint32_t)0x04000000)
-#define DMA_LISR_TEIF3                       ((uint32_t)0x02000000)
-#define DMA_LISR_DMEIF3                      ((uint32_t)0x01000000)
-#define DMA_LISR_FEIF3                       ((uint32_t)0x00400000)
-#define DMA_LISR_TCIF2                       ((uint32_t)0x00200000)
-#define DMA_LISR_HTIF2                       ((uint32_t)0x00100000)
-#define DMA_LISR_TEIF2                       ((uint32_t)0x00080000)
-#define DMA_LISR_DMEIF2                      ((uint32_t)0x00040000)
-#define DMA_LISR_FEIF2                       ((uint32_t)0x00010000)
-#define DMA_LISR_TCIF1                       ((uint32_t)0x00000800)
-#define DMA_LISR_HTIF1                       ((uint32_t)0x00000400)
-#define DMA_LISR_TEIF1                       ((uint32_t)0x00000200)
-#define DMA_LISR_DMEIF1                      ((uint32_t)0x00000100)
-#define DMA_LISR_FEIF1                       ((uint32_t)0x00000040)
-#define DMA_LISR_TCIF0                       ((uint32_t)0x00000020)
-#define DMA_LISR_HTIF0                       ((uint32_t)0x00000010)
-#define DMA_LISR_TEIF0                       ((uint32_t)0x00000008)
-#define DMA_LISR_DMEIF0                      ((uint32_t)0x00000004)
-#define DMA_LISR_FEIF0                       ((uint32_t)0x00000001)
+#define DMA_LISR_TCIF3                       (0x08000000UL)
+#define DMA_LISR_HTIF3                       (0x04000000UL)
+#define DMA_LISR_TEIF3                       (0x02000000UL)
+#define DMA_LISR_DMEIF3                      (0x01000000UL)
+#define DMA_LISR_FEIF3                       (0x00400000UL)
+#define DMA_LISR_TCIF2                       (0x00200000UL)
+#define DMA_LISR_HTIF2                       (0x00100000UL)
+#define DMA_LISR_TEIF2                       (0x00080000UL)
+#define DMA_LISR_DMEIF2                      (0x00040000UL)
+#define DMA_LISR_FEIF2                       (0x00010000UL)
+#define DMA_LISR_TCIF1                       (0x00000800UL)
+#define DMA_LISR_HTIF1                       (0x00000400UL)
+#define DMA_LISR_TEIF1                       (0x00000200UL)
+#define DMA_LISR_DMEIF1                      (0x00000100UL)
+#define DMA_LISR_FEIF1                       (0x00000040UL)
+#define DMA_LISR_TCIF0                       (0x00000020UL)
+#define DMA_LISR_HTIF0                       (0x00000010UL)
+#define DMA_LISR_TEIF0                       (0x00000008UL)
+#define DMA_LISR_DMEIF0                      (0x00000004UL)
+#define DMA_LISR_FEIF0                       (0x00000001UL)
 
 /********************  Bits definition for DMA_HISR register  *****************/
-#define DMA_HISR_TCIF7                       ((uint32_t)0x08000000)
-#define DMA_HISR_HTIF7                       ((uint32_t)0x04000000)
-#define DMA_HISR_TEIF7                       ((uint32_t)0x02000000)
-#define DMA_HISR_DMEIF7                      ((uint32_t)0x01000000)
-#define DMA_HISR_FEIF7                       ((uint32_t)0x00400000)
-#define DMA_HISR_TCIF6                       ((uint32_t)0x00200000)
-#define DMA_HISR_HTIF6                       ((uint32_t)0x00100000)
-#define DMA_HISR_TEIF6                       ((uint32_t)0x00080000)
-#define DMA_HISR_DMEIF6                      ((uint32_t)0x00040000)
-#define DMA_HISR_FEIF6                       ((uint32_t)0x00010000)
-#define DMA_HISR_TCIF5                       ((uint32_t)0x00000800)
-#define DMA_HISR_HTIF5                       ((uint32_t)0x00000400)
-#define DMA_HISR_TEIF5                       ((uint32_t)0x00000200)
-#define DMA_HISR_DMEIF5                      ((uint32_t)0x00000100)
-#define DMA_HISR_FEIF5                       ((uint32_t)0x00000040)
-#define DMA_HISR_TCIF4                       ((uint32_t)0x00000020)
-#define DMA_HISR_HTIF4                       ((uint32_t)0x00000010)
-#define DMA_HISR_TEIF4                       ((uint32_t)0x00000008)
-#define DMA_HISR_DMEIF4                      ((uint32_t)0x00000004)
-#define DMA_HISR_FEIF4                       ((uint32_t)0x00000001)
+#define DMA_HISR_TCIF7                       (0x08000000UL)
+#define DMA_HISR_HTIF7                       (0x04000000UL)
+#define DMA_HISR_TEIF7                       (0x02000000UL)
+#define DMA_HISR_DMEIF7                      (0x01000000UL)
+#define DMA_HISR_FEIF7                       (0x00400000UL)
+#define DMA_HISR_TCIF6                       (0x00200000UL)
+#define DMA_HISR_HTIF6                       (0x00100000UL)
+#define DMA_HISR_TEIF6                       (0x00080000UL)
+#define DMA_HISR_DMEIF6                      (0x00040000UL)
+#define DMA_HISR_FEIF6                       (0x00010000UL)
+#define DMA_HISR_TCIF5                       (0x00000800UL)
+#define DMA_HISR_HTIF5                       (0x00000400UL)
+#define DMA_HISR_TEIF5                       (0x00000200UL)
+#define DMA_HISR_DMEIF5                      (0x00000100UL)
+#define DMA_HISR_FEIF5                       (0x00000040UL)
+#define DMA_HISR_TCIF4                       (0x00000020UL)
+#define DMA_HISR_HTIF4                       (0x00000010UL)
+#define DMA_HISR_TEIF4                       (0x00000008UL)
+#define DMA_HISR_DMEIF4                      (0x00000004UL)
+#define DMA_HISR_FEIF4                       (0x00000001UL)
 
 /********************  Bits definition for DMA_LIFCR register  ****************/
-#define DMA_LIFCR_CTCIF3                     ((uint32_t)0x08000000)
-#define DMA_LIFCR_CHTIF3                     ((uint32_t)0x04000000)
-#define DMA_LIFCR_CTEIF3                     ((uint32_t)0x02000000)
-#define DMA_LIFCR_CDMEIF3                    ((uint32_t)0x01000000)
-#define DMA_LIFCR_CFEIF3                     ((uint32_t)0x00400000)
-#define DMA_LIFCR_CTCIF2                     ((uint32_t)0x00200000)
-#define DMA_LIFCR_CHTIF2                     ((uint32_t)0x00100000)
-#define DMA_LIFCR_CTEIF2                     ((uint32_t)0x00080000)
-#define DMA_LIFCR_CDMEIF2                    ((uint32_t)0x00040000)
-#define DMA_LIFCR_CFEIF2                     ((uint32_t)0x00010000)
-#define DMA_LIFCR_CTCIF1                     ((uint32_t)0x00000800)
-#define DMA_LIFCR_CHTIF1                     ((uint32_t)0x00000400)
-#define DMA_LIFCR_CTEIF1                     ((uint32_t)0x00000200)
-#define DMA_LIFCR_CDMEIF1                    ((uint32_t)0x00000100)
-#define DMA_LIFCR_CFEIF1                     ((uint32_t)0x00000040)
-#define DMA_LIFCR_CTCIF0                     ((uint32_t)0x00000020)
-#define DMA_LIFCR_CHTIF0                     ((uint32_t)0x00000010)
-#define DMA_LIFCR_CTEIF0                     ((uint32_t)0x00000008)
-#define DMA_LIFCR_CDMEIF0                    ((uint32_t)0x00000004)
-#define DMA_LIFCR_CFEIF0                     ((uint32_t)0x00000001)
+#define DMA_LIFCR_CTCIF3                     (0x08000000UL)
+#define DMA_LIFCR_CHTIF3                     (0x04000000UL)
+#define DMA_LIFCR_CTEIF3                     (0x02000000UL)
+#define DMA_LIFCR_CDMEIF3                    (0x01000000UL)
+#define DMA_LIFCR_CFEIF3                     (0x00400000UL)
+#define DMA_LIFCR_CTCIF2                     (0x00200000UL)
+#define DMA_LIFCR_CHTIF2                     (0x00100000UL)
+#define DMA_LIFCR_CTEIF2                     (0x00080000UL)
+#define DMA_LIFCR_CDMEIF2                    (0x00040000UL)
+#define DMA_LIFCR_CFEIF2                     (0x00010000UL)
+#define DMA_LIFCR_CTCIF1                     (0x00000800UL)
+#define DMA_LIFCR_CHTIF1                     (0x00000400UL)
+#define DMA_LIFCR_CTEIF1                     (0x00000200UL)
+#define DMA_LIFCR_CDMEIF1                    (0x00000100UL)
+#define DMA_LIFCR_CFEIF1                     (0x00000040UL)
+#define DMA_LIFCR_CTCIF0                     (0x00000020UL)
+#define DMA_LIFCR_CHTIF0                     (0x00000010UL)
+#define DMA_LIFCR_CTEIF0                     (0x00000008UL)
+#define DMA_LIFCR_CDMEIF0                    (0x00000004UL)
+#define DMA_LIFCR_CFEIF0                     (0x00000001UL)
 
 /********************  Bits definition for DMA_HIFCR  register  ****************/
-#define DMA_HIFCR_CTCIF7                     ((uint32_t)0x08000000)
-#define DMA_HIFCR_CHTIF7                     ((uint32_t)0x04000000)
-#define DMA_HIFCR_CTEIF7                     ((uint32_t)0x02000000)
-#define DMA_HIFCR_CDMEIF7                    ((uint32_t)0x01000000)
-#define DMA_HIFCR_CFEIF7                     ((uint32_t)0x00400000)
-#define DMA_HIFCR_CTCIF6                     ((uint32_t)0x00200000)
-#define DMA_HIFCR_CHTIF6                     ((uint32_t)0x00100000)
-#define DMA_HIFCR_CTEIF6                     ((uint32_t)0x00080000)
-#define DMA_HIFCR_CDMEIF6                    ((uint32_t)0x00040000)
-#define DMA_HIFCR_CFEIF6                     ((uint32_t)0x00010000)
-#define DMA_HIFCR_CTCIF5                     ((uint32_t)0x00000800)
-#define DMA_HIFCR_CHTIF5                     ((uint32_t)0x00000400)
-#define DMA_HIFCR_CTEIF5                     ((uint32_t)0x00000200)
-#define DMA_HIFCR_CDMEIF5                    ((uint32_t)0x00000100)
-#define DMA_HIFCR_CFEIF5                     ((uint32_t)0x00000040)
-#define DMA_HIFCR_CTCIF4                     ((uint32_t)0x00000020)
-#define DMA_HIFCR_CHTIF4                     ((uint32_t)0x00000010)
-#define DMA_HIFCR_CTEIF4                     ((uint32_t)0x00000008)
-#define DMA_HIFCR_CDMEIF4                    ((uint32_t)0x00000004)
-#define DMA_HIFCR_CFEIF4                     ((uint32_t)0x00000001)
+#define DMA_HIFCR_CTCIF7                     (0x08000000UL)
+#define DMA_HIFCR_CHTIF7                     (0x04000000UL)
+#define DMA_HIFCR_CTEIF7                     (0x02000000UL)
+#define DMA_HIFCR_CDMEIF7                    (0x01000000UL)
+#define DMA_HIFCR_CFEIF7                     (0x00400000UL)
+#define DMA_HIFCR_CTCIF6                     (0x00200000UL)
+#define DMA_HIFCR_CHTIF6                     (0x00100000UL)
+#define DMA_HIFCR_CTEIF6                     (0x00080000UL)
+#define DMA_HIFCR_CDMEIF6                    (0x00040000UL)
+#define DMA_HIFCR_CFEIF6                     (0x00010000UL)
+#define DMA_HIFCR_CTCIF5                     (0x00000800UL)
+#define DMA_HIFCR_CHTIF5                     (0x00000400UL)
+#define DMA_HIFCR_CTEIF5                     (0x00000200UL)
+#define DMA_HIFCR_CDMEIF5                    (0x00000100UL)
+#define DMA_HIFCR_CFEIF5                     (0x00000040UL)
+#define DMA_HIFCR_CTCIF4                     (0x00000020UL)
+#define DMA_HIFCR_CHTIF4                     (0x00000010UL)
+#define DMA_HIFCR_CTEIF4                     (0x00000008UL)
+#define DMA_HIFCR_CDMEIF4                    (0x00000004UL)
+#define DMA_HIFCR_CFEIF4                     (0x00000001UL)
 
 
 /******************************************************************************/
@@ -1467,154 +1463,154 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for EXTI_IMR register  *******************/
-#define  EXTI_IMR_MR0                        ((uint32_t)0x00000001)        /*!< Interrupt Mask on line 0 */
-#define  EXTI_IMR_MR1                        ((uint32_t)0x00000002)        /*!< Interrupt Mask on line 1 */
-#define  EXTI_IMR_MR2                        ((uint32_t)0x00000004)        /*!< Interrupt Mask on line 2 */
-#define  EXTI_IMR_MR3                        ((uint32_t)0x00000008)        /*!< Interrupt Mask on line 3 */
-#define  EXTI_IMR_MR4                        ((uint32_t)0x00000010)        /*!< Interrupt Mask on line 4 */
-#define  EXTI_IMR_MR5                        ((uint32_t)0x00000020)        /*!< Interrupt Mask on line 5 */
-#define  EXTI_IMR_MR6                        ((uint32_t)0x00000040)        /*!< Interrupt Mask on line 6 */
-#define  EXTI_IMR_MR7                        ((uint32_t)0x00000080)        /*!< Interrupt Mask on line 7 */
-#define  EXTI_IMR_MR8                        ((uint32_t)0x00000100)        /*!< Interrupt Mask on line 8 */
-#define  EXTI_IMR_MR9                        ((uint32_t)0x00000200)        /*!< Interrupt Mask on line 9 */
-#define  EXTI_IMR_MR10                       ((uint32_t)0x00000400)        /*!< Interrupt Mask on line 10 */
-#define  EXTI_IMR_MR11                       ((uint32_t)0x00000800)        /*!< Interrupt Mask on line 11 */
-#define  EXTI_IMR_MR12                       ((uint32_t)0x00001000)        /*!< Interrupt Mask on line 12 */
-#define  EXTI_IMR_MR13                       ((uint32_t)0x00002000)        /*!< Interrupt Mask on line 13 */
-#define  EXTI_IMR_MR14                       ((uint32_t)0x00004000)        /*!< Interrupt Mask on line 14 */
-#define  EXTI_IMR_MR15                       ((uint32_t)0x00008000)        /*!< Interrupt Mask on line 15 */
-#define  EXTI_IMR_MR16                       ((uint32_t)0x00010000)        /*!< Interrupt Mask on line 16 */
-#define  EXTI_IMR_MR17                       ((uint32_t)0x00020000)        /*!< Interrupt Mask on line 17 */
-#define  EXTI_IMR_MR18                       ((uint32_t)0x00040000)        /*!< Interrupt Mask on line 18 */
-#define  EXTI_IMR_MR19                       ((uint32_t)0x00080000)        /*!< Interrupt Mask on line 19 */
-#define  EXTI_IMR_MR20                       ((uint32_t)0x00100000)        /*!< Interrupt Mask on line 20 */
-#define  EXTI_IMR_MR21                       ((uint32_t)0x00200000)        /*!< Interrupt Mask on line 21 */
-#define  EXTI_IMR_MR22                       ((uint32_t)0x00400000)        /*!< Interrupt Mask on line 22 */
+#define  EXTI_IMR_MR0                        (0x00000001UL)        /*!< Interrupt Mask on line 0 */
+#define  EXTI_IMR_MR1                        (0x00000002UL)        /*!< Interrupt Mask on line 1 */
+#define  EXTI_IMR_MR2                        (0x00000004UL)        /*!< Interrupt Mask on line 2 */
+#define  EXTI_IMR_MR3                        (0x00000008UL)        /*!< Interrupt Mask on line 3 */
+#define  EXTI_IMR_MR4                        (0x00000010UL)        /*!< Interrupt Mask on line 4 */
+#define  EXTI_IMR_MR5                        (0x00000020UL)        /*!< Interrupt Mask on line 5 */
+#define  EXTI_IMR_MR6                        (0x00000040UL)        /*!< Interrupt Mask on line 6 */
+#define  EXTI_IMR_MR7                        (0x00000080UL)        /*!< Interrupt Mask on line 7 */
+#define  EXTI_IMR_MR8                        (0x00000100UL)        /*!< Interrupt Mask on line 8 */
+#define  EXTI_IMR_MR9                        (0x00000200UL)        /*!< Interrupt Mask on line 9 */
+#define  EXTI_IMR_MR10                       (0x00000400UL)        /*!< Interrupt Mask on line 10 */
+#define  EXTI_IMR_MR11                       (0x00000800UL)        /*!< Interrupt Mask on line 11 */
+#define  EXTI_IMR_MR12                       (0x00001000UL)        /*!< Interrupt Mask on line 12 */
+#define  EXTI_IMR_MR13                       (0x00002000UL)        /*!< Interrupt Mask on line 13 */
+#define  EXTI_IMR_MR14                       (0x00004000UL)        /*!< Interrupt Mask on line 14 */
+#define  EXTI_IMR_MR15                       (0x00008000UL)        /*!< Interrupt Mask on line 15 */
+#define  EXTI_IMR_MR16                       (0x00010000UL)        /*!< Interrupt Mask on line 16 */
+#define  EXTI_IMR_MR17                       (0x00020000UL)        /*!< Interrupt Mask on line 17 */
+#define  EXTI_IMR_MR18                       (0x00040000UL)        /*!< Interrupt Mask on line 18 */
+#define  EXTI_IMR_MR19                       (0x00080000UL)        /*!< Interrupt Mask on line 19 */
+#define  EXTI_IMR_MR20                       (0x00100000UL)        /*!< Interrupt Mask on line 20 */
+#define  EXTI_IMR_MR21                       (0x00200000UL)        /*!< Interrupt Mask on line 21 */
+#define  EXTI_IMR_MR22                       (0x00400000UL)        /*!< Interrupt Mask on line 22 */
 
 /*******************  Bit definition for EXTI_EMR register  *******************/
-#define  EXTI_EMR_MR0                        ((uint32_t)0x00000001)        /*!< Event Mask on line 0 */
-#define  EXTI_EMR_MR1                        ((uint32_t)0x00000002)        /*!< Event Mask on line 1 */
-#define  EXTI_EMR_MR2                        ((uint32_t)0x00000004)        /*!< Event Mask on line 2 */
-#define  EXTI_EMR_MR3                        ((uint32_t)0x00000008)        /*!< Event Mask on line 3 */
-#define  EXTI_EMR_MR4                        ((uint32_t)0x00000010)        /*!< Event Mask on line 4 */
-#define  EXTI_EMR_MR5                        ((uint32_t)0x00000020)        /*!< Event Mask on line 5 */
-#define  EXTI_EMR_MR6                        ((uint32_t)0x00000040)        /*!< Event Mask on line 6 */
-#define  EXTI_EMR_MR7                        ((uint32_t)0x00000080)        /*!< Event Mask on line 7 */
-#define  EXTI_EMR_MR8                        ((uint32_t)0x00000100)        /*!< Event Mask on line 8 */
-#define  EXTI_EMR_MR9                        ((uint32_t)0x00000200)        /*!< Event Mask on line 9 */
-#define  EXTI_EMR_MR10                       ((uint32_t)0x00000400)        /*!< Event Mask on line 10 */
-#define  EXTI_EMR_MR11                       ((uint32_t)0x00000800)        /*!< Event Mask on line 11 */
-#define  EXTI_EMR_MR12                       ((uint32_t)0x00001000)        /*!< Event Mask on line 12 */
-#define  EXTI_EMR_MR13                       ((uint32_t)0x00002000)        /*!< Event Mask on line 13 */
-#define  EXTI_EMR_MR14                       ((uint32_t)0x00004000)        /*!< Event Mask on line 14 */
-#define  EXTI_EMR_MR15                       ((uint32_t)0x00008000)        /*!< Event Mask on line 15 */
-#define  EXTI_EMR_MR16                       ((uint32_t)0x00010000)        /*!< Event Mask on line 16 */
-#define  EXTI_EMR_MR17                       ((uint32_t)0x00020000)        /*!< Event Mask on line 17 */
-#define  EXTI_EMR_MR18                       ((uint32_t)0x00040000)        /*!< Event Mask on line 18 */
-#define  EXTI_EMR_MR19                       ((uint32_t)0x00080000)        /*!< Event Mask on line 19 */
-#define  EXTI_EMR_MR20                       ((uint32_t)0x00100000)        /*!< Event Mask on line 20 */
-#define  EXTI_EMR_MR21                       ((uint32_t)0x00200000)        /*!< Event Mask on line 21 */
-#define  EXTI_EMR_MR22                       ((uint32_t)0x00400000)        /*!< Event Mask on line 22 */
+#define  EXTI_EMR_MR0                        (0x00000001UL)        /*!< Event Mask on line 0 */
+#define  EXTI_EMR_MR1                        (0x00000002UL)        /*!< Event Mask on line 1 */
+#define  EXTI_EMR_MR2                        (0x00000004UL)        /*!< Event Mask on line 2 */
+#define  EXTI_EMR_MR3                        (0x00000008UL)        /*!< Event Mask on line 3 */
+#define  EXTI_EMR_MR4                        (0x00000010UL)        /*!< Event Mask on line 4 */
+#define  EXTI_EMR_MR5                        (0x00000020UL)        /*!< Event Mask on line 5 */
+#define  EXTI_EMR_MR6                        (0x00000040UL)        /*!< Event Mask on line 6 */
+#define  EXTI_EMR_MR7                        (0x00000080UL)        /*!< Event Mask on line 7 */
+#define  EXTI_EMR_MR8                        (0x00000100UL)        /*!< Event Mask on line 8 */
+#define  EXTI_EMR_MR9                        (0x00000200UL)        /*!< Event Mask on line 9 */
+#define  EXTI_EMR_MR10                       (0x00000400UL)        /*!< Event Mask on line 10 */
+#define  EXTI_EMR_MR11                       (0x00000800UL)        /*!< Event Mask on line 11 */
+#define  EXTI_EMR_MR12                       (0x00001000UL)        /*!< Event Mask on line 12 */
+#define  EXTI_EMR_MR13                       (0x00002000UL)        /*!< Event Mask on line 13 */
+#define  EXTI_EMR_MR14                       (0x00004000UL)        /*!< Event Mask on line 14 */
+#define  EXTI_EMR_MR15                       (0x00008000UL)        /*!< Event Mask on line 15 */
+#define  EXTI_EMR_MR16                       (0x00010000UL)        /*!< Event Mask on line 16 */
+#define  EXTI_EMR_MR17                       (0x00020000UL)        /*!< Event Mask on line 17 */
+#define  EXTI_EMR_MR18                       (0x00040000UL)        /*!< Event Mask on line 18 */
+#define  EXTI_EMR_MR19                       (0x00080000UL)        /*!< Event Mask on line 19 */
+#define  EXTI_EMR_MR20                       (0x00100000UL)        /*!< Event Mask on line 20 */
+#define  EXTI_EMR_MR21                       (0x00200000UL)        /*!< Event Mask on line 21 */
+#define  EXTI_EMR_MR22                       (0x00400000UL)        /*!< Event Mask on line 22 */
 
 /******************  Bit definition for EXTI_RTSR register  *******************/
-#define  EXTI_RTSR_TR0                       ((uint32_t)0x00000001)        /*!< Rising trigger event configuration bit of line 0 */
-#define  EXTI_RTSR_TR1                       ((uint32_t)0x00000002)        /*!< Rising trigger event configuration bit of line 1 */
-#define  EXTI_RTSR_TR2                       ((uint32_t)0x00000004)        /*!< Rising trigger event configuration bit of line 2 */
-#define  EXTI_RTSR_TR3                       ((uint32_t)0x00000008)        /*!< Rising trigger event configuration bit of line 3 */
-#define  EXTI_RTSR_TR4                       ((uint32_t)0x00000010)        /*!< Rising trigger event configuration bit of line 4 */
-#define  EXTI_RTSR_TR5                       ((uint32_t)0x00000020)        /*!< Rising trigger event configuration bit of line 5 */
-#define  EXTI_RTSR_TR6                       ((uint32_t)0x00000040)        /*!< Rising trigger event configuration bit of line 6 */
-#define  EXTI_RTSR_TR7                       ((uint32_t)0x00000080)        /*!< Rising trigger event configuration bit of line 7 */
-#define  EXTI_RTSR_TR8                       ((uint32_t)0x00000100)        /*!< Rising trigger event configuration bit of line 8 */
-#define  EXTI_RTSR_TR9                       ((uint32_t)0x00000200)        /*!< Rising trigger event configuration bit of line 9 */
-#define  EXTI_RTSR_TR10                      ((uint32_t)0x00000400)        /*!< Rising trigger event configuration bit of line 10 */
-#define  EXTI_RTSR_TR11                      ((uint32_t)0x00000800)        /*!< Rising trigger event configuration bit of line 11 */
-#define  EXTI_RTSR_TR12                      ((uint32_t)0x00001000)        /*!< Rising trigger event configuration bit of line 12 */
-#define  EXTI_RTSR_TR13                      ((uint32_t)0x00002000)        /*!< Rising trigger event configuration bit of line 13 */
-#define  EXTI_RTSR_TR14                      ((uint32_t)0x00004000)        /*!< Rising trigger event configuration bit of line 14 */
-#define  EXTI_RTSR_TR15                      ((uint32_t)0x00008000)        /*!< Rising trigger event configuration bit of line 15 */
-#define  EXTI_RTSR_TR16                      ((uint32_t)0x00010000)        /*!< Rising trigger event configuration bit of line 16 */
-#define  EXTI_RTSR_TR17                      ((uint32_t)0x00020000)        /*!< Rising trigger event configuration bit of line 17 */
-#define  EXTI_RTSR_TR18                      ((uint32_t)0x00040000)        /*!< Rising trigger event configuration bit of line 18 */
-#define  EXTI_RTSR_TR19                      ((uint32_t)0x00080000)        /*!< Rising trigger event configuration bit of line 19 */
-#define  EXTI_RTSR_TR20                      ((uint32_t)0x00100000)        /*!< Rising trigger event configuration bit of line 20 */
-#define  EXTI_RTSR_TR21                      ((uint32_t)0x00200000)        /*!< Rising trigger event configuration bit of line 21 */
-#define  EXTI_RTSR_TR22                      ((uint32_t)0x00400000)        /*!< Rising trigger event configuration bit of line 22 */
+#define  EXTI_RTSR_TR0                       (0x00000001UL)        /*!< Rising trigger event configuration bit of line 0 */
+#define  EXTI_RTSR_TR1                       (0x00000002UL)        /*!< Rising trigger event configuration bit of line 1 */
+#define  EXTI_RTSR_TR2                       (0x00000004UL)        /*!< Rising trigger event configuration bit of line 2 */
+#define  EXTI_RTSR_TR3                       (0x00000008UL)        /*!< Rising trigger event configuration bit of line 3 */
+#define  EXTI_RTSR_TR4                       (0x00000010UL)        /*!< Rising trigger event configuration bit of line 4 */
+#define  EXTI_RTSR_TR5                       (0x00000020UL)        /*!< Rising trigger event configuration bit of line 5 */
+#define  EXTI_RTSR_TR6                       (0x00000040UL)        /*!< Rising trigger event configuration bit of line 6 */
+#define  EXTI_RTSR_TR7                       (0x00000080UL)        /*!< Rising trigger event configuration bit of line 7 */
+#define  EXTI_RTSR_TR8                       (0x00000100UL)        /*!< Rising trigger event configuration bit of line 8 */
+#define  EXTI_RTSR_TR9                       (0x00000200UL)        /*!< Rising trigger event configuration bit of line 9 */
+#define  EXTI_RTSR_TR10                      (0x00000400UL)        /*!< Rising trigger event configuration bit of line 10 */
+#define  EXTI_RTSR_TR11                      (0x00000800UL)        /*!< Rising trigger event configuration bit of line 11 */
+#define  EXTI_RTSR_TR12                      (0x00001000UL)        /*!< Rising trigger event configuration bit of line 12 */
+#define  EXTI_RTSR_TR13                      (0x00002000UL)        /*!< Rising trigger event configuration bit of line 13 */
+#define  EXTI_RTSR_TR14                      (0x00004000UL)        /*!< Rising trigger event configuration bit of line 14 */
+#define  EXTI_RTSR_TR15                      (0x00008000UL)        /*!< Rising trigger event configuration bit of line 15 */
+#define  EXTI_RTSR_TR16                      (0x00010000UL)        /*!< Rising trigger event configuration bit of line 16 */
+#define  EXTI_RTSR_TR17                      (0x00020000UL)        /*!< Rising trigger event configuration bit of line 17 */
+#define  EXTI_RTSR_TR18                      (0x00040000UL)        /*!< Rising trigger event configuration bit of line 18 */
+#define  EXTI_RTSR_TR19                      (0x00080000UL)        /*!< Rising trigger event configuration bit of line 19 */
+#define  EXTI_RTSR_TR20                      (0x00100000UL)        /*!< Rising trigger event configuration bit of line 20 */
+#define  EXTI_RTSR_TR21                      (0x00200000UL)        /*!< Rising trigger event configuration bit of line 21 */
+#define  EXTI_RTSR_TR22                      (0x00400000UL)        /*!< Rising trigger event configuration bit of line 22 */
 
 /******************  Bit definition for EXTI_FTSR register  *******************/
-#define  EXTI_FTSR_TR0                       ((uint32_t)0x00000001)        /*!< Falling trigger event configuration bit of line 0 */
-#define  EXTI_FTSR_TR1                       ((uint32_t)0x00000002)        /*!< Falling trigger event configuration bit of line 1 */
-#define  EXTI_FTSR_TR2                       ((uint32_t)0x00000004)        /*!< Falling trigger event configuration bit of line 2 */
-#define  EXTI_FTSR_TR3                       ((uint32_t)0x00000008)        /*!< Falling trigger event configuration bit of line 3 */
-#define  EXTI_FTSR_TR4                       ((uint32_t)0x00000010)        /*!< Falling trigger event configuration bit of line 4 */
-#define  EXTI_FTSR_TR5                       ((uint32_t)0x00000020)        /*!< Falling trigger event configuration bit of line 5 */
-#define  EXTI_FTSR_TR6                       ((uint32_t)0x00000040)        /*!< Falling trigger event configuration bit of line 6 */
-#define  EXTI_FTSR_TR7                       ((uint32_t)0x00000080)        /*!< Falling trigger event configuration bit of line 7 */
-#define  EXTI_FTSR_TR8                       ((uint32_t)0x00000100)        /*!< Falling trigger event configuration bit of line 8 */
-#define  EXTI_FTSR_TR9                       ((uint32_t)0x00000200)        /*!< Falling trigger event configuration bit of line 9 */
-#define  EXTI_FTSR_TR10                      ((uint32_t)0x00000400)        /*!< Falling trigger event configuration bit of line 10 */
-#define  EXTI_FTSR_TR11                      ((uint32_t)0x00000800)        /*!< Falling trigger event configuration bit of line 11 */
-#define  EXTI_FTSR_TR12                      ((uint32_t)0x00001000)        /*!< Falling trigger event configuration bit of line 12 */
-#define  EXTI_FTSR_TR13                      ((uint32_t)0x00002000)        /*!< Falling trigger event configuration bit of line 13 */
-#define  EXTI_FTSR_TR14                      ((uint32_t)0x00004000)        /*!< Falling trigger event configuration bit of line 14 */
-#define  EXTI_FTSR_TR15                      ((uint32_t)0x00008000)        /*!< Falling trigger event configuration bit of line 15 */
-#define  EXTI_FTSR_TR16                      ((uint32_t)0x00010000)        /*!< Falling trigger event configuration bit of line 16 */
-#define  EXTI_FTSR_TR17                      ((uint32_t)0x00020000)        /*!< Falling trigger event configuration bit of line 17 */
-#define  EXTI_FTSR_TR18                      ((uint32_t)0x00040000)        /*!< Falling trigger event configuration bit of line 18 */
-#define  EXTI_FTSR_TR19                      ((uint32_t)0x00080000)        /*!< Falling trigger event configuration bit of line 19 */
-#define  EXTI_FTSR_TR20                      ((uint32_t)0x00100000)        /*!< Falling trigger event configuration bit of line 20 */
-#define  EXTI_FTSR_TR21                      ((uint32_t)0x00200000)        /*!< Falling trigger event configuration bit of line 21 */
-#define  EXTI_FTSR_TR22                      ((uint32_t)0x00400000)        /*!< Falling trigger event configuration bit of line 22 */
+#define  EXTI_FTSR_TR0                       (0x00000001UL)        /*!< Falling trigger event configuration bit of line 0 */
+#define  EXTI_FTSR_TR1                       (0x00000002UL)        /*!< Falling trigger event configuration bit of line 1 */
+#define  EXTI_FTSR_TR2                       (0x00000004UL)        /*!< Falling trigger event configuration bit of line 2 */
+#define  EXTI_FTSR_TR3                       (0x00000008UL)        /*!< Falling trigger event configuration bit of line 3 */
+#define  EXTI_FTSR_TR4                       (0x00000010UL)        /*!< Falling trigger event configuration bit of line 4 */
+#define  EXTI_FTSR_TR5                       (0x00000020UL)        /*!< Falling trigger event configuration bit of line 5 */
+#define  EXTI_FTSR_TR6                       (0x00000040UL)        /*!< Falling trigger event configuration bit of line 6 */
+#define  EXTI_FTSR_TR7                       (0x00000080UL)        /*!< Falling trigger event configuration bit of line 7 */
+#define  EXTI_FTSR_TR8                       (0x00000100UL)        /*!< Falling trigger event configuration bit of line 8 */
+#define  EXTI_FTSR_TR9                       (0x00000200UL)        /*!< Falling trigger event configuration bit of line 9 */
+#define  EXTI_FTSR_TR10                      (0x00000400UL)        /*!< Falling trigger event configuration bit of line 10 */
+#define  EXTI_FTSR_TR11                      (0x00000800UL)        /*!< Falling trigger event configuration bit of line 11 */
+#define  EXTI_FTSR_TR12                      (0x00001000UL)        /*!< Falling trigger event configuration bit of line 12 */
+#define  EXTI_FTSR_TR13                      (0x00002000UL)        /*!< Falling trigger event configuration bit of line 13 */
+#define  EXTI_FTSR_TR14                      (0x00004000UL)        /*!< Falling trigger event configuration bit of line 14 */
+#define  EXTI_FTSR_TR15                      (0x00008000UL)        /*!< Falling trigger event configuration bit of line 15 */
+#define  EXTI_FTSR_TR16                      (0x00010000UL)        /*!< Falling trigger event configuration bit of line 16 */
+#define  EXTI_FTSR_TR17                      (0x00020000UL)        /*!< Falling trigger event configuration bit of line 17 */
+#define  EXTI_FTSR_TR18                      (0x00040000UL)        /*!< Falling trigger event configuration bit of line 18 */
+#define  EXTI_FTSR_TR19                      (0x00080000UL)        /*!< Falling trigger event configuration bit of line 19 */
+#define  EXTI_FTSR_TR20                      (0x00100000UL)        /*!< Falling trigger event configuration bit of line 20 */
+#define  EXTI_FTSR_TR21                      (0x00200000UL)        /*!< Falling trigger event configuration bit of line 21 */
+#define  EXTI_FTSR_TR22                      (0x00400000UL)        /*!< Falling trigger event configuration bit of line 22 */
 
 /******************  Bit definition for EXTI_SWIER register  ******************/
-#define  EXTI_SWIER_SWIER0                   ((uint32_t)0x00000001)        /*!< Software Interrupt on line 0 */
-#define  EXTI_SWIER_SWIER1                   ((uint32_t)0x00000002)        /*!< Software Interrupt on line 1 */
-#define  EXTI_SWIER_SWIER2                   ((uint32_t)0x00000004)        /*!< Software Interrupt on line 2 */
-#define  EXTI_SWIER_SWIER3                   ((uint32_t)0x00000008)        /*!< Software Interrupt on line 3 */
-#define  EXTI_SWIER_SWIER4                   ((uint32_t)0x00000010)        /*!< Software Interrupt on line 4 */
-#define  EXTI_SWIER_SWIER5                   ((uint32_t)0x00000020)        /*!< Software Interrupt on line 5 */
-#define  EXTI_SWIER_SWIER6                   ((uint32_t)0x00000040)        /*!< Software Interrupt on line 6 */
-#define  EXTI_SWIER_SWIER7                   ((uint32_t)0x00000080)        /*!< Software Interrupt on line 7 */
-#define  EXTI_SWIER_SWIER8                   ((uint32_t)0x00000100)        /*!< Software Interrupt on line 8 */
-#define  EXTI_SWIER_SWIER9                   ((uint32_t)0x00000200)        /*!< Software Interrupt on line 9 */
-#define  EXTI_SWIER_SWIER10                  ((uint32_t)0x00000400)        /*!< Software Interrupt on line 10 */
-#define  EXTI_SWIER_SWIER11                  ((uint32_t)0x00000800)        /*!< Software Interrupt on line 11 */
-#define  EXTI_SWIER_SWIER12                  ((uint32_t)0x00001000)        /*!< Software Interrupt on line 12 */
-#define  EXTI_SWIER_SWIER13                  ((uint32_t)0x00002000)        /*!< Software Interrupt on line 13 */
-#define  EXTI_SWIER_SWIER14                  ((uint32_t)0x00004000)        /*!< Software Interrupt on line 14 */
-#define  EXTI_SWIER_SWIER15                  ((uint32_t)0x00008000)        /*!< Software Interrupt on line 15 */
-#define  EXTI_SWIER_SWIER16                  ((uint32_t)0x00010000)        /*!< Software Interrupt on line 16 */
-#define  EXTI_SWIER_SWIER17                  ((uint32_t)0x00020000)        /*!< Software Interrupt on line 17 */
-#define  EXTI_SWIER_SWIER18                  ((uint32_t)0x00040000)        /*!< Software Interrupt on line 18 */
-#define  EXTI_SWIER_SWIER19                  ((uint32_t)0x00080000)        /*!< Software Interrupt on line 19 */
-#define  EXTI_SWIER_SWIER20                  ((uint32_t)0x00100000)        /*!< Software Interrupt on line 20 */
-#define  EXTI_SWIER_SWIER21                  ((uint32_t)0x00200000)        /*!< Software Interrupt on line 21 */
-#define  EXTI_SWIER_SWIER22                  ((uint32_t)0x00400000)        /*!< Software Interrupt on line 22 */
+#define  EXTI_SWIER_SWIER0                   (0x00000001UL)        /*!< Software Interrupt on line 0 */
+#define  EXTI_SWIER_SWIER1                   (0x00000002UL)        /*!< Software Interrupt on line 1 */
+#define  EXTI_SWIER_SWIER2                   (0x00000004UL)        /*!< Software Interrupt on line 2 */
+#define  EXTI_SWIER_SWIER3                   (0x00000008UL)        /*!< Software Interrupt on line 3 */
+#define  EXTI_SWIER_SWIER4                   (0x00000010UL)        /*!< Software Interrupt on line 4 */
+#define  EXTI_SWIER_SWIER5                   (0x00000020UL)        /*!< Software Interrupt on line 5 */
+#define  EXTI_SWIER_SWIER6                   (0x00000040UL)        /*!< Software Interrupt on line 6 */
+#define  EXTI_SWIER_SWIER7                   (0x00000080UL)        /*!< Software Interrupt on line 7 */
+#define  EXTI_SWIER_SWIER8                   (0x00000100UL)        /*!< Software Interrupt on line 8 */
+#define  EXTI_SWIER_SWIER9                   (0x00000200UL)        /*!< Software Interrupt on line 9 */
+#define  EXTI_SWIER_SWIER10                  (0x00000400UL)        /*!< Software Interrupt on line 10 */
+#define  EXTI_SWIER_SWIER11                  (0x00000800UL)        /*!< Software Interrupt on line 11 */
+#define  EXTI_SWIER_SWIER12                  (0x00001000UL)        /*!< Software Interrupt on line 12 */
+#define  EXTI_SWIER_SWIER13                  (0x00002000UL)        /*!< Software Interrupt on line 13 */
+#define  EXTI_SWIER_SWIER14                  (0x00004000UL)        /*!< Software Interrupt on line 14 */
+#define  EXTI_SWIER_SWIER15                  (0x00008000UL)        /*!< Software Interrupt on line 15 */
+#define  EXTI_SWIER_SWIER16                  (0x00010000UL)        /*!< Software Interrupt on line 16 */
+#define  EXTI_SWIER_SWIER17                  (0x00020000UL)        /*!< Software Interrupt on line 17 */
+#define  EXTI_SWIER_SWIER18                  (0x00040000UL)        /*!< Software Interrupt on line 18 */
+#define  EXTI_SWIER_SWIER19                  (0x00080000UL)        /*!< Software Interrupt on line 19 */
+#define  EXTI_SWIER_SWIER20                  (0x00100000UL)        /*!< Software Interrupt on line 20 */
+#define  EXTI_SWIER_SWIER21                  (0x00200000UL)        /*!< Software Interrupt on line 21 */
+#define  EXTI_SWIER_SWIER22                  (0x00400000UL)        /*!< Software Interrupt on line 22 */
 
 /*******************  Bit definition for EXTI_PR register  ********************/
-#define  EXTI_PR_PR0                         ((uint32_t)0x00000001)        /*!< Pending bit for line 0 */
-#define  EXTI_PR_PR1                         ((uint32_t)0x00000002)        /*!< Pending bit for line 1 */
-#define  EXTI_PR_PR2                         ((uint32_t)0x00000004)        /*!< Pending bit for line 2 */
-#define  EXTI_PR_PR3                         ((uint32_t)0x00000008)        /*!< Pending bit for line 3 */
-#define  EXTI_PR_PR4                         ((uint32_t)0x00000010)        /*!< Pending bit for line 4 */
-#define  EXTI_PR_PR5                         ((uint32_t)0x00000020)        /*!< Pending bit for line 5 */
-#define  EXTI_PR_PR6                         ((uint32_t)0x00000040)        /*!< Pending bit for line 6 */
-#define  EXTI_PR_PR7                         ((uint32_t)0x00000080)        /*!< Pending bit for line 7 */
-#define  EXTI_PR_PR8                         ((uint32_t)0x00000100)        /*!< Pending bit for line 8 */
-#define  EXTI_PR_PR9                         ((uint32_t)0x00000200)        /*!< Pending bit for line 9 */
-#define  EXTI_PR_PR10                        ((uint32_t)0x00000400)        /*!< Pending bit for line 10 */
-#define  EXTI_PR_PR11                        ((uint32_t)0x00000800)        /*!< Pending bit for line 11 */
-#define  EXTI_PR_PR12                        ((uint32_t)0x00001000)        /*!< Pending bit for line 12 */
-#define  EXTI_PR_PR13                        ((uint32_t)0x00002000)        /*!< Pending bit for line 13 */
-#define  EXTI_PR_PR14                        ((uint32_t)0x00004000)        /*!< Pending bit for line 14 */
-#define  EXTI_PR_PR15                        ((uint32_t)0x00008000)        /*!< Pending bit for line 15 */
-#define  EXTI_PR_PR16                        ((uint32_t)0x00010000)        /*!< Pending bit for line 16 */
-#define  EXTI_PR_PR17                        ((uint32_t)0x00020000)        /*!< Pending bit for line 17 */
-#define  EXTI_PR_PR18                        ((uint32_t)0x00040000)        /*!< Pending bit for line 18 */
-#define  EXTI_PR_PR19                        ((uint32_t)0x00080000)        /*!< Pending bit for line 19 */
-#define  EXTI_PR_PR20                        ((uint32_t)0x00100000)        /*!< Pending bit for line 20 */
-#define  EXTI_PR_PR21                        ((uint32_t)0x00200000)        /*!< Pending bit for line 21 */
-#define  EXTI_PR_PR22                        ((uint32_t)0x00400000)        /*!< Pending bit for line 22 */
+#define  EXTI_PR_PR0                         (0x00000001UL)        /*!< Pending bit for line 0 */
+#define  EXTI_PR_PR1                         (0x00000002UL)        /*!< Pending bit for line 1 */
+#define  EXTI_PR_PR2                         (0x00000004UL)        /*!< Pending bit for line 2 */
+#define  EXTI_PR_PR3                         (0x00000008UL)        /*!< Pending bit for line 3 */
+#define  EXTI_PR_PR4                         (0x00000010UL)        /*!< Pending bit for line 4 */
+#define  EXTI_PR_PR5                         (0x00000020UL)        /*!< Pending bit for line 5 */
+#define  EXTI_PR_PR6                         (0x00000040UL)        /*!< Pending bit for line 6 */
+#define  EXTI_PR_PR7                         (0x00000080UL)        /*!< Pending bit for line 7 */
+#define  EXTI_PR_PR8                         (0x00000100UL)        /*!< Pending bit for line 8 */
+#define  EXTI_PR_PR9                         (0x00000200UL)        /*!< Pending bit for line 9 */
+#define  EXTI_PR_PR10                        (0x00000400UL)        /*!< Pending bit for line 10 */
+#define  EXTI_PR_PR11                        (0x00000800UL)        /*!< Pending bit for line 11 */
+#define  EXTI_PR_PR12                        (0x00001000UL)        /*!< Pending bit for line 12 */
+#define  EXTI_PR_PR13                        (0x00002000UL)        /*!< Pending bit for line 13 */
+#define  EXTI_PR_PR14                        (0x00004000UL)        /*!< Pending bit for line 14 */
+#define  EXTI_PR_PR15                        (0x00008000UL)        /*!< Pending bit for line 15 */
+#define  EXTI_PR_PR16                        (0x00010000UL)        /*!< Pending bit for line 16 */
+#define  EXTI_PR_PR17                        (0x00020000UL)        /*!< Pending bit for line 17 */
+#define  EXTI_PR_PR18                        (0x00040000UL)        /*!< Pending bit for line 18 */
+#define  EXTI_PR_PR19                        (0x00080000UL)        /*!< Pending bit for line 19 */
+#define  EXTI_PR_PR20                        (0x00100000UL)        /*!< Pending bit for line 20 */
+#define  EXTI_PR_PR21                        (0x00200000UL)        /*!< Pending bit for line 21 */
+#define  EXTI_PR_PR22                        (0x00400000UL)        /*!< Pending bit for line 22 */
 
 /******************************************************************************/
 /*                                                                            */
@@ -1622,97 +1618,97 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bits definition for FLASH_ACR register  *****************/
-#define FLASH_ACR_LATENCY                    ((uint32_t)0x0000000F)
-#define FLASH_ACR_LATENCY_0WS                ((uint32_t)0x00000000)
-#define FLASH_ACR_LATENCY_1WS                ((uint32_t)0x00000001)
-#define FLASH_ACR_LATENCY_2WS                ((uint32_t)0x00000002)
-#define FLASH_ACR_LATENCY_3WS                ((uint32_t)0x00000003)
-#define FLASH_ACR_LATENCY_4WS                ((uint32_t)0x00000004)
-#define FLASH_ACR_LATENCY_5WS                ((uint32_t)0x00000005)
-#define FLASH_ACR_LATENCY_6WS                ((uint32_t)0x00000006)
-#define FLASH_ACR_LATENCY_7WS                ((uint32_t)0x00000007)
+#define FLASH_ACR_LATENCY                    (0x0000000FUL)
+#define FLASH_ACR_LATENCY_0WS                (0x00000000UL)
+#define FLASH_ACR_LATENCY_1WS                (0x00000001UL)
+#define FLASH_ACR_LATENCY_2WS                (0x00000002UL)
+#define FLASH_ACR_LATENCY_3WS                (0x00000003UL)
+#define FLASH_ACR_LATENCY_4WS                (0x00000004UL)
+#define FLASH_ACR_LATENCY_5WS                (0x00000005UL)
+#define FLASH_ACR_LATENCY_6WS                (0x00000006UL)
+#define FLASH_ACR_LATENCY_7WS                (0x00000007UL)
 
-#define FLASH_ACR_PRFTEN                     ((uint32_t)0x00000100)
-#define FLASH_ACR_ICEN                       ((uint32_t)0x00000200)
-#define FLASH_ACR_DCEN                       ((uint32_t)0x00000400)
-#define FLASH_ACR_ICRST                      ((uint32_t)0x00000800)
-#define FLASH_ACR_DCRST                      ((uint32_t)0x00001000)
-#define FLASH_ACR_BYTE0_ADDRESS              ((uint32_t)0x40023C00)
-#define FLASH_ACR_BYTE2_ADDRESS              ((uint32_t)0x40023C03)
+#define FLASH_ACR_PRFTEN                     (0x00000100UL)
+#define FLASH_ACR_ICEN                       (0x00000200UL)
+#define FLASH_ACR_DCEN                       (0x00000400UL)
+#define FLASH_ACR_ICRST                      (0x00000800UL)
+#define FLASH_ACR_DCRST                      (0x00001000UL)
+#define FLASH_ACR_BYTE0_ADDRESS              (0x40023C00UL)
+#define FLASH_ACR_BYTE2_ADDRESS              (0x40023C03UL)
 
 /*******************  Bits definition for FLASH_SR register  ******************/
-#define FLASH_SR_EOP                         ((uint32_t)0x00000001)
-#define FLASH_SR_SOP                         ((uint32_t)0x00000002)
-#define FLASH_SR_WRPERR                      ((uint32_t)0x00000010)
-#define FLASH_SR_PGAERR                      ((uint32_t)0x00000020)
-#define FLASH_SR_PGPERR                      ((uint32_t)0x00000040)
-#define FLASH_SR_PGSERR                      ((uint32_t)0x00000080)
-#define FLASH_SR_BSY                         ((uint32_t)0x00010000)
+#define FLASH_SR_EOP                         (0x00000001UL)
+#define FLASH_SR_SOP                         (0x00000002UL)
+#define FLASH_SR_WRPERR                      (0x00000010UL)
+#define FLASH_SR_PGAERR                      (0x00000020UL)
+#define FLASH_SR_PGPERR                      (0x00000040UL)
+#define FLASH_SR_PGSERR                      (0x00000080UL)
+#define FLASH_SR_BSY                         (0x00010000UL)
 
 /*******************  Bits definition for FLASH_CR register  ******************/
-#define FLASH_CR_PG                          ((uint32_t)0x00000001)
-#define FLASH_CR_SER                         ((uint32_t)0x00000002)
-#define FLASH_CR_MER                         ((uint32_t)0x00000004)
-#define FLASH_CR_SNB                         ((uint32_t)0x000000F8)
-#define FLASH_CR_SNB_0                       ((uint32_t)0x00000008)
-#define FLASH_CR_SNB_1                       ((uint32_t)0x00000010)
-#define FLASH_CR_SNB_2                       ((uint32_t)0x00000020)
-#define FLASH_CR_SNB_3                       ((uint32_t)0x00000040)
-#define FLASH_CR_SNB_4                       ((uint32_t)0x00000080)
-#define FLASH_CR_PSIZE                       ((uint32_t)0x00000300)
-#define FLASH_CR_PSIZE_0                     ((uint32_t)0x00000100)
-#define FLASH_CR_PSIZE_1                     ((uint32_t)0x00000200)
-#define FLASH_CR_STRT                        ((uint32_t)0x00010000)
-#define FLASH_CR_EOPIE                       ((uint32_t)0x01000000)
-#define FLASH_CR_LOCK                        ((uint32_t)0x80000000)
+#define FLASH_CR_PG                          (0x00000001UL)
+#define FLASH_CR_SER                         (0x00000002UL)
+#define FLASH_CR_MER                         (0x00000004UL)
+#define FLASH_CR_SNB                         (0x000000F8UL)
+#define FLASH_CR_SNB_0                       (0x00000008UL)
+#define FLASH_CR_SNB_1                       (0x00000010UL)
+#define FLASH_CR_SNB_2                       (0x00000020UL)
+#define FLASH_CR_SNB_3                       (0x00000040UL)
+#define FLASH_CR_SNB_4                       (0x00000080UL)
+#define FLASH_CR_PSIZE                       (0x00000300UL)
+#define FLASH_CR_PSIZE_0                     (0x00000100UL)
+#define FLASH_CR_PSIZE_1                     (0x00000200UL)
+#define FLASH_CR_STRT                        (0x00010000UL)
+#define FLASH_CR_EOPIE                       (0x01000000UL)
+#define FLASH_CR_LOCK                        (0x80000000UL)
 
 /*******************  Bits definition for FLASH_OPTCR register  ***************/
-#define FLASH_OPTCR_OPTLOCK                 ((uint32_t)0x00000001)
-#define FLASH_OPTCR_OPTSTRT                 ((uint32_t)0x00000002)
-#define FLASH_OPTCR_BOR_LEV_0               ((uint32_t)0x00000004)
-#define FLASH_OPTCR_BOR_LEV_1               ((uint32_t)0x00000008)
-#define FLASH_OPTCR_BOR_LEV                 ((uint32_t)0x0000000C)
+#define FLASH_OPTCR_OPTLOCK                 (0x00000001UL)
+#define FLASH_OPTCR_OPTSTRT                 (0x00000002UL)
+#define FLASH_OPTCR_BOR_LEV_0               (0x00000004UL)
+#define FLASH_OPTCR_BOR_LEV_1               (0x00000008UL)
+#define FLASH_OPTCR_BOR_LEV                 (0x0000000CUL)
 
-#define FLASH_OPTCR_WDG_SW                  ((uint32_t)0x00000020)
-#define FLASH_OPTCR_nRST_STOP               ((uint32_t)0x00000040)
-#define FLASH_OPTCR_nRST_STDBY              ((uint32_t)0x00000080)
-#define FLASH_OPTCR_RDP                     ((uint32_t)0x0000FF00)
-#define FLASH_OPTCR_RDP_0                   ((uint32_t)0x00000100)
-#define FLASH_OPTCR_RDP_1                   ((uint32_t)0x00000200)
-#define FLASH_OPTCR_RDP_2                   ((uint32_t)0x00000400)
-#define FLASH_OPTCR_RDP_3                   ((uint32_t)0x00000800)
-#define FLASH_OPTCR_RDP_4                   ((uint32_t)0x00001000)
-#define FLASH_OPTCR_RDP_5                   ((uint32_t)0x00002000)
-#define FLASH_OPTCR_RDP_6                   ((uint32_t)0x00004000)
-#define FLASH_OPTCR_RDP_7                   ((uint32_t)0x00008000)
-#define FLASH_OPTCR_nWRP                    ((uint32_t)0x0FFF0000)
-#define FLASH_OPTCR_nWRP_0                  ((uint32_t)0x00010000)
-#define FLASH_OPTCR_nWRP_1                  ((uint32_t)0x00020000)
-#define FLASH_OPTCR_nWRP_2                  ((uint32_t)0x00040000)
-#define FLASH_OPTCR_nWRP_3                  ((uint32_t)0x00080000)
-#define FLASH_OPTCR_nWRP_4                  ((uint32_t)0x00100000)
-#define FLASH_OPTCR_nWRP_5                  ((uint32_t)0x00200000)
-#define FLASH_OPTCR_nWRP_6                  ((uint32_t)0x00400000)
-#define FLASH_OPTCR_nWRP_7                  ((uint32_t)0x00800000)
-#define FLASH_OPTCR_nWRP_8                  ((uint32_t)0x01000000)
-#define FLASH_OPTCR_nWRP_9                  ((uint32_t)0x02000000)
-#define FLASH_OPTCR_nWRP_10                 ((uint32_t)0x04000000)
-#define FLASH_OPTCR_nWRP_11                 ((uint32_t)0x08000000)
+#define FLASH_OPTCR_WDG_SW                  (0x00000020UL)
+#define FLASH_OPTCR_nRST_STOP               (0x00000040UL)
+#define FLASH_OPTCR_nRST_STDBY              (0x00000080UL)
+#define FLASH_OPTCR_RDP                     (0x0000FF00UL)
+#define FLASH_OPTCR_RDP_0                   (0x00000100UL)
+#define FLASH_OPTCR_RDP_1                   (0x00000200UL)
+#define FLASH_OPTCR_RDP_2                   (0x00000400UL)
+#define FLASH_OPTCR_RDP_3                   (0x00000800UL)
+#define FLASH_OPTCR_RDP_4                   (0x00001000UL)
+#define FLASH_OPTCR_RDP_5                   (0x00002000UL)
+#define FLASH_OPTCR_RDP_6                   (0x00004000UL)
+#define FLASH_OPTCR_RDP_7                   (0x00008000UL)
+#define FLASH_OPTCR_nWRP                    (0x0FFF0000UL)
+#define FLASH_OPTCR_nWRP_0                  (0x00010000UL)
+#define FLASH_OPTCR_nWRP_1                  (0x00020000UL)
+#define FLASH_OPTCR_nWRP_2                  (0x00040000UL)
+#define FLASH_OPTCR_nWRP_3                  (0x00080000UL)
+#define FLASH_OPTCR_nWRP_4                  (0x00100000UL)
+#define FLASH_OPTCR_nWRP_5                  (0x00200000UL)
+#define FLASH_OPTCR_nWRP_6                  (0x00400000UL)
+#define FLASH_OPTCR_nWRP_7                  (0x00800000UL)
+#define FLASH_OPTCR_nWRP_8                  (0x01000000UL)
+#define FLASH_OPTCR_nWRP_9                  (0x02000000UL)
+#define FLASH_OPTCR_nWRP_10                 (0x04000000UL)
+#define FLASH_OPTCR_nWRP_11                 (0x08000000UL)
 
 /******************  Bits definition for FLASH_OPTCR1 register  ***************/
-#define FLASH_OPTCR1_nWRP                    ((uint32_t)0x0FFF0000)
-#define FLASH_OPTCR1_nWRP_0                  ((uint32_t)0x00010000)
-#define FLASH_OPTCR1_nWRP_1                  ((uint32_t)0x00020000)
-#define FLASH_OPTCR1_nWRP_2                  ((uint32_t)0x00040000)
-#define FLASH_OPTCR1_nWRP_3                  ((uint32_t)0x00080000)
-#define FLASH_OPTCR1_nWRP_4                  ((uint32_t)0x00100000)
-#define FLASH_OPTCR1_nWRP_5                  ((uint32_t)0x00200000)
-#define FLASH_OPTCR1_nWRP_6                  ((uint32_t)0x00400000)
-#define FLASH_OPTCR1_nWRP_7                  ((uint32_t)0x00800000)
-#define FLASH_OPTCR1_nWRP_8                  ((uint32_t)0x01000000)
-#define FLASH_OPTCR1_nWRP_9                  ((uint32_t)0x02000000)
-#define FLASH_OPTCR1_nWRP_10                 ((uint32_t)0x04000000)
-#define FLASH_OPTCR1_nWRP_11                 ((uint32_t)0x08000000)
+#define FLASH_OPTCR1_nWRP                    (0x0FFF0000UL)
+#define FLASH_OPTCR1_nWRP_0                  (0x00010000UL)
+#define FLASH_OPTCR1_nWRP_1                  (0x00020000UL)
+#define FLASH_OPTCR1_nWRP_2                  (0x00040000UL)
+#define FLASH_OPTCR1_nWRP_3                  (0x00080000UL)
+#define FLASH_OPTCR1_nWRP_4                  (0x00100000UL)
+#define FLASH_OPTCR1_nWRP_5                  (0x00200000UL)
+#define FLASH_OPTCR1_nWRP_6                  (0x00400000UL)
+#define FLASH_OPTCR1_nWRP_7                  (0x00800000UL)
+#define FLASH_OPTCR1_nWRP_8                  (0x01000000UL)
+#define FLASH_OPTCR1_nWRP_9                  (0x02000000UL)
+#define FLASH_OPTCR1_nWRP_10                 (0x04000000UL)
+#define FLASH_OPTCR1_nWRP_11                 (0x08000000UL)
 
 /******************************************************************************/
 /*                                                                            */
@@ -1720,235 +1716,235 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /******************  Bits definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODER0                    ((uint32_t)0x00000003)
-#define GPIO_MODER_MODER0_0                  ((uint32_t)0x00000001)
-#define GPIO_MODER_MODER0_1                  ((uint32_t)0x00000002)
+#define GPIO_MODER_MODER0                    (0x00000003UL)
+#define GPIO_MODER_MODER0_0                  (0x00000001UL)
+#define GPIO_MODER_MODER0_1                  (0x00000002UL)
 
-#define GPIO_MODER_MODER1                    ((uint32_t)0x0000000C)
-#define GPIO_MODER_MODER1_0                  ((uint32_t)0x00000004)
-#define GPIO_MODER_MODER1_1                  ((uint32_t)0x00000008)
+#define GPIO_MODER_MODER1                    (0x0000000CUL)
+#define GPIO_MODER_MODER1_0                  (0x00000004UL)
+#define GPIO_MODER_MODER1_1                  (0x00000008UL)
 
-#define GPIO_MODER_MODER2                    ((uint32_t)0x00000030)
-#define GPIO_MODER_MODER2_0                  ((uint32_t)0x00000010)
-#define GPIO_MODER_MODER2_1                  ((uint32_t)0x00000020)
+#define GPIO_MODER_MODER2                    (0x00000030UL)
+#define GPIO_MODER_MODER2_0                  (0x00000010UL)
+#define GPIO_MODER_MODER2_1                  (0x00000020UL)
 
-#define GPIO_MODER_MODER3                    ((uint32_t)0x000000C0)
-#define GPIO_MODER_MODER3_0                  ((uint32_t)0x00000040)
-#define GPIO_MODER_MODER3_1                  ((uint32_t)0x00000080)
+#define GPIO_MODER_MODER3                    (0x000000C0UL)
+#define GPIO_MODER_MODER3_0                  (0x00000040UL)
+#define GPIO_MODER_MODER3_1                  (0x00000080UL)
 
-#define GPIO_MODER_MODER4                    ((uint32_t)0x00000300)
-#define GPIO_MODER_MODER4_0                  ((uint32_t)0x00000100)
-#define GPIO_MODER_MODER4_1                  ((uint32_t)0x00000200)
+#define GPIO_MODER_MODER4                    (0x00000300UL)
+#define GPIO_MODER_MODER4_0                  (0x00000100UL)
+#define GPIO_MODER_MODER4_1                  (0x00000200UL)
 
-#define GPIO_MODER_MODER5                    ((uint32_t)0x00000C00)
-#define GPIO_MODER_MODER5_0                  ((uint32_t)0x00000400)
-#define GPIO_MODER_MODER5_1                  ((uint32_t)0x00000800)
+#define GPIO_MODER_MODER5                    (0x00000C00UL)
+#define GPIO_MODER_MODER5_0                  (0x00000400UL)
+#define GPIO_MODER_MODER5_1                  (0x00000800UL)
 
-#define GPIO_MODER_MODER6                    ((uint32_t)0x00003000)
-#define GPIO_MODER_MODER6_0                  ((uint32_t)0x00001000)
-#define GPIO_MODER_MODER6_1                  ((uint32_t)0x00002000)
+#define GPIO_MODER_MODER6                    (0x00003000UL)
+#define GPIO_MODER_MODER6_0                  (0x00001000UL)
+#define GPIO_MODER_MODER6_1                  (0x00002000UL)
 
-#define GPIO_MODER_MODER7                    ((uint32_t)0x0000C000)
-#define GPIO_MODER_MODER7_0                  ((uint32_t)0x00004000)
-#define GPIO_MODER_MODER7_1                  ((uint32_t)0x00008000)
+#define GPIO_MODER_MODER7                    (0x0000C000UL)
+#define GPIO_MODER_MODER7_0                  (0x00004000UL)
+#define GPIO_MODER_MODER7_1                  (0x00008000UL)
 
-#define GPIO_MODER_MODER8                    ((uint32_t)0x00030000)
-#define GPIO_MODER_MODER8_0                  ((uint32_t)0x00010000)
-#define GPIO_MODER_MODER8_1                  ((uint32_t)0x00020000)
+#define GPIO_MODER_MODER8                    (0x00030000UL)
+#define GPIO_MODER_MODER8_0                  (0x00010000UL)
+#define GPIO_MODER_MODER8_1                  (0x00020000UL)
 
-#define GPIO_MODER_MODER9                    ((uint32_t)0x000C0000)
-#define GPIO_MODER_MODER9_0                  ((uint32_t)0x00040000)
-#define GPIO_MODER_MODER9_1                  ((uint32_t)0x00080000)
+#define GPIO_MODER_MODER9                    (0x000C0000UL)
+#define GPIO_MODER_MODER9_0                  (0x00040000UL)
+#define GPIO_MODER_MODER9_1                  (0x00080000UL)
 
-#define GPIO_MODER_MODER10                   ((uint32_t)0x00300000)
-#define GPIO_MODER_MODER10_0                 ((uint32_t)0x00100000)
-#define GPIO_MODER_MODER10_1                 ((uint32_t)0x00200000)
+#define GPIO_MODER_MODER10                   (0x00300000UL)
+#define GPIO_MODER_MODER10_0                 (0x00100000UL)
+#define GPIO_MODER_MODER10_1                 (0x00200000UL)
 
-#define GPIO_MODER_MODER11                   ((uint32_t)0x00C00000)
-#define GPIO_MODER_MODER11_0                 ((uint32_t)0x00400000)
-#define GPIO_MODER_MODER11_1                 ((uint32_t)0x00800000)
+#define GPIO_MODER_MODER11                   (0x00C00000UL)
+#define GPIO_MODER_MODER11_0                 (0x00400000UL)
+#define GPIO_MODER_MODER11_1                 (0x00800000UL)
 
-#define GPIO_MODER_MODER12                   ((uint32_t)0x03000000)
-#define GPIO_MODER_MODER12_0                 ((uint32_t)0x01000000)
-#define GPIO_MODER_MODER12_1                 ((uint32_t)0x02000000)
+#define GPIO_MODER_MODER12                   (0x03000000UL)
+#define GPIO_MODER_MODER12_0                 (0x01000000UL)
+#define GPIO_MODER_MODER12_1                 (0x02000000UL)
 
-#define GPIO_MODER_MODER13                   ((uint32_t)0x0C000000)
-#define GPIO_MODER_MODER13_0                 ((uint32_t)0x04000000)
-#define GPIO_MODER_MODER13_1                 ((uint32_t)0x08000000)
+#define GPIO_MODER_MODER13                   (0x0C000000UL)
+#define GPIO_MODER_MODER13_0                 (0x04000000UL)
+#define GPIO_MODER_MODER13_1                 (0x08000000UL)
 
-#define GPIO_MODER_MODER14                   ((uint32_t)0x30000000)
-#define GPIO_MODER_MODER14_0                 ((uint32_t)0x10000000)
-#define GPIO_MODER_MODER14_1                 ((uint32_t)0x20000000)
+#define GPIO_MODER_MODER14                   (0x30000000UL)
+#define GPIO_MODER_MODER14_0                 (0x10000000UL)
+#define GPIO_MODER_MODER14_1                 (0x20000000UL)
 
-#define GPIO_MODER_MODER15                   ((uint32_t)0xC0000000)
-#define GPIO_MODER_MODER15_0                 ((uint32_t)0x40000000)
-#define GPIO_MODER_MODER15_1                 ((uint32_t)0x80000000)
+#define GPIO_MODER_MODER15                   (0xC0000000UL)
+#define GPIO_MODER_MODER15_0                 (0x40000000UL)
+#define GPIO_MODER_MODER15_1                 (0x80000000UL)
 
 /******************  Bits definition for GPIO_OTYPER register  ****************/
-#define GPIO_OTYPER_OT_0                     ((uint32_t)0x00000001)
-#define GPIO_OTYPER_OT_1                     ((uint32_t)0x00000002)
-#define GPIO_OTYPER_OT_2                     ((uint32_t)0x00000004)
-#define GPIO_OTYPER_OT_3                     ((uint32_t)0x00000008)
-#define GPIO_OTYPER_OT_4                     ((uint32_t)0x00000010)
-#define GPIO_OTYPER_OT_5                     ((uint32_t)0x00000020)
-#define GPIO_OTYPER_OT_6                     ((uint32_t)0x00000040)
-#define GPIO_OTYPER_OT_7                     ((uint32_t)0x00000080)
-#define GPIO_OTYPER_OT_8                     ((uint32_t)0x00000100)
-#define GPIO_OTYPER_OT_9                     ((uint32_t)0x00000200)
-#define GPIO_OTYPER_OT_10                    ((uint32_t)0x00000400)
-#define GPIO_OTYPER_OT_11                    ((uint32_t)0x00000800)
-#define GPIO_OTYPER_OT_12                    ((uint32_t)0x00001000)
-#define GPIO_OTYPER_OT_13                    ((uint32_t)0x00002000)
-#define GPIO_OTYPER_OT_14                    ((uint32_t)0x00004000)
-#define GPIO_OTYPER_OT_15                    ((uint32_t)0x00008000)
+#define GPIO_OTYPER_OT_0                     (0x00000001UL)
+#define GPIO_OTYPER_OT_1                     (0x00000002UL)
+#define GPIO_OTYPER_OT_2                     (0x00000004UL)
+#define GPIO_OTYPER_OT_3                     (0x00000008UL)
+#define GPIO_OTYPER_OT_4                     (0x00000010UL)
+#define GPIO_OTYPER_OT_5                     (0x00000020UL)
+#define GPIO_OTYPER_OT_6                     (0x00000040UL)
+#define GPIO_OTYPER_OT_7                     (0x00000080UL)
+#define GPIO_OTYPER_OT_8                     (0x00000100UL)
+#define GPIO_OTYPER_OT_9                     (0x00000200UL)
+#define GPIO_OTYPER_OT_10                    (0x00000400UL)
+#define GPIO_OTYPER_OT_11                    (0x00000800UL)
+#define GPIO_OTYPER_OT_12                    (0x00001000UL)
+#define GPIO_OTYPER_OT_13                    (0x00002000UL)
+#define GPIO_OTYPER_OT_14                    (0x00004000UL)
+#define GPIO_OTYPER_OT_15                    (0x00008000UL)
 
 /******************  Bits definition for GPIO_OSPEEDR register  ***************/
-#define GPIO_OSPEEDER_OSPEEDR0               ((uint32_t)0x00000003)
-#define GPIO_OSPEEDER_OSPEEDR0_0             ((uint32_t)0x00000001)
-#define GPIO_OSPEEDER_OSPEEDR0_1             ((uint32_t)0x00000002)
+#define GPIO_OSPEEDER_OSPEEDR0               (0x00000003UL)
+#define GPIO_OSPEEDER_OSPEEDR0_0             (0x00000001UL)
+#define GPIO_OSPEEDER_OSPEEDR0_1             (0x00000002UL)
 
-#define GPIO_OSPEEDER_OSPEEDR1               ((uint32_t)0x0000000C)
-#define GPIO_OSPEEDER_OSPEEDR1_0             ((uint32_t)0x00000004)
-#define GPIO_OSPEEDER_OSPEEDR1_1             ((uint32_t)0x00000008)
+#define GPIO_OSPEEDER_OSPEEDR1               (0x0000000CUL)
+#define GPIO_OSPEEDER_OSPEEDR1_0             (0x00000004UL)
+#define GPIO_OSPEEDER_OSPEEDR1_1             (0x00000008UL)
 
-#define GPIO_OSPEEDER_OSPEEDR2               ((uint32_t)0x00000030)
-#define GPIO_OSPEEDER_OSPEEDR2_0             ((uint32_t)0x00000010)
-#define GPIO_OSPEEDER_OSPEEDR2_1             ((uint32_t)0x00000020)
+#define GPIO_OSPEEDER_OSPEEDR2               (0x00000030UL)
+#define GPIO_OSPEEDER_OSPEEDR2_0             (0x00000010UL)
+#define GPIO_OSPEEDER_OSPEEDR2_1             (0x00000020UL)
 
-#define GPIO_OSPEEDER_OSPEEDR3               ((uint32_t)0x000000C0)
-#define GPIO_OSPEEDER_OSPEEDR3_0             ((uint32_t)0x00000040)
-#define GPIO_OSPEEDER_OSPEEDR3_1             ((uint32_t)0x00000080)
+#define GPIO_OSPEEDER_OSPEEDR3               (0x000000C0UL)
+#define GPIO_OSPEEDER_OSPEEDR3_0             (0x00000040UL)
+#define GPIO_OSPEEDER_OSPEEDR3_1             (0x00000080UL)
 
-#define GPIO_OSPEEDER_OSPEEDR4               ((uint32_t)0x00000300)
-#define GPIO_OSPEEDER_OSPEEDR4_0             ((uint32_t)0x00000100)
-#define GPIO_OSPEEDER_OSPEEDR4_1             ((uint32_t)0x00000200)
+#define GPIO_OSPEEDER_OSPEEDR4               (0x00000300UL)
+#define GPIO_OSPEEDER_OSPEEDR4_0             (0x00000100UL)
+#define GPIO_OSPEEDER_OSPEEDR4_1             (0x00000200UL)
 
-#define GPIO_OSPEEDER_OSPEEDR5               ((uint32_t)0x00000C00)
-#define GPIO_OSPEEDER_OSPEEDR5_0             ((uint32_t)0x00000400)
-#define GPIO_OSPEEDER_OSPEEDR5_1             ((uint32_t)0x00000800)
+#define GPIO_OSPEEDER_OSPEEDR5               (0x00000C00UL)
+#define GPIO_OSPEEDER_OSPEEDR5_0             (0x00000400UL)
+#define GPIO_OSPEEDER_OSPEEDR5_1             (0x00000800UL)
 
-#define GPIO_OSPEEDER_OSPEEDR6               ((uint32_t)0x00003000)
-#define GPIO_OSPEEDER_OSPEEDR6_0             ((uint32_t)0x00001000)
-#define GPIO_OSPEEDER_OSPEEDR6_1             ((uint32_t)0x00002000)
+#define GPIO_OSPEEDER_OSPEEDR6               (0x00003000UL)
+#define GPIO_OSPEEDER_OSPEEDR6_0             (0x00001000UL)
+#define GPIO_OSPEEDER_OSPEEDR6_1             (0x00002000UL)
 
-#define GPIO_OSPEEDER_OSPEEDR7               ((uint32_t)0x0000C000)
-#define GPIO_OSPEEDER_OSPEEDR7_0             ((uint32_t)0x00004000)
-#define GPIO_OSPEEDER_OSPEEDR7_1             ((uint32_t)0x00008000)
+#define GPIO_OSPEEDER_OSPEEDR7               (0x0000C000UL)
+#define GPIO_OSPEEDER_OSPEEDR7_0             (0x00004000UL)
+#define GPIO_OSPEEDER_OSPEEDR7_1             (0x00008000UL)
 
-#define GPIO_OSPEEDER_OSPEEDR8               ((uint32_t)0x00030000)
-#define GPIO_OSPEEDER_OSPEEDR8_0             ((uint32_t)0x00010000)
-#define GPIO_OSPEEDER_OSPEEDR8_1             ((uint32_t)0x00020000)
+#define GPIO_OSPEEDER_OSPEEDR8               (0x00030000UL)
+#define GPIO_OSPEEDER_OSPEEDR8_0             (0x00010000UL)
+#define GPIO_OSPEEDER_OSPEEDR8_1             (0x00020000UL)
 
-#define GPIO_OSPEEDER_OSPEEDR9               ((uint32_t)0x000C0000)
-#define GPIO_OSPEEDER_OSPEEDR9_0             ((uint32_t)0x00040000)
-#define GPIO_OSPEEDER_OSPEEDR9_1             ((uint32_t)0x00080000)
+#define GPIO_OSPEEDER_OSPEEDR9               (0x000C0000UL)
+#define GPIO_OSPEEDER_OSPEEDR9_0             (0x00040000UL)
+#define GPIO_OSPEEDER_OSPEEDR9_1             (0x00080000UL)
 
-#define GPIO_OSPEEDER_OSPEEDR10              ((uint32_t)0x00300000)
-#define GPIO_OSPEEDER_OSPEEDR10_0            ((uint32_t)0x00100000)
-#define GPIO_OSPEEDER_OSPEEDR10_1            ((uint32_t)0x00200000)
+#define GPIO_OSPEEDER_OSPEEDR10              (0x00300000UL)
+#define GPIO_OSPEEDER_OSPEEDR10_0            (0x00100000UL)
+#define GPIO_OSPEEDER_OSPEEDR10_1            (0x00200000UL)
 
-#define GPIO_OSPEEDER_OSPEEDR11              ((uint32_t)0x00C00000)
-#define GPIO_OSPEEDER_OSPEEDR11_0            ((uint32_t)0x00400000)
-#define GPIO_OSPEEDER_OSPEEDR11_1            ((uint32_t)0x00800000)
+#define GPIO_OSPEEDER_OSPEEDR11              (0x00C00000UL)
+#define GPIO_OSPEEDER_OSPEEDR11_0            (0x00400000UL)
+#define GPIO_OSPEEDER_OSPEEDR11_1            (0x00800000UL)
 
-#define GPIO_OSPEEDER_OSPEEDR12              ((uint32_t)0x03000000)
-#define GPIO_OSPEEDER_OSPEEDR12_0            ((uint32_t)0x01000000)
-#define GPIO_OSPEEDER_OSPEEDR12_1            ((uint32_t)0x02000000)
+#define GPIO_OSPEEDER_OSPEEDR12              (0x03000000UL)
+#define GPIO_OSPEEDER_OSPEEDR12_0            (0x01000000UL)
+#define GPIO_OSPEEDER_OSPEEDR12_1            (0x02000000UL)
 
-#define GPIO_OSPEEDER_OSPEEDR13              ((uint32_t)0x0C000000)
-#define GPIO_OSPEEDER_OSPEEDR13_0            ((uint32_t)0x04000000)
-#define GPIO_OSPEEDER_OSPEEDR13_1            ((uint32_t)0x08000000)
+#define GPIO_OSPEEDER_OSPEEDR13              (0x0C000000UL)
+#define GPIO_OSPEEDER_OSPEEDR13_0            (0x04000000UL)
+#define GPIO_OSPEEDER_OSPEEDR13_1            (0x08000000UL)
 
-#define GPIO_OSPEEDER_OSPEEDR14              ((uint32_t)0x30000000)
-#define GPIO_OSPEEDER_OSPEEDR14_0            ((uint32_t)0x10000000)
-#define GPIO_OSPEEDER_OSPEEDR14_1            ((uint32_t)0x20000000)
+#define GPIO_OSPEEDER_OSPEEDR14              (0x30000000UL)
+#define GPIO_OSPEEDER_OSPEEDR14_0            (0x10000000UL)
+#define GPIO_OSPEEDER_OSPEEDR14_1            (0x20000000UL)
 
-#define GPIO_OSPEEDER_OSPEEDR15              ((uint32_t)0xC0000000)
-#define GPIO_OSPEEDER_OSPEEDR15_0            ((uint32_t)0x40000000)
-#define GPIO_OSPEEDER_OSPEEDR15_1            ((uint32_t)0x80000000)
+#define GPIO_OSPEEDER_OSPEEDR15              (0xC0000000UL)
+#define GPIO_OSPEEDER_OSPEEDR15_0            (0x40000000UL)
+#define GPIO_OSPEEDER_OSPEEDR15_1            (0x80000000UL)
 
 /******************  Bits definition for GPIO_PUPDR register  *****************/
-#define GPIO_PUPDR_PUPDR0                    ((uint32_t)0x00000003)
-#define GPIO_PUPDR_PUPDR0_0                  ((uint32_t)0x00000001)
-#define GPIO_PUPDR_PUPDR0_1                  ((uint32_t)0x00000002)
+#define GPIO_PUPDR_PUPDR0                    (0x00000003UL)
+#define GPIO_PUPDR_PUPDR0_0                  (0x00000001UL)
+#define GPIO_PUPDR_PUPDR0_1                  (0x00000002UL)
 
-#define GPIO_PUPDR_PUPDR1                    ((uint32_t)0x0000000C)
-#define GPIO_PUPDR_PUPDR1_0                  ((uint32_t)0x00000004)
-#define GPIO_PUPDR_PUPDR1_1                  ((uint32_t)0x00000008)
+#define GPIO_PUPDR_PUPDR1                    (0x0000000CUL)
+#define GPIO_PUPDR_PUPDR1_0                  (0x00000004UL)
+#define GPIO_PUPDR_PUPDR1_1                  (0x00000008UL)
 
-#define GPIO_PUPDR_PUPDR2                    ((uint32_t)0x00000030)
-#define GPIO_PUPDR_PUPDR2_0                  ((uint32_t)0x00000010)
-#define GPIO_PUPDR_PUPDR2_1                  ((uint32_t)0x00000020)
+#define GPIO_PUPDR_PUPDR2                    (0x00000030UL)
+#define GPIO_PUPDR_PUPDR2_0                  (0x00000010UL)
+#define GPIO_PUPDR_PUPDR2_1                  (0x00000020UL)
 
-#define GPIO_PUPDR_PUPDR3                    ((uint32_t)0x000000C0)
-#define GPIO_PUPDR_PUPDR3_0                  ((uint32_t)0x00000040)
-#define GPIO_PUPDR_PUPDR3_1                  ((uint32_t)0x00000080)
+#define GPIO_PUPDR_PUPDR3                    (0x000000C0UL)
+#define GPIO_PUPDR_PUPDR3_0                  (0x00000040UL)
+#define GPIO_PUPDR_PUPDR3_1                  (0x00000080UL)
 
-#define GPIO_PUPDR_PUPDR4                    ((uint32_t)0x00000300)
-#define GPIO_PUPDR_PUPDR4_0                  ((uint32_t)0x00000100)
-#define GPIO_PUPDR_PUPDR4_1                  ((uint32_t)0x00000200)
+#define GPIO_PUPDR_PUPDR4                    (0x00000300UL)
+#define GPIO_PUPDR_PUPDR4_0                  (0x00000100UL)
+#define GPIO_PUPDR_PUPDR4_1                  (0x00000200UL)
 
-#define GPIO_PUPDR_PUPDR5                    ((uint32_t)0x00000C00)
-#define GPIO_PUPDR_PUPDR5_0                  ((uint32_t)0x00000400)
-#define GPIO_PUPDR_PUPDR5_1                  ((uint32_t)0x00000800)
+#define GPIO_PUPDR_PUPDR5                    (0x00000C00UL)
+#define GPIO_PUPDR_PUPDR5_0                  (0x00000400UL)
+#define GPIO_PUPDR_PUPDR5_1                  (0x00000800UL)
 
-#define GPIO_PUPDR_PUPDR6                    ((uint32_t)0x00003000)
-#define GPIO_PUPDR_PUPDR6_0                  ((uint32_t)0x00001000)
-#define GPIO_PUPDR_PUPDR6_1                  ((uint32_t)0x00002000)
+#define GPIO_PUPDR_PUPDR6                    (0x00003000UL)
+#define GPIO_PUPDR_PUPDR6_0                  (0x00001000UL)
+#define GPIO_PUPDR_PUPDR6_1                  (0x00002000UL)
 
-#define GPIO_PUPDR_PUPDR7                    ((uint32_t)0x0000C000)
-#define GPIO_PUPDR_PUPDR7_0                  ((uint32_t)0x00004000)
-#define GPIO_PUPDR_PUPDR7_1                  ((uint32_t)0x00008000)
+#define GPIO_PUPDR_PUPDR7                    (0x0000C000UL)
+#define GPIO_PUPDR_PUPDR7_0                  (0x00004000UL)
+#define GPIO_PUPDR_PUPDR7_1                  (0x00008000UL)
 
-#define GPIO_PUPDR_PUPDR8                    ((uint32_t)0x00030000)
-#define GPIO_PUPDR_PUPDR8_0                  ((uint32_t)0x00010000)
-#define GPIO_PUPDR_PUPDR8_1                  ((uint32_t)0x00020000)
+#define GPIO_PUPDR_PUPDR8                    (0x00030000UL)
+#define GPIO_PUPDR_PUPDR8_0                  (0x00010000UL)
+#define GPIO_PUPDR_PUPDR8_1                  (0x00020000UL)
 
-#define GPIO_PUPDR_PUPDR9                    ((uint32_t)0x000C0000)
-#define GPIO_PUPDR_PUPDR9_0                  ((uint32_t)0x00040000)
-#define GPIO_PUPDR_PUPDR9_1                  ((uint32_t)0x00080000)
+#define GPIO_PUPDR_PUPDR9                    (0x000C0000UL)
+#define GPIO_PUPDR_PUPDR9_0                  (0x00040000UL)
+#define GPIO_PUPDR_PUPDR9_1                  (0x00080000UL)
 
-#define GPIO_PUPDR_PUPDR10                   ((uint32_t)0x00300000)
-#define GPIO_PUPDR_PUPDR10_0                 ((uint32_t)0x00100000)
-#define GPIO_PUPDR_PUPDR10_1                 ((uint32_t)0x00200000)
+#define GPIO_PUPDR_PUPDR10                   (0x00300000UL)
+#define GPIO_PUPDR_PUPDR10_0                 (0x00100000UL)
+#define GPIO_PUPDR_PUPDR10_1                 (0x00200000UL)
 
-#define GPIO_PUPDR_PUPDR11                   ((uint32_t)0x00C00000)
-#define GPIO_PUPDR_PUPDR11_0                 ((uint32_t)0x00400000)
-#define GPIO_PUPDR_PUPDR11_1                 ((uint32_t)0x00800000)
+#define GPIO_PUPDR_PUPDR11                   (0x00C00000UL)
+#define GPIO_PUPDR_PUPDR11_0                 (0x00400000UL)
+#define GPIO_PUPDR_PUPDR11_1                 (0x00800000UL)
 
-#define GPIO_PUPDR_PUPDR12                   ((uint32_t)0x03000000)
-#define GPIO_PUPDR_PUPDR12_0                 ((uint32_t)0x01000000)
-#define GPIO_PUPDR_PUPDR12_1                 ((uint32_t)0x02000000)
+#define GPIO_PUPDR_PUPDR12                   (0x03000000UL)
+#define GPIO_PUPDR_PUPDR12_0                 (0x01000000UL)
+#define GPIO_PUPDR_PUPDR12_1                 (0x02000000UL)
 
-#define GPIO_PUPDR_PUPDR13                   ((uint32_t)0x0C000000)
-#define GPIO_PUPDR_PUPDR13_0                 ((uint32_t)0x04000000)
-#define GPIO_PUPDR_PUPDR13_1                 ((uint32_t)0x08000000)
+#define GPIO_PUPDR_PUPDR13                   (0x0C000000UL)
+#define GPIO_PUPDR_PUPDR13_0                 (0x04000000UL)
+#define GPIO_PUPDR_PUPDR13_1                 (0x08000000UL)
 
-#define GPIO_PUPDR_PUPDR14                   ((uint32_t)0x30000000)
-#define GPIO_PUPDR_PUPDR14_0                 ((uint32_t)0x10000000)
-#define GPIO_PUPDR_PUPDR14_1                 ((uint32_t)0x20000000)
+#define GPIO_PUPDR_PUPDR14                   (0x30000000UL)
+#define GPIO_PUPDR_PUPDR14_0                 (0x10000000UL)
+#define GPIO_PUPDR_PUPDR14_1                 (0x20000000UL)
 
-#define GPIO_PUPDR_PUPDR15                   ((uint32_t)0xC0000000)
-#define GPIO_PUPDR_PUPDR15_0                 ((uint32_t)0x40000000)
-#define GPIO_PUPDR_PUPDR15_1                 ((uint32_t)0x80000000)
+#define GPIO_PUPDR_PUPDR15                   (0xC0000000UL)
+#define GPIO_PUPDR_PUPDR15_0                 (0x40000000UL)
+#define GPIO_PUPDR_PUPDR15_1                 (0x80000000UL)
 
 /******************  Bits definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_IDR_0                       ((uint32_t)0x00000001)
-#define GPIO_IDR_IDR_1                       ((uint32_t)0x00000002)
-#define GPIO_IDR_IDR_2                       ((uint32_t)0x00000004)
-#define GPIO_IDR_IDR_3                       ((uint32_t)0x00000008)
-#define GPIO_IDR_IDR_4                       ((uint32_t)0x00000010)
-#define GPIO_IDR_IDR_5                       ((uint32_t)0x00000020)
-#define GPIO_IDR_IDR_6                       ((uint32_t)0x00000040)
-#define GPIO_IDR_IDR_7                       ((uint32_t)0x00000080)
-#define GPIO_IDR_IDR_8                       ((uint32_t)0x00000100)
-#define GPIO_IDR_IDR_9                       ((uint32_t)0x00000200)
-#define GPIO_IDR_IDR_10                      ((uint32_t)0x00000400)
-#define GPIO_IDR_IDR_11                      ((uint32_t)0x00000800)
-#define GPIO_IDR_IDR_12                      ((uint32_t)0x00001000)
-#define GPIO_IDR_IDR_13                      ((uint32_t)0x00002000)
-#define GPIO_IDR_IDR_14                      ((uint32_t)0x00004000)
-#define GPIO_IDR_IDR_15                      ((uint32_t)0x00008000)
+#define GPIO_IDR_IDR_0                       (0x00000001UL)
+#define GPIO_IDR_IDR_1                       (0x00000002UL)
+#define GPIO_IDR_IDR_2                       (0x00000004UL)
+#define GPIO_IDR_IDR_3                       (0x00000008UL)
+#define GPIO_IDR_IDR_4                       (0x00000010UL)
+#define GPIO_IDR_IDR_5                       (0x00000020UL)
+#define GPIO_IDR_IDR_6                       (0x00000040UL)
+#define GPIO_IDR_IDR_7                       (0x00000080UL)
+#define GPIO_IDR_IDR_8                       (0x00000100UL)
+#define GPIO_IDR_IDR_9                       (0x00000200UL)
+#define GPIO_IDR_IDR_10                      (0x00000400UL)
+#define GPIO_IDR_IDR_11                      (0x00000800UL)
+#define GPIO_IDR_IDR_12                      (0x00001000UL)
+#define GPIO_IDR_IDR_13                      (0x00002000UL)
+#define GPIO_IDR_IDR_14                      (0x00004000UL)
+#define GPIO_IDR_IDR_15                      (0x00008000UL)
 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
 #define GPIO_OTYPER_IDR_0                    GPIO_IDR_IDR_0
 #define GPIO_OTYPER_IDR_1                    GPIO_IDR_IDR_1
@@ -1968,22 +1964,22 @@ USB_OTG_HostChannelTypeDef;
 #define GPIO_OTYPER_IDR_15                   GPIO_IDR_IDR_15
 
 /******************  Bits definition for GPIO_ODR register  *******************/
-#define GPIO_ODR_ODR_0                       ((uint32_t)0x00000001)
-#define GPIO_ODR_ODR_1                       ((uint32_t)0x00000002)
-#define GPIO_ODR_ODR_2                       ((uint32_t)0x00000004)
-#define GPIO_ODR_ODR_3                       ((uint32_t)0x00000008)
-#define GPIO_ODR_ODR_4                       ((uint32_t)0x00000010)
-#define GPIO_ODR_ODR_5                       ((uint32_t)0x00000020)
-#define GPIO_ODR_ODR_6                       ((uint32_t)0x00000040)
-#define GPIO_ODR_ODR_7                       ((uint32_t)0x00000080)
-#define GPIO_ODR_ODR_8                       ((uint32_t)0x00000100)
-#define GPIO_ODR_ODR_9                       ((uint32_t)0x00000200)
-#define GPIO_ODR_ODR_10                      ((uint32_t)0x00000400)
-#define GPIO_ODR_ODR_11                      ((uint32_t)0x00000800)
-#define GPIO_ODR_ODR_12                      ((uint32_t)0x00001000)
-#define GPIO_ODR_ODR_13                      ((uint32_t)0x00002000)
-#define GPIO_ODR_ODR_14                      ((uint32_t)0x00004000)
-#define GPIO_ODR_ODR_15                      ((uint32_t)0x00008000)
+#define GPIO_ODR_ODR_0                       (0x00000001UL)
+#define GPIO_ODR_ODR_1                       (0x00000002UL)
+#define GPIO_ODR_ODR_2                       (0x00000004UL)
+#define GPIO_ODR_ODR_3                       (0x00000008UL)
+#define GPIO_ODR_ODR_4                       (0x00000010UL)
+#define GPIO_ODR_ODR_5                       (0x00000020UL)
+#define GPIO_ODR_ODR_6                       (0x00000040UL)
+#define GPIO_ODR_ODR_7                       (0x00000080UL)
+#define GPIO_ODR_ODR_8                       (0x00000100UL)
+#define GPIO_ODR_ODR_9                       (0x00000200UL)
+#define GPIO_ODR_ODR_10                      (0x00000400UL)
+#define GPIO_ODR_ODR_11                      (0x00000800UL)
+#define GPIO_ODR_ODR_12                      (0x00001000UL)
+#define GPIO_ODR_ODR_13                      (0x00002000UL)
+#define GPIO_ODR_ODR_14                      (0x00004000UL)
+#define GPIO_ODR_ODR_15                      (0x00008000UL)
 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
 #define GPIO_OTYPER_ODR_0                    GPIO_ODR_ODR_0
 #define GPIO_OTYPER_ODR_1                    GPIO_ODR_ODR_1
@@ -2003,57 +1999,57 @@ USB_OTG_HostChannelTypeDef;
 #define GPIO_OTYPER_ODR_15                   GPIO_ODR_ODR_15
 
 /******************  Bits definition for GPIO_BSRR register  ******************/
-#define GPIO_BSRR_BS_0                       ((uint32_t)0x00000001)
-#define GPIO_BSRR_BS_1                       ((uint32_t)0x00000002)
-#define GPIO_BSRR_BS_2                       ((uint32_t)0x00000004)
-#define GPIO_BSRR_BS_3                       ((uint32_t)0x00000008)
-#define GPIO_BSRR_BS_4                       ((uint32_t)0x00000010)
-#define GPIO_BSRR_BS_5                       ((uint32_t)0x00000020)
-#define GPIO_BSRR_BS_6                       ((uint32_t)0x00000040)
-#define GPIO_BSRR_BS_7                       ((uint32_t)0x00000080)
-#define GPIO_BSRR_BS_8                       ((uint32_t)0x00000100)
-#define GPIO_BSRR_BS_9                       ((uint32_t)0x00000200)
-#define GPIO_BSRR_BS_10                      ((uint32_t)0x00000400)
-#define GPIO_BSRR_BS_11                      ((uint32_t)0x00000800)
-#define GPIO_BSRR_BS_12                      ((uint32_t)0x00001000)
-#define GPIO_BSRR_BS_13                      ((uint32_t)0x00002000)
-#define GPIO_BSRR_BS_14                      ((uint32_t)0x00004000)
-#define GPIO_BSRR_BS_15                      ((uint32_t)0x00008000)
-#define GPIO_BSRR_BR_0                       ((uint32_t)0x00010000)
-#define GPIO_BSRR_BR_1                       ((uint32_t)0x00020000)
-#define GPIO_BSRR_BR_2                       ((uint32_t)0x00040000)
-#define GPIO_BSRR_BR_3                       ((uint32_t)0x00080000)
-#define GPIO_BSRR_BR_4                       ((uint32_t)0x00100000)
-#define GPIO_BSRR_BR_5                       ((uint32_t)0x00200000)
-#define GPIO_BSRR_BR_6                       ((uint32_t)0x00400000)
-#define GPIO_BSRR_BR_7                       ((uint32_t)0x00800000)
-#define GPIO_BSRR_BR_8                       ((uint32_t)0x01000000)
-#define GPIO_BSRR_BR_9                       ((uint32_t)0x02000000)
-#define GPIO_BSRR_BR_10                      ((uint32_t)0x04000000)
-#define GPIO_BSRR_BR_11                      ((uint32_t)0x08000000)
-#define GPIO_BSRR_BR_12                      ((uint32_t)0x10000000)
-#define GPIO_BSRR_BR_13                      ((uint32_t)0x20000000)
-#define GPIO_BSRR_BR_14                      ((uint32_t)0x40000000)
-#define GPIO_BSRR_BR_15                      ((uint32_t)0x80000000)
+#define GPIO_BSRR_BS_0                       (0x00000001UL)
+#define GPIO_BSRR_BS_1                       (0x00000002UL)
+#define GPIO_BSRR_BS_2                       (0x00000004UL)
+#define GPIO_BSRR_BS_3                       (0x00000008UL)
+#define GPIO_BSRR_BS_4                       (0x00000010UL)
+#define GPIO_BSRR_BS_5                       (0x00000020UL)
+#define GPIO_BSRR_BS_6                       (0x00000040UL)
+#define GPIO_BSRR_BS_7                       (0x00000080UL)
+#define GPIO_BSRR_BS_8                       (0x00000100UL)
+#define GPIO_BSRR_BS_9                       (0x00000200UL)
+#define GPIO_BSRR_BS_10                      (0x00000400UL)
+#define GPIO_BSRR_BS_11                      (0x00000800UL)
+#define GPIO_BSRR_BS_12                      (0x00001000UL)
+#define GPIO_BSRR_BS_13                      (0x00002000UL)
+#define GPIO_BSRR_BS_14                      (0x00004000UL)
+#define GPIO_BSRR_BS_15                      (0x00008000UL)
+#define GPIO_BSRR_BR_0                       (0x00010000UL)
+#define GPIO_BSRR_BR_1                       (0x00020000UL)
+#define GPIO_BSRR_BR_2                       (0x00040000UL)
+#define GPIO_BSRR_BR_3                       (0x00080000UL)
+#define GPIO_BSRR_BR_4                       (0x00100000UL)
+#define GPIO_BSRR_BR_5                       (0x00200000UL)
+#define GPIO_BSRR_BR_6                       (0x00400000UL)
+#define GPIO_BSRR_BR_7                       (0x00800000UL)
+#define GPIO_BSRR_BR_8                       (0x01000000UL)
+#define GPIO_BSRR_BR_9                       (0x02000000UL)
+#define GPIO_BSRR_BR_10                      (0x04000000UL)
+#define GPIO_BSRR_BR_11                      (0x08000000UL)
+#define GPIO_BSRR_BR_12                      (0x10000000UL)
+#define GPIO_BSRR_BR_13                      (0x20000000UL)
+#define GPIO_BSRR_BR_14                      (0x40000000UL)
+#define GPIO_BSRR_BR_15                      (0x80000000UL)
 
 /****************** Bit definition for GPIO_LCKR register *********************/
-#define GPIO_LCKR_LCK0                       ((uint32_t)0x00000001)
-#define GPIO_LCKR_LCK1                       ((uint32_t)0x00000002)
-#define GPIO_LCKR_LCK2                       ((uint32_t)0x00000004)
-#define GPIO_LCKR_LCK3                       ((uint32_t)0x00000008)
-#define GPIO_LCKR_LCK4                       ((uint32_t)0x00000010)
-#define GPIO_LCKR_LCK5                       ((uint32_t)0x00000020)
-#define GPIO_LCKR_LCK6                       ((uint32_t)0x00000040)
-#define GPIO_LCKR_LCK7                       ((uint32_t)0x00000080)
-#define GPIO_LCKR_LCK8                       ((uint32_t)0x00000100)
-#define GPIO_LCKR_LCK9                       ((uint32_t)0x00000200)
-#define GPIO_LCKR_LCK10                      ((uint32_t)0x00000400)
-#define GPIO_LCKR_LCK11                      ((uint32_t)0x00000800)
-#define GPIO_LCKR_LCK12                      ((uint32_t)0x00001000)
-#define GPIO_LCKR_LCK13                      ((uint32_t)0x00002000)
-#define GPIO_LCKR_LCK14                      ((uint32_t)0x00004000)
-#define GPIO_LCKR_LCK15                      ((uint32_t)0x00008000)
-#define GPIO_LCKR_LCKK                       ((uint32_t)0x00010000)
+#define GPIO_LCKR_LCK0                       (0x00000001UL)
+#define GPIO_LCKR_LCK1                       (0x00000002UL)
+#define GPIO_LCKR_LCK2                       (0x00000004UL)
+#define GPIO_LCKR_LCK3                       (0x00000008UL)
+#define GPIO_LCKR_LCK4                       (0x00000010UL)
+#define GPIO_LCKR_LCK5                       (0x00000020UL)
+#define GPIO_LCKR_LCK6                       (0x00000040UL)
+#define GPIO_LCKR_LCK7                       (0x00000080UL)
+#define GPIO_LCKR_LCK8                       (0x00000100UL)
+#define GPIO_LCKR_LCK9                       (0x00000200UL)
+#define GPIO_LCKR_LCK10                      (0x00000400UL)
+#define GPIO_LCKR_LCK11                      (0x00000800UL)
+#define GPIO_LCKR_LCK12                      (0x00001000UL)
+#define GPIO_LCKR_LCK13                      (0x00002000UL)
+#define GPIO_LCKR_LCK14                      (0x00004000UL)
+#define GPIO_LCKR_LCK15                      (0x00008000UL)
+#define GPIO_LCKR_LCKK                       (0x00010000UL)
 
 /******************************************************************************/
 /*                                                                            */
@@ -2061,97 +2057,97 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for I2C_CR1 register  ********************/
-#define  I2C_CR1_PE                          ((uint32_t)0x00000001)     /*!<Peripheral Enable                             */
-#define  I2C_CR1_SMBUS                       ((uint32_t)0x00000002)     /*!<SMBus Mode                                    */
-#define  I2C_CR1_SMBTYPE                     ((uint32_t)0x00000008)     /*!<SMBus Type                                    */
-#define  I2C_CR1_ENARP                       ((uint32_t)0x00000010)     /*!<ARP Enable                                    */
-#define  I2C_CR1_ENPEC                       ((uint32_t)0x00000020)     /*!<PEC Enable                                    */
-#define  I2C_CR1_ENGC                        ((uint32_t)0x00000040)     /*!<General Call Enable                           */
-#define  I2C_CR1_NOSTRETCH                   ((uint32_t)0x00000080)     /*!<Clock Stretching Disable (Slave mode)  */
-#define  I2C_CR1_START                       ((uint32_t)0x00000100)     /*!<Start Generation                              */
-#define  I2C_CR1_STOP                        ((uint32_t)0x00000200)     /*!<Stop Generation                               */
-#define  I2C_CR1_ACK                         ((uint32_t)0x00000400)     /*!<Acknowledge Enable                            */
-#define  I2C_CR1_POS                         ((uint32_t)0x00000800)     /*!<Acknowledge/PEC Position (for data reception) */
-#define  I2C_CR1_PEC                         ((uint32_t)0x00001000)     /*!<Packet Error Checking                         */
-#define  I2C_CR1_ALERT                       ((uint32_t)0x00002000)     /*!<SMBus Alert                                   */
-#define  I2C_CR1_SWRST                       ((uint32_t)0x00008000)     /*!<Software Reset                                */
+#define  I2C_CR1_PE                          (0x00000001UL)     /*!<Peripheral Enable                             */
+#define  I2C_CR1_SMBUS                       (0x00000002UL)     /*!<SMBus Mode                                    */
+#define  I2C_CR1_SMBTYPE                     (0x00000008UL)     /*!<SMBus Type                                    */
+#define  I2C_CR1_ENARP                       (0x00000010UL)     /*!<ARP Enable                                    */
+#define  I2C_CR1_ENPEC                       (0x00000020UL)     /*!<PEC Enable                                    */
+#define  I2C_CR1_ENGC                        (0x00000040UL)     /*!<General Call Enable                           */
+#define  I2C_CR1_NOSTRETCH                   (0x00000080UL)     /*!<Clock Stretching Disable (Slave mode)  */
+#define  I2C_CR1_START                       (0x00000100UL)     /*!<Start Generation                              */
+#define  I2C_CR1_STOP                        (0x00000200UL)     /*!<Stop Generation                               */
+#define  I2C_CR1_ACK                         (0x00000400UL)     /*!<Acknowledge Enable                            */
+#define  I2C_CR1_POS                         (0x00000800UL)     /*!<Acknowledge/PEC Position (for data reception) */
+#define  I2C_CR1_PEC                         (0x00001000UL)     /*!<Packet Error Checking                         */
+#define  I2C_CR1_ALERT                       (0x00002000UL)     /*!<SMBus Alert                                   */
+#define  I2C_CR1_SWRST                       (0x00008000UL)     /*!<Software Reset                                */
 
 /*******************  Bit definition for I2C_CR2 register  ********************/
-#define  I2C_CR2_FREQ                        ((uint32_t)0x0000003F)     /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */
-#define  I2C_CR2_FREQ_0                      ((uint32_t)0x00000001)     /*!<Bit 0 */
-#define  I2C_CR2_FREQ_1                      ((uint32_t)0x00000002)     /*!<Bit 1 */
-#define  I2C_CR2_FREQ_2                      ((uint32_t)0x00000004)     /*!<Bit 2 */
-#define  I2C_CR2_FREQ_3                      ((uint32_t)0x00000008)     /*!<Bit 3 */
-#define  I2C_CR2_FREQ_4                      ((uint32_t)0x00000010)     /*!<Bit 4 */
-#define  I2C_CR2_FREQ_5                      ((uint32_t)0x00000020)     /*!<Bit 5 */
+#define  I2C_CR2_FREQ                        (0x0000003FUL)     /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */
+#define  I2C_CR2_FREQ_0                      (0x00000001UL)     /*!<Bit 0 */
+#define  I2C_CR2_FREQ_1                      (0x00000002UL)     /*!<Bit 1 */
+#define  I2C_CR2_FREQ_2                      (0x00000004UL)     /*!<Bit 2 */
+#define  I2C_CR2_FREQ_3                      (0x00000008UL)     /*!<Bit 3 */
+#define  I2C_CR2_FREQ_4                      (0x00000010UL)     /*!<Bit 4 */
+#define  I2C_CR2_FREQ_5                      (0x00000020UL)     /*!<Bit 5 */
 
-#define  I2C_CR2_ITERREN                     ((uint32_t)0x00000100)     /*!<Error Interrupt Enable  */
-#define  I2C_CR2_ITEVTEN                     ((uint32_t)0x00000200)     /*!<Event Interrupt Enable  */
-#define  I2C_CR2_ITBUFEN                     ((uint32_t)0x00000400)     /*!<Buffer Interrupt Enable */
-#define  I2C_CR2_DMAEN                       ((uint32_t)0x00000800)     /*!<DMA Requests Enable     */
-#define  I2C_CR2_LAST                        ((uint32_t)0x00001000)     /*!<DMA Last Transfer       */
+#define  I2C_CR2_ITERREN                     (0x00000100UL)     /*!<Error Interrupt Enable  */
+#define  I2C_CR2_ITEVTEN                     (0x00000200UL)     /*!<Event Interrupt Enable  */
+#define  I2C_CR2_ITBUFEN                     (0x00000400UL)     /*!<Buffer Interrupt Enable */
+#define  I2C_CR2_DMAEN                       (0x00000800UL)     /*!<DMA Requests Enable     */
+#define  I2C_CR2_LAST                        (0x00001000UL)     /*!<DMA Last Transfer       */
 
 /*******************  Bit definition for I2C_OAR1 register  *******************/
-#define  I2C_OAR1_ADD1_7                     ((uint32_t)0x000000FE)     /*!<Interface Address */
-#define  I2C_OAR1_ADD8_9                     ((uint32_t)0x00000300)     /*!<Interface Address */
+#define  I2C_OAR1_ADD1_7                     (0x000000FEUL)     /*!<Interface Address */
+#define  I2C_OAR1_ADD8_9                     (0x00000300UL)     /*!<Interface Address */
 
-#define  I2C_OAR1_ADD0                       ((uint32_t)0x00000001)     /*!<Bit 0 */
-#define  I2C_OAR1_ADD1                       ((uint32_t)0x00000002)     /*!<Bit 1 */
-#define  I2C_OAR1_ADD2                       ((uint32_t)0x00000004)     /*!<Bit 2 */
-#define  I2C_OAR1_ADD3                       ((uint32_t)0x00000008)     /*!<Bit 3 */
-#define  I2C_OAR1_ADD4                       ((uint32_t)0x00000010)     /*!<Bit 4 */
-#define  I2C_OAR1_ADD5                       ((uint32_t)0x00000020)     /*!<Bit 5 */
-#define  I2C_OAR1_ADD6                       ((uint32_t)0x00000040)     /*!<Bit 6 */
-#define  I2C_OAR1_ADD7                       ((uint32_t)0x00000080)     /*!<Bit 7 */
-#define  I2C_OAR1_ADD8                       ((uint32_t)0x00000100)     /*!<Bit 8 */
-#define  I2C_OAR1_ADD9                       ((uint32_t)0x00000200)     /*!<Bit 9 */
+#define  I2C_OAR1_ADD0                       (0x00000001UL)     /*!<Bit 0 */
+#define  I2C_OAR1_ADD1                       (0x00000002UL)     /*!<Bit 1 */
+#define  I2C_OAR1_ADD2                       (0x00000004UL)     /*!<Bit 2 */
+#define  I2C_OAR1_ADD3                       (0x00000008UL)     /*!<Bit 3 */
+#define  I2C_OAR1_ADD4                       (0x00000010UL)     /*!<Bit 4 */
+#define  I2C_OAR1_ADD5                       (0x00000020UL)     /*!<Bit 5 */
+#define  I2C_OAR1_ADD6                       (0x00000040UL)     /*!<Bit 6 */
+#define  I2C_OAR1_ADD7                       (0x00000080UL)     /*!<Bit 7 */
+#define  I2C_OAR1_ADD8                       (0x00000100UL)     /*!<Bit 8 */
+#define  I2C_OAR1_ADD9                       (0x00000200UL)     /*!<Bit 9 */
 
-#define  I2C_OAR1_ADDMODE                    ((uint32_t)0x00008000)     /*!<Addressing Mode (Slave mode) */
+#define  I2C_OAR1_ADDMODE                    (0x00008000UL)     /*!<Addressing Mode (Slave mode) */
 
 /*******************  Bit definition for I2C_OAR2 register  *******************/
-#define  I2C_OAR2_ENDUAL                     ((uint32_t)0x00000001)        /*!<Dual addressing mode enable */
-#define  I2C_OAR2_ADD2                       ((uint32_t)0x000000FE)        /*!<Interface address           */
+#define  I2C_OAR2_ENDUAL                     (0x00000001UL)        /*!<Dual addressing mode enable */
+#define  I2C_OAR2_ADD2                       (0x000000FEUL)        /*!<Interface address           */
 
 /********************  Bit definition for I2C_DR register  ********************/
-#define  I2C_DR_DR                           ((uint32_t)0x000000FF)        /*!<8-bit Data Register         */
+#define  I2C_DR_DR                           (0x000000FFUL)        /*!<8-bit Data Register         */
 
 /*******************  Bit definition for I2C_SR1 register  ********************/
-#define  I2C_SR1_SB                          ((uint32_t)0x00000001)     /*!<Start Bit (Master mode)                  */
-#define  I2C_SR1_ADDR                        ((uint32_t)0x00000002)     /*!<Address sent (master mode)/matched (slave mode) */
-#define  I2C_SR1_BTF                         ((uint32_t)0x00000004)     /*!<Byte Transfer Finished                          */
-#define  I2C_SR1_ADD10                       ((uint32_t)0x00000008)     /*!<10-bit header sent (Master mode)         */
-#define  I2C_SR1_STOPF                       ((uint32_t)0x00000010)     /*!<Stop detection (Slave mode)              */
-#define  I2C_SR1_RXNE                        ((uint32_t)0x00000040)     /*!<Data Register not Empty (receivers)      */
-#define  I2C_SR1_TXE                         ((uint32_t)0x00000080)     /*!<Data Register Empty (transmitters)       */
-#define  I2C_SR1_BERR                        ((uint32_t)0x00000100)     /*!<Bus Error                                       */
-#define  I2C_SR1_ARLO                        ((uint32_t)0x00000200)     /*!<Arbitration Lost (master mode)           */
-#define  I2C_SR1_AF                          ((uint32_t)0x00000400)     /*!<Acknowledge Failure                             */
-#define  I2C_SR1_OVR                         ((uint32_t)0x00000800)     /*!<Overrun/Underrun                                */
-#define  I2C_SR1_PECERR                      ((uint32_t)0x00001000)     /*!<PEC Error in reception                          */
-#define  I2C_SR1_TIMEOUT                     ((uint32_t)0x00004000)     /*!<Timeout or Tlow Error                           */
-#define  I2C_SR1_SMBALERT                    ((uint32_t)0x00008000)     /*!<SMBus Alert                                     */
+#define  I2C_SR1_SB                          (0x00000001UL)     /*!<Start Bit (Master mode)                  */
+#define  I2C_SR1_ADDR                        (0x00000002UL)     /*!<Address sent (master mode)/matched (slave mode) */
+#define  I2C_SR1_BTF                         (0x00000004UL)     /*!<Byte Transfer Finished                          */
+#define  I2C_SR1_ADD10                       (0x00000008UL)     /*!<10-bit header sent (Master mode)         */
+#define  I2C_SR1_STOPF                       (0x00000010UL)     /*!<Stop detection (Slave mode)              */
+#define  I2C_SR1_RXNE                        (0x00000040UL)     /*!<Data Register not Empty (receivers)      */
+#define  I2C_SR1_TXE                         (0x00000080UL)     /*!<Data Register Empty (transmitters)       */
+#define  I2C_SR1_BERR                        (0x00000100UL)     /*!<Bus Error                                       */
+#define  I2C_SR1_ARLO                        (0x00000200UL)     /*!<Arbitration Lost (master mode)           */
+#define  I2C_SR1_AF                          (0x00000400UL)     /*!<Acknowledge Failure                             */
+#define  I2C_SR1_OVR                         (0x00000800UL)     /*!<Overrun/Underrun                                */
+#define  I2C_SR1_PECERR                      (0x00001000UL)     /*!<PEC Error in reception                          */
+#define  I2C_SR1_TIMEOUT                     (0x00004000UL)     /*!<Timeout or Tlow Error                           */
+#define  I2C_SR1_SMBALERT                    (0x00008000UL)     /*!<SMBus Alert                                     */
 
 /*******************  Bit definition for I2C_SR2 register  ********************/
-#define  I2C_SR2_MSL                         ((uint32_t)0x00000001)     /*!<Master/Slave                              */
-#define  I2C_SR2_BUSY                        ((uint32_t)0x00000002)     /*!<Bus Busy                                  */
-#define  I2C_SR2_TRA                         ((uint32_t)0x00000004)     /*!<Transmitter/Receiver                      */
-#define  I2C_SR2_GENCALL                     ((uint32_t)0x00000010)     /*!<General Call Address (Slave mode)  */
-#define  I2C_SR2_SMBDEFAULT                  ((uint32_t)0x00000020)     /*!<SMBus Device Default Address (Slave mode) */
-#define  I2C_SR2_SMBHOST                     ((uint32_t)0x00000040)     /*!<SMBus Host Header (Slave mode)     */
-#define  I2C_SR2_DUALF                       ((uint32_t)0x00000080)     /*!<Dual Flag (Slave mode)             */
-#define  I2C_SR2_PEC                         ((uint32_t)0x0000FF00)     /*!<Packet Error Checking Register            */
+#define  I2C_SR2_MSL                         (0x00000001UL)     /*!<Master/Slave                              */
+#define  I2C_SR2_BUSY                        (0x00000002UL)     /*!<Bus Busy                                  */
+#define  I2C_SR2_TRA                         (0x00000004UL)     /*!<Transmitter/Receiver                      */
+#define  I2C_SR2_GENCALL                     (0x00000010UL)     /*!<General Call Address (Slave mode)  */
+#define  I2C_SR2_SMBDEFAULT                  (0x00000020UL)     /*!<SMBus Device Default Address (Slave mode) */
+#define  I2C_SR2_SMBHOST                     (0x00000040UL)     /*!<SMBus Host Header (Slave mode)     */
+#define  I2C_SR2_DUALF                       (0x00000080UL)     /*!<Dual Flag (Slave mode)             */
+#define  I2C_SR2_PEC                         (0x0000FF00UL)     /*!<Packet Error Checking Register            */
 
 /*******************  Bit definition for I2C_CCR register  ********************/
-#define  I2C_CCR_CCR                         ((uint32_t)0x00000FFF)     /*!<Clock Control Register in Fast/Standard mode (Master mode) */
-#define  I2C_CCR_DUTY                        ((uint32_t)0x00004000)     /*!<Fast Mode Duty Cycle                                       */
-#define  I2C_CCR_FS                          ((uint32_t)0x00008000)     /*!<I2C Master Mode Selection                                  */
+#define  I2C_CCR_CCR                         (0x00000FFFUL)     /*!<Clock Control Register in Fast/Standard mode (Master mode) */
+#define  I2C_CCR_DUTY                        (0x00004000UL)     /*!<Fast Mode Duty Cycle                                       */
+#define  I2C_CCR_FS                          (0x00008000UL)     /*!<I2C Master Mode Selection                                  */
 
 /******************  Bit definition for I2C_TRISE register  *******************/
-#define  I2C_TRISE_TRISE                     ((uint32_t)0x0000003F)     /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
+#define  I2C_TRISE_TRISE                     (0x0000003FUL)     /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
 
 /******************  Bit definition for I2C_FLTR register  *******************/
-#define  I2C_FLTR_DNF                        ((uint32_t)0x0000000F)     /*!<Digital Noise Filter */
-#define  I2C_FLTR_ANOFF                      ((uint32_t)0x00000010)     /*!<Analog Noise Filter OFF */
+#define  I2C_FLTR_DNF                        (0x0000000FUL)     /*!<Digital Noise Filter */
+#define  I2C_FLTR_ANOFF                      (0x00000010UL)     /*!<Analog Noise Filter OFF */
 
 /******************************************************************************/
 /*                                                                            */
@@ -2159,20 +2155,20 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for IWDG_KR register  ********************/
-#define  IWDG_KR_KEY                         ((uint32_t)0xFFFF)            /*!<Key value (write only, read 0000h)  */
+#define  IWDG_KR_KEY                         (0xFFFFUL)            /*!<Key value (write only, read 0000h)  */
 
 /*******************  Bit definition for IWDG_PR register  ********************/
-#define  IWDG_PR_PR                          ((uint32_t)0x07)               /*!<PR[2:0] (Prescaler divider)         */
-#define  IWDG_PR_PR_0                        ((uint32_t)0x01)               /*!<Bit 0 */
-#define  IWDG_PR_PR_1                        ((uint32_t)0x02)               /*!<Bit 1 */
-#define  IWDG_PR_PR_2                        ((uint32_t)0x04)               /*!<Bit 2 */
+#define  IWDG_PR_PR                          (0x07UL)               /*!<PR[2:0] (Prescaler divider)         */
+#define  IWDG_PR_PR_0                        (0x01UL)               /*!<Bit 0 */
+#define  IWDG_PR_PR_1                        (0x02UL)               /*!<Bit 1 */
+#define  IWDG_PR_PR_2                        (0x04UL)               /*!<Bit 2 */
 
 /*******************  Bit definition for IWDG_RLR register  *******************/
-#define  IWDG_RLR_RL                         ((uint32_t)0x0FFF)            /*!<Watchdog counter reload value        */
+#define  IWDG_RLR_RL                         (0x0FFFUL)            /*!<Watchdog counter reload value        */
 
 /*******************  Bit definition for IWDG_SR register  ********************/
-#define  IWDG_SR_PVU                         ((uint32_t)0x01)               /*!<Watchdog prescaler value update      */
-#define  IWDG_SR_RVU                         ((uint32_t)0x02)               /*!<Watchdog counter reload value update */
+#define  IWDG_SR_PVU                         (0x01UL)               /*!<Watchdog prescaler value update      */
+#define  IWDG_SR_RVU                         (0x02UL)               /*!<Watchdog counter reload value update */
 
 
 /******************************************************************************/
@@ -2181,50 +2177,50 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for PWR_CR register  ********************/
-#define  PWR_CR_LPDS                         ((uint32_t)0x00000001)     /*!< Low-Power Deepsleep                 */
-#define  PWR_CR_PDDS                         ((uint32_t)0x00000002)     /*!< Power Down Deepsleep                */
-#define  PWR_CR_CWUF                         ((uint32_t)0x00000004)     /*!< Clear Wakeup Flag                   */
-#define  PWR_CR_CSBF                         ((uint32_t)0x00000008)     /*!< Clear Standby Flag                  */
-#define  PWR_CR_PVDE                         ((uint32_t)0x00000010)     /*!< Power Voltage Detector Enable       */
+#define  PWR_CR_LPDS                         (0x00000001UL)     /*!< Low-Power Deepsleep                 */
+#define  PWR_CR_PDDS                         (0x00000002UL)     /*!< Power Down Deepsleep                */
+#define  PWR_CR_CWUF                         (0x00000004UL)     /*!< Clear Wakeup Flag                   */
+#define  PWR_CR_CSBF                         (0x00000008UL)     /*!< Clear Standby Flag                  */
+#define  PWR_CR_PVDE                         (0x00000010UL)     /*!< Power Voltage Detector Enable       */
 
-#define  PWR_CR_PLS                          ((uint32_t)0x000000E0)     /*!< PLS[2:0] bits (PVD Level Selection) */
-#define  PWR_CR_PLS_0                        ((uint32_t)0x00000020)     /*!< Bit 0 */
-#define  PWR_CR_PLS_1                        ((uint32_t)0x00000040)     /*!< Bit 1 */
-#define  PWR_CR_PLS_2                        ((uint32_t)0x00000080)     /*!< Bit 2 */
+#define  PWR_CR_PLS                          (0x000000E0UL)     /*!< PLS[2:0] bits (PVD Level Selection) */
+#define  PWR_CR_PLS_0                        (0x00000020UL)     /*!< Bit 0 */
+#define  PWR_CR_PLS_1                        (0x00000040UL)     /*!< Bit 1 */
+#define  PWR_CR_PLS_2                        (0x00000080UL)     /*!< Bit 2 */
 
 /*!< PVD level configuration */
-#define  PWR_CR_PLS_LEV0                     ((uint32_t)0x00000000)     /*!< PVD level 0 */
-#define  PWR_CR_PLS_LEV1                     ((uint32_t)0x00000020)     /*!< PVD level 1 */
-#define  PWR_CR_PLS_LEV2                     ((uint32_t)0x00000040)     /*!< PVD level 2 */
-#define  PWR_CR_PLS_LEV3                     ((uint32_t)0x00000060)     /*!< PVD level 3 */
-#define  PWR_CR_PLS_LEV4                     ((uint32_t)0x00000080)     /*!< PVD level 4 */
-#define  PWR_CR_PLS_LEV5                     ((uint32_t)0x000000A0)     /*!< PVD level 5 */
-#define  PWR_CR_PLS_LEV6                     ((uint32_t)0x000000C0)     /*!< PVD level 6 */
-#define  PWR_CR_PLS_LEV7                     ((uint32_t)0x000000E0)     /*!< PVD level 7 */
+#define  PWR_CR_PLS_LEV0                     (0x00000000UL)     /*!< PVD level 0 */
+#define  PWR_CR_PLS_LEV1                     (0x00000020UL)     /*!< PVD level 1 */
+#define  PWR_CR_PLS_LEV2                     (0x00000040UL)     /*!< PVD level 2 */
+#define  PWR_CR_PLS_LEV3                     (0x00000060UL)     /*!< PVD level 3 */
+#define  PWR_CR_PLS_LEV4                     (0x00000080UL)     /*!< PVD level 4 */
+#define  PWR_CR_PLS_LEV5                     (0x000000A0UL)     /*!< PVD level 5 */
+#define  PWR_CR_PLS_LEV6                     (0x000000C0UL)     /*!< PVD level 6 */
+#define  PWR_CR_PLS_LEV7                     (0x000000E0UL)     /*!< PVD level 7 */
 
-#define  PWR_CR_DBP                          ((uint32_t)0x00000100)     /*!< Disable Backup Domain write protection                     */
-#define  PWR_CR_FPDS                         ((uint32_t)0x00000200)     /*!< Flash power down in Stop mode                              */
-#define  PWR_CR_LPLVDS                       ((uint32_t)0x00000400)     /*!< Low Power Regulator Low Voltage in Deep Sleep mode         */
-#define  PWR_CR_MRLVDS                       ((uint32_t)0x00000800)     /*!< Main Regulator Low Voltage in Deep Sleep mode              */
-#define  PWR_CR_ADCDC1                       ((uint32_t)0x00002000)     /*!< Refer to AN4073 on how to use this bit                     */
+#define  PWR_CR_DBP                          (0x00000100UL)     /*!< Disable Backup Domain write protection                     */
+#define  PWR_CR_FPDS                         (0x00000200UL)     /*!< Flash power down in Stop mode                              */
+#define  PWR_CR_LPLVDS                       (0x00000400UL)     /*!< Low Power Regulator Low Voltage in Deep Sleep mode         */
+#define  PWR_CR_MRLVDS                       (0x00000800UL)     /*!< Main Regulator Low Voltage in Deep Sleep mode              */
+#define  PWR_CR_ADCDC1                       (0x00002000UL)     /*!< Refer to AN4073 on how to use this bit                     */
 
-#define  PWR_CR_VOS                          ((uint32_t)0x0000C000)     /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
-#define  PWR_CR_VOS_0                        ((uint32_t)0x00004000)     /*!< Bit 0 */
-#define  PWR_CR_VOS_1                        ((uint32_t)0x00008000)     /*!< Bit 1 */
+#define  PWR_CR_VOS                          (0x0000C000UL)     /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
+#define  PWR_CR_VOS_0                        (0x00004000UL)     /*!< Bit 0 */
+#define  PWR_CR_VOS_1                        (0x00008000UL)     /*!< Bit 1 */
 
-#define  PWR_CR_FMSSR                        ((uint32_t)0x00100000)     /*!< Flash Memory Sleep System Run        */
-#define  PWR_CR_FISSR                        ((uint32_t)0x00200000)     /*!< Flash Interface Stop while System Run */
+#define  PWR_CR_FMSSR                        (0x00100000UL)     /*!< Flash Memory Sleep System Run        */
+#define  PWR_CR_FISSR                        (0x00200000UL)     /*!< Flash Interface Stop while System Run */
 /* Legacy define */
 #define  PWR_CR_PMODE                        PWR_CR_VOS
 
 /*******************  Bit definition for PWR_CSR register  ********************/
-#define  PWR_CSR_WUF                         ((uint32_t)0x00000001)     /*!< Wakeup Flag                                      */
-#define  PWR_CSR_SBF                         ((uint32_t)0x00000002)     /*!< Standby Flag                                     */
-#define  PWR_CSR_PVDO                        ((uint32_t)0x00000004)     /*!< PVD Output                                       */
-#define  PWR_CSR_BRR                         ((uint32_t)0x00000008)     /*!< Backup regulator ready                           */
-#define  PWR_CSR_EWUP                        ((uint32_t)0x00000100)     /*!< Enable WKUP pin                                  */
-#define  PWR_CSR_BRE                         ((uint32_t)0x00000200)     /*!< Backup regulator enable                          */
-#define  PWR_CSR_VOSRDY                      ((uint32_t)0x00004000)     /*!< Regulator voltage scaling output selection ready */
+#define  PWR_CSR_WUF                         (0x00000001UL)     /*!< Wakeup Flag                                      */
+#define  PWR_CSR_SBF                         (0x00000002UL)     /*!< Standby Flag                                     */
+#define  PWR_CSR_PVDO                        (0x00000004UL)     /*!< PVD Output                                       */
+#define  PWR_CSR_BRR                         (0x00000008UL)     /*!< Backup regulator ready                           */
+#define  PWR_CSR_EWUP                        (0x00000100UL)     /*!< Enable WKUP pin                                  */
+#define  PWR_CSR_BRE                         (0x00000200UL)     /*!< Backup regulator enable                          */
+#define  PWR_CSR_VOSRDY                      (0x00004000UL)     /*!< Regulator voltage scaling output selection ready */
 
 /* Legacy define */
 #define  PWR_CSR_REGRDY                      PWR_CSR_VOSRDY
@@ -2235,761 +2231,761 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for RCC_CR register  ********************/
-#define  RCC_CR_HSION                        ((uint32_t)0x00000001)
-#define  RCC_CR_HSIRDY                       ((uint32_t)0x00000002)
+#define  RCC_CR_HSION                        (0x00000001UL)
+#define  RCC_CR_HSIRDY                       (0x00000002UL)
 
-#define  RCC_CR_HSITRIM                      ((uint32_t)0x000000F8)
-#define  RCC_CR_HSITRIM_0                    ((uint32_t)0x00000008)/*!<Bit 0 */
-#define  RCC_CR_HSITRIM_1                    ((uint32_t)0x00000010)/*!<Bit 1 */
-#define  RCC_CR_HSITRIM_2                    ((uint32_t)0x00000020)/*!<Bit 2 */
-#define  RCC_CR_HSITRIM_3                    ((uint32_t)0x00000040)/*!<Bit 3 */
-#define  RCC_CR_HSITRIM_4                    ((uint32_t)0x00000080)/*!<Bit 4 */
+#define  RCC_CR_HSITRIM                      (0x000000F8UL)
+#define  RCC_CR_HSITRIM_0                    (0x00000008UL)/*!<Bit 0 */
+#define  RCC_CR_HSITRIM_1                    (0x00000010UL)/*!<Bit 1 */
+#define  RCC_CR_HSITRIM_2                    (0x00000020UL)/*!<Bit 2 */
+#define  RCC_CR_HSITRIM_3                    (0x00000040UL)/*!<Bit 3 */
+#define  RCC_CR_HSITRIM_4                    (0x00000080UL)/*!<Bit 4 */
 
-#define  RCC_CR_HSICAL                       ((uint32_t)0x0000FF00)
-#define  RCC_CR_HSICAL_0                     ((uint32_t)0x00000100)/*!<Bit 0 */
-#define  RCC_CR_HSICAL_1                     ((uint32_t)0x00000200)/*!<Bit 1 */
-#define  RCC_CR_HSICAL_2                     ((uint32_t)0x00000400)/*!<Bit 2 */
-#define  RCC_CR_HSICAL_3                     ((uint32_t)0x00000800)/*!<Bit 3 */
-#define  RCC_CR_HSICAL_4                     ((uint32_t)0x00001000)/*!<Bit 4 */
-#define  RCC_CR_HSICAL_5                     ((uint32_t)0x00002000)/*!<Bit 5 */
-#define  RCC_CR_HSICAL_6                     ((uint32_t)0x00004000)/*!<Bit 6 */
-#define  RCC_CR_HSICAL_7                     ((uint32_t)0x00008000)/*!<Bit 7 */
+#define  RCC_CR_HSICAL                       (0x0000FF00UL)
+#define  RCC_CR_HSICAL_0                     (0x00000100UL)/*!<Bit 0 */
+#define  RCC_CR_HSICAL_1                     (0x00000200UL)/*!<Bit 1 */
+#define  RCC_CR_HSICAL_2                     (0x00000400UL)/*!<Bit 2 */
+#define  RCC_CR_HSICAL_3                     (0x00000800UL)/*!<Bit 3 */
+#define  RCC_CR_HSICAL_4                     (0x00001000UL)/*!<Bit 4 */
+#define  RCC_CR_HSICAL_5                     (0x00002000UL)/*!<Bit 5 */
+#define  RCC_CR_HSICAL_6                     (0x00004000UL)/*!<Bit 6 */
+#define  RCC_CR_HSICAL_7                     (0x00008000UL)/*!<Bit 7 */
 
-#define  RCC_CR_HSEON                        ((uint32_t)0x00010000)
-#define  RCC_CR_HSERDY                       ((uint32_t)0x00020000)
-#define  RCC_CR_HSEBYP                       ((uint32_t)0x00040000)
-#define  RCC_CR_CSSON                        ((uint32_t)0x00080000)
-#define  RCC_CR_PLLON                        ((uint32_t)0x01000000)
-#define  RCC_CR_PLLRDY                       ((uint32_t)0x02000000)
-#define  RCC_CR_PLLI2SON                     ((uint32_t)0x04000000)
-#define  RCC_CR_PLLI2SRDY                    ((uint32_t)0x08000000)
+#define  RCC_CR_HSEON                        (0x00010000UL)
+#define  RCC_CR_HSERDY                       (0x00020000UL)
+#define  RCC_CR_HSEBYP                       (0x00040000UL)
+#define  RCC_CR_CSSON                        (0x00080000UL)
+#define  RCC_CR_PLLON                        (0x01000000UL)
+#define  RCC_CR_PLLRDY                       (0x02000000UL)
+#define  RCC_CR_PLLI2SON                     (0x04000000UL)
+#define  RCC_CR_PLLI2SRDY                    (0x08000000UL)
 
 /********************  Bit definition for RCC_PLLCFGR register  ***************/
-#define  RCC_PLLCFGR_PLLM                    ((uint32_t)0x0000003F)
-#define  RCC_PLLCFGR_PLLM_0                  ((uint32_t)0x00000001)
-#define  RCC_PLLCFGR_PLLM_1                  ((uint32_t)0x00000002)
-#define  RCC_PLLCFGR_PLLM_2                  ((uint32_t)0x00000004)
-#define  RCC_PLLCFGR_PLLM_3                  ((uint32_t)0x00000008)
-#define  RCC_PLLCFGR_PLLM_4                  ((uint32_t)0x00000010)
-#define  RCC_PLLCFGR_PLLM_5                  ((uint32_t)0x00000020)
+#define  RCC_PLLCFGR_PLLM                    (0x0000003FUL)
+#define  RCC_PLLCFGR_PLLM_0                  (0x00000001UL)
+#define  RCC_PLLCFGR_PLLM_1                  (0x00000002UL)
+#define  RCC_PLLCFGR_PLLM_2                  (0x00000004UL)
+#define  RCC_PLLCFGR_PLLM_3                  (0x00000008UL)
+#define  RCC_PLLCFGR_PLLM_4                  (0x00000010UL)
+#define  RCC_PLLCFGR_PLLM_5                  (0x00000020UL)
 
-#define  RCC_PLLCFGR_PLLN                     ((uint32_t)0x00007FC0)
-#define  RCC_PLLCFGR_PLLN_0                   ((uint32_t)0x00000040)
-#define  RCC_PLLCFGR_PLLN_1                   ((uint32_t)0x00000080)
-#define  RCC_PLLCFGR_PLLN_2                   ((uint32_t)0x00000100)
-#define  RCC_PLLCFGR_PLLN_3                   ((uint32_t)0x00000200)
-#define  RCC_PLLCFGR_PLLN_4                   ((uint32_t)0x00000400)
-#define  RCC_PLLCFGR_PLLN_5                   ((uint32_t)0x00000800)
-#define  RCC_PLLCFGR_PLLN_6                   ((uint32_t)0x00001000)
-#define  RCC_PLLCFGR_PLLN_7                   ((uint32_t)0x00002000)
-#define  RCC_PLLCFGR_PLLN_8                   ((uint32_t)0x00004000)
+#define  RCC_PLLCFGR_PLLN                     (0x00007FC0UL)
+#define  RCC_PLLCFGR_PLLN_0                   (0x00000040UL)
+#define  RCC_PLLCFGR_PLLN_1                   (0x00000080UL)
+#define  RCC_PLLCFGR_PLLN_2                   (0x00000100UL)
+#define  RCC_PLLCFGR_PLLN_3                   (0x00000200UL)
+#define  RCC_PLLCFGR_PLLN_4                   (0x00000400UL)
+#define  RCC_PLLCFGR_PLLN_5                   (0x00000800UL)
+#define  RCC_PLLCFGR_PLLN_6                   (0x00001000UL)
+#define  RCC_PLLCFGR_PLLN_7                   (0x00002000UL)
+#define  RCC_PLLCFGR_PLLN_8                   (0x00004000UL)
 
-#define  RCC_PLLCFGR_PLLP                    ((uint32_t)0x00030000)
-#define  RCC_PLLCFGR_PLLP_0                  ((uint32_t)0x00010000)
-#define  RCC_PLLCFGR_PLLP_1                  ((uint32_t)0x00020000)
+#define  RCC_PLLCFGR_PLLP                    (0x00030000UL)
+#define  RCC_PLLCFGR_PLLP_0                  (0x00010000UL)
+#define  RCC_PLLCFGR_PLLP_1                  (0x00020000UL)
 
-#define  RCC_PLLCFGR_PLLSRC                  ((uint32_t)0x00400000)
-#define  RCC_PLLCFGR_PLLSRC_HSE              ((uint32_t)0x00400000)
-#define  RCC_PLLCFGR_PLLSRC_HSI              ((uint32_t)0x00000000)
+#define  RCC_PLLCFGR_PLLSRC                  (0x00400000UL)
+#define  RCC_PLLCFGR_PLLSRC_HSE              (0x00400000UL)
+#define  RCC_PLLCFGR_PLLSRC_HSI              (0x00000000UL)
 
-#define  RCC_PLLCFGR_PLLQ                    ((uint32_t)0x0F000000)
-#define  RCC_PLLCFGR_PLLQ_0                  ((uint32_t)0x01000000)
-#define  RCC_PLLCFGR_PLLQ_1                  ((uint32_t)0x02000000)
-#define  RCC_PLLCFGR_PLLQ_2                  ((uint32_t)0x04000000)
-#define  RCC_PLLCFGR_PLLQ_3                  ((uint32_t)0x08000000)
+#define  RCC_PLLCFGR_PLLQ                    (0x0F000000UL)
+#define  RCC_PLLCFGR_PLLQ_0                  (0x01000000UL)
+#define  RCC_PLLCFGR_PLLQ_1                  (0x02000000UL)
+#define  RCC_PLLCFGR_PLLQ_2                  (0x04000000UL)
+#define  RCC_PLLCFGR_PLLQ_3                  (0x08000000UL)
 
 /********************  Bit definition for RCC_CFGR register  ******************/
 /*!< SW configuration */
-#define  RCC_CFGR_SW                         ((uint32_t)0x00000003)        /*!< SW[1:0] bits (System clock Switch) */
-#define  RCC_CFGR_SW_0                       ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  RCC_CFGR_SW_1                       ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  RCC_CFGR_SW                         (0x00000003UL)        /*!< SW[1:0] bits (System clock Switch) */
+#define  RCC_CFGR_SW_0                       (0x00000001UL)        /*!< Bit 0 */
+#define  RCC_CFGR_SW_1                       (0x00000002UL)        /*!< Bit 1 */
 
-#define  RCC_CFGR_SW_HSI                     ((uint32_t)0x00000000)        /*!< HSI selected as system clock */
-#define  RCC_CFGR_SW_HSE                     ((uint32_t)0x00000001)        /*!< HSE selected as system clock */
-#define  RCC_CFGR_SW_PLL                     ((uint32_t)0x00000002)        /*!< PLL selected as system clock */
+#define  RCC_CFGR_SW_HSI                     (0x00000000UL)        /*!< HSI selected as system clock */
+#define  RCC_CFGR_SW_HSE                     (0x00000001UL)        /*!< HSE selected as system clock */
+#define  RCC_CFGR_SW_PLL                     (0x00000002UL)        /*!< PLL selected as system clock */
 
 /*!< SWS configuration */
-#define  RCC_CFGR_SWS                        ((uint32_t)0x0000000C)        /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define  RCC_CFGR_SWS_0                      ((uint32_t)0x00000004)        /*!< Bit 0 */
-#define  RCC_CFGR_SWS_1                      ((uint32_t)0x00000008)        /*!< Bit 1 */
+#define  RCC_CFGR_SWS                        (0x0000000CUL)        /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define  RCC_CFGR_SWS_0                      (0x00000004UL)        /*!< Bit 0 */
+#define  RCC_CFGR_SWS_1                      (0x00000008UL)        /*!< Bit 1 */
 
-#define  RCC_CFGR_SWS_HSI                    ((uint32_t)0x00000000)        /*!< HSI oscillator used as system clock */
-#define  RCC_CFGR_SWS_HSE                    ((uint32_t)0x00000004)        /*!< HSE oscillator used as system clock */
-#define  RCC_CFGR_SWS_PLL                    ((uint32_t)0x00000008)        /*!< PLL used as system clock */
+#define  RCC_CFGR_SWS_HSI                    (0x00000000UL)        /*!< HSI oscillator used as system clock */
+#define  RCC_CFGR_SWS_HSE                    (0x00000004UL)        /*!< HSE oscillator used as system clock */
+#define  RCC_CFGR_SWS_PLL                    (0x00000008UL)        /*!< PLL used as system clock */
 
 /*!< HPRE configuration */
-#define  RCC_CFGR_HPRE                       ((uint32_t)0x000000F0)        /*!< HPRE[3:0] bits (AHB prescaler) */
-#define  RCC_CFGR_HPRE_0                     ((uint32_t)0x00000010)        /*!< Bit 0 */
-#define  RCC_CFGR_HPRE_1                     ((uint32_t)0x00000020)        /*!< Bit 1 */
-#define  RCC_CFGR_HPRE_2                     ((uint32_t)0x00000040)        /*!< Bit 2 */
-#define  RCC_CFGR_HPRE_3                     ((uint32_t)0x00000080)        /*!< Bit 3 */
+#define  RCC_CFGR_HPRE                       (0x000000F0UL)        /*!< HPRE[3:0] bits (AHB prescaler) */
+#define  RCC_CFGR_HPRE_0                     (0x00000010UL)        /*!< Bit 0 */
+#define  RCC_CFGR_HPRE_1                     (0x00000020UL)        /*!< Bit 1 */
+#define  RCC_CFGR_HPRE_2                     (0x00000040UL)        /*!< Bit 2 */
+#define  RCC_CFGR_HPRE_3                     (0x00000080UL)        /*!< Bit 3 */
 
-#define  RCC_CFGR_HPRE_DIV1                  ((uint32_t)0x00000000)        /*!< SYSCLK not divided */
-#define  RCC_CFGR_HPRE_DIV2                  ((uint32_t)0x00000080)        /*!< SYSCLK divided by 2 */
-#define  RCC_CFGR_HPRE_DIV4                  ((uint32_t)0x00000090)        /*!< SYSCLK divided by 4 */
-#define  RCC_CFGR_HPRE_DIV8                  ((uint32_t)0x000000A0)        /*!< SYSCLK divided by 8 */
-#define  RCC_CFGR_HPRE_DIV16                 ((uint32_t)0x000000B0)        /*!< SYSCLK divided by 16 */
-#define  RCC_CFGR_HPRE_DIV64                 ((uint32_t)0x000000C0)        /*!< SYSCLK divided by 64 */
-#define  RCC_CFGR_HPRE_DIV128                ((uint32_t)0x000000D0)        /*!< SYSCLK divided by 128 */
-#define  RCC_CFGR_HPRE_DIV256                ((uint32_t)0x000000E0)        /*!< SYSCLK divided by 256 */
-#define  RCC_CFGR_HPRE_DIV512                ((uint32_t)0x000000F0)        /*!< SYSCLK divided by 512 */
+#define  RCC_CFGR_HPRE_DIV1                  (0x00000000UL)        /*!< SYSCLK not divided */
+#define  RCC_CFGR_HPRE_DIV2                  (0x00000080UL)        /*!< SYSCLK divided by 2 */
+#define  RCC_CFGR_HPRE_DIV4                  (0x00000090UL)        /*!< SYSCLK divided by 4 */
+#define  RCC_CFGR_HPRE_DIV8                  (0x000000A0UL)        /*!< SYSCLK divided by 8 */
+#define  RCC_CFGR_HPRE_DIV16                 (0x000000B0UL)        /*!< SYSCLK divided by 16 */
+#define  RCC_CFGR_HPRE_DIV64                 (0x000000C0UL)        /*!< SYSCLK divided by 64 */
+#define  RCC_CFGR_HPRE_DIV128                (0x000000D0UL)        /*!< SYSCLK divided by 128 */
+#define  RCC_CFGR_HPRE_DIV256                (0x000000E0UL)        /*!< SYSCLK divided by 256 */
+#define  RCC_CFGR_HPRE_DIV512                (0x000000F0UL)        /*!< SYSCLK divided by 512 */
 
 /*!< PPRE1 configuration */
-#define  RCC_CFGR_PPRE1                      ((uint32_t)0x00001C00)        /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define  RCC_CFGR_PPRE1_0                    ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE1_1                    ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE1_2                    ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  RCC_CFGR_PPRE1                      (0x00001C00UL)        /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define  RCC_CFGR_PPRE1_0                    (0x00000400UL)        /*!< Bit 0 */
+#define  RCC_CFGR_PPRE1_1                    (0x00000800UL)        /*!< Bit 1 */
+#define  RCC_CFGR_PPRE1_2                    (0x00001000UL)        /*!< Bit 2 */
 
-#define  RCC_CFGR_PPRE1_DIV1                 ((uint32_t)0x00000000)        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE1_DIV2                 ((uint32_t)0x00001000)        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE1_DIV4                 ((uint32_t)0x00001400)        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE1_DIV8                 ((uint32_t)0x00001800)        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE1_DIV16                ((uint32_t)0x00001C00)        /*!< HCLK divided by 16 */
+#define  RCC_CFGR_PPRE1_DIV1                 (0x00000000UL)        /*!< HCLK not divided */
+#define  RCC_CFGR_PPRE1_DIV2                 (0x00001000UL)        /*!< HCLK divided by 2 */
+#define  RCC_CFGR_PPRE1_DIV4                 (0x00001400UL)        /*!< HCLK divided by 4 */
+#define  RCC_CFGR_PPRE1_DIV8                 (0x00001800UL)        /*!< HCLK divided by 8 */
+#define  RCC_CFGR_PPRE1_DIV16                (0x00001C00UL)        /*!< HCLK divided by 16 */
 
 /*!< PPRE2 configuration */
-#define  RCC_CFGR_PPRE2                      ((uint32_t)0x0000E000)        /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define  RCC_CFGR_PPRE2_0                    ((uint32_t)0x00002000)        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE2_1                    ((uint32_t)0x00004000)        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE2_2                    ((uint32_t)0x00008000)        /*!< Bit 2 */
+#define  RCC_CFGR_PPRE2                      (0x0000E000UL)        /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define  RCC_CFGR_PPRE2_0                    (0x00002000UL)        /*!< Bit 0 */
+#define  RCC_CFGR_PPRE2_1                    (0x00004000UL)        /*!< Bit 1 */
+#define  RCC_CFGR_PPRE2_2                    (0x00008000UL)        /*!< Bit 2 */
 
-#define  RCC_CFGR_PPRE2_DIV1                 ((uint32_t)0x00000000)        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE2_DIV2                 ((uint32_t)0x00008000)        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE2_DIV4                 ((uint32_t)0x0000A000)        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE2_DIV8                 ((uint32_t)0x0000C000)        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE2_DIV16                ((uint32_t)0x0000E000)        /*!< HCLK divided by 16 */
+#define  RCC_CFGR_PPRE2_DIV1                 (0x00000000UL)        /*!< HCLK not divided */
+#define  RCC_CFGR_PPRE2_DIV2                 (0x00008000UL)        /*!< HCLK divided by 2 */
+#define  RCC_CFGR_PPRE2_DIV4                 (0x0000A000UL)        /*!< HCLK divided by 4 */
+#define  RCC_CFGR_PPRE2_DIV8                 (0x0000C000UL)        /*!< HCLK divided by 8 */
+#define  RCC_CFGR_PPRE2_DIV16                (0x0000E000UL)        /*!< HCLK divided by 16 */
 
 /*!< RTCPRE configuration */
-#define  RCC_CFGR_RTCPRE                     ((uint32_t)0x001F0000)
-#define  RCC_CFGR_RTCPRE_0                   ((uint32_t)0x00010000)
-#define  RCC_CFGR_RTCPRE_1                   ((uint32_t)0x00020000)
-#define  RCC_CFGR_RTCPRE_2                   ((uint32_t)0x00040000)
-#define  RCC_CFGR_RTCPRE_3                   ((uint32_t)0x00080000)
-#define  RCC_CFGR_RTCPRE_4                   ((uint32_t)0x00100000)
+#define  RCC_CFGR_RTCPRE                     (0x001F0000UL)
+#define  RCC_CFGR_RTCPRE_0                   (0x00010000UL)
+#define  RCC_CFGR_RTCPRE_1                   (0x00020000UL)
+#define  RCC_CFGR_RTCPRE_2                   (0x00040000UL)
+#define  RCC_CFGR_RTCPRE_3                   (0x00080000UL)
+#define  RCC_CFGR_RTCPRE_4                   (0x00100000UL)
 
 /*!< MCO1 configuration */
-#define  RCC_CFGR_MCO1                       ((uint32_t)0x00600000)
-#define  RCC_CFGR_MCO1_0                     ((uint32_t)0x00200000)
-#define  RCC_CFGR_MCO1_1                     ((uint32_t)0x00400000)
+#define  RCC_CFGR_MCO1                       (0x00600000UL)
+#define  RCC_CFGR_MCO1_0                     (0x00200000UL)
+#define  RCC_CFGR_MCO1_1                     (0x00400000UL)
 
-#define  RCC_CFGR_I2SSRC                     ((uint32_t)0x00800000)
+#define  RCC_CFGR_I2SSRC                     (0x00800000UL)
 
-#define  RCC_CFGR_MCO1PRE                    ((uint32_t)0x07000000)
-#define  RCC_CFGR_MCO1PRE_0                  ((uint32_t)0x01000000)
-#define  RCC_CFGR_MCO1PRE_1                  ((uint32_t)0x02000000)
-#define  RCC_CFGR_MCO1PRE_2                  ((uint32_t)0x04000000)
+#define  RCC_CFGR_MCO1PRE                    (0x07000000UL)
+#define  RCC_CFGR_MCO1PRE_0                  (0x01000000UL)
+#define  RCC_CFGR_MCO1PRE_1                  (0x02000000UL)
+#define  RCC_CFGR_MCO1PRE_2                  (0x04000000UL)
 
-#define  RCC_CFGR_MCO2PRE                    ((uint32_t)0x38000000)
-#define  RCC_CFGR_MCO2PRE_0                  ((uint32_t)0x08000000)
-#define  RCC_CFGR_MCO2PRE_1                  ((uint32_t)0x10000000)
-#define  RCC_CFGR_MCO2PRE_2                  ((uint32_t)0x20000000)
+#define  RCC_CFGR_MCO2PRE                    (0x38000000UL)
+#define  RCC_CFGR_MCO2PRE_0                  (0x08000000UL)
+#define  RCC_CFGR_MCO2PRE_1                  (0x10000000UL)
+#define  RCC_CFGR_MCO2PRE_2                  (0x20000000UL)
 
-#define  RCC_CFGR_MCO2                       ((uint32_t)0xC0000000)
-#define  RCC_CFGR_MCO2_0                     ((uint32_t)0x40000000)
-#define  RCC_CFGR_MCO2_1                     ((uint32_t)0x80000000)
+#define  RCC_CFGR_MCO2                       (0xC0000000UL)
+#define  RCC_CFGR_MCO2_0                     (0x40000000UL)
+#define  RCC_CFGR_MCO2_1                     (0x80000000UL)
 
 /********************  Bit definition for RCC_CIR register  *******************/
-#define  RCC_CIR_LSIRDYF                     ((uint32_t)0x00000001)
-#define  RCC_CIR_LSERDYF                     ((uint32_t)0x00000002)
-#define  RCC_CIR_HSIRDYF                     ((uint32_t)0x00000004)
-#define  RCC_CIR_HSERDYF                     ((uint32_t)0x00000008)
-#define  RCC_CIR_PLLRDYF                     ((uint32_t)0x00000010)
-#define  RCC_CIR_PLLI2SRDYF                  ((uint32_t)0x00000020)
+#define  RCC_CIR_LSIRDYF                     (0x00000001UL)
+#define  RCC_CIR_LSERDYF                     (0x00000002UL)
+#define  RCC_CIR_HSIRDYF                     (0x00000004UL)
+#define  RCC_CIR_HSERDYF                     (0x00000008UL)
+#define  RCC_CIR_PLLRDYF                     (0x00000010UL)
+#define  RCC_CIR_PLLI2SRDYF                  (0x00000020UL)
 
-#define  RCC_CIR_CSSF                        ((uint32_t)0x00000080)
-#define  RCC_CIR_LSIRDYIE                    ((uint32_t)0x00000100)
-#define  RCC_CIR_LSERDYIE                    ((uint32_t)0x00000200)
-#define  RCC_CIR_HSIRDYIE                    ((uint32_t)0x00000400)
-#define  RCC_CIR_HSERDYIE                    ((uint32_t)0x00000800)
-#define  RCC_CIR_PLLRDYIE                    ((uint32_t)0x00001000)
-#define  RCC_CIR_PLLI2SRDYIE                 ((uint32_t)0x00002000)
+#define  RCC_CIR_CSSF                        (0x00000080UL)
+#define  RCC_CIR_LSIRDYIE                    (0x00000100UL)
+#define  RCC_CIR_LSERDYIE                    (0x00000200UL)
+#define  RCC_CIR_HSIRDYIE                    (0x00000400UL)
+#define  RCC_CIR_HSERDYIE                    (0x00000800UL)
+#define  RCC_CIR_PLLRDYIE                    (0x00001000UL)
+#define  RCC_CIR_PLLI2SRDYIE                 (0x00002000UL)
 
-#define  RCC_CIR_LSIRDYC                     ((uint32_t)0x00010000)
-#define  RCC_CIR_LSERDYC                     ((uint32_t)0x00020000)
-#define  RCC_CIR_HSIRDYC                     ((uint32_t)0x00040000)
-#define  RCC_CIR_HSERDYC                     ((uint32_t)0x00080000)
-#define  RCC_CIR_PLLRDYC                     ((uint32_t)0x00100000)
-#define  RCC_CIR_PLLI2SRDYC                  ((uint32_t)0x00200000)
+#define  RCC_CIR_LSIRDYC                     (0x00010000UL)
+#define  RCC_CIR_LSERDYC                     (0x00020000UL)
+#define  RCC_CIR_HSIRDYC                     (0x00040000UL)
+#define  RCC_CIR_HSERDYC                     (0x00080000UL)
+#define  RCC_CIR_PLLRDYC                     (0x00100000UL)
+#define  RCC_CIR_PLLI2SRDYC                  (0x00200000UL)
 
-#define  RCC_CIR_CSSC                        ((uint32_t)0x00800000)
+#define  RCC_CIR_CSSC                        (0x00800000UL)
 
 /********************  Bit definition for RCC_AHB1RSTR register  **************/
-#define  RCC_AHB1RSTR_GPIOARST               ((uint32_t)0x00000001)
-#define  RCC_AHB1RSTR_GPIOBRST               ((uint32_t)0x00000002)
-#define  RCC_AHB1RSTR_GPIOCRST               ((uint32_t)0x00000004)
-#define  RCC_AHB1RSTR_GPIODRST               ((uint32_t)0x00000008)
-#define  RCC_AHB1RSTR_GPIOERST               ((uint32_t)0x00000010)
-#define  RCC_AHB1RSTR_GPIOHRST               ((uint32_t)0x00000080)
-#define  RCC_AHB1RSTR_CRCRST                 ((uint32_t)0x00001000)
-#define  RCC_AHB1RSTR_DMA1RST                ((uint32_t)0x00200000)
-#define  RCC_AHB1RSTR_DMA2RST                ((uint32_t)0x00400000)
+#define  RCC_AHB1RSTR_GPIOARST               (0x00000001UL)
+#define  RCC_AHB1RSTR_GPIOBRST               (0x00000002UL)
+#define  RCC_AHB1RSTR_GPIOCRST               (0x00000004UL)
+#define  RCC_AHB1RSTR_GPIODRST               (0x00000008UL)
+#define  RCC_AHB1RSTR_GPIOERST               (0x00000010UL)
+#define  RCC_AHB1RSTR_GPIOHRST               (0x00000080UL)
+#define  RCC_AHB1RSTR_CRCRST                 (0x00001000UL)
+#define  RCC_AHB1RSTR_DMA1RST                (0x00200000UL)
+#define  RCC_AHB1RSTR_DMA2RST                (0x00400000UL)
 
 /********************  Bit definition for RCC_AHB2RSTR register  **************/
-#define  RCC_AHB2RSTR_OTGFSRST               ((uint32_t)0x00000080)
+#define  RCC_AHB2RSTR_OTGFSRST               (0x00000080UL)
 
 /********************  Bit definition for RCC_AHB3RSTR register  **************/
 
 /********************  Bit definition for RCC_APB1RSTR register  **************/
-#define  RCC_APB1RSTR_TIM2RST                ((uint32_t)0x00000001)
-#define  RCC_APB1RSTR_TIM3RST                ((uint32_t)0x00000002)
-#define  RCC_APB1RSTR_TIM4RST                ((uint32_t)0x00000004)
-#define  RCC_APB1RSTR_TIM5RST                ((uint32_t)0x00000008)
-#define  RCC_APB1RSTR_WWDGRST                ((uint32_t)0x00000800)
-#define  RCC_APB1RSTR_SPI2RST                ((uint32_t)0x00004000)
-#define  RCC_APB1RSTR_SPI3RST                ((uint32_t)0x00008000)
-#define  RCC_APB1RSTR_USART2RST              ((uint32_t)0x00020000)
-#define  RCC_APB1RSTR_I2C1RST                ((uint32_t)0x00200000)
-#define  RCC_APB1RSTR_I2C2RST                ((uint32_t)0x00400000)
-#define  RCC_APB1RSTR_I2C3RST                ((uint32_t)0x00800000)
-#define  RCC_APB1RSTR_PWRRST                 ((uint32_t)0x10000000)
+#define  RCC_APB1RSTR_TIM2RST                (0x00000001UL)
+#define  RCC_APB1RSTR_TIM3RST                (0x00000002UL)
+#define  RCC_APB1RSTR_TIM4RST                (0x00000004UL)
+#define  RCC_APB1RSTR_TIM5RST                (0x00000008UL)
+#define  RCC_APB1RSTR_WWDGRST                (0x00000800UL)
+#define  RCC_APB1RSTR_SPI2RST                (0x00004000UL)
+#define  RCC_APB1RSTR_SPI3RST                (0x00008000UL)
+#define  RCC_APB1RSTR_USART2RST              (0x00020000UL)
+#define  RCC_APB1RSTR_I2C1RST                (0x00200000UL)
+#define  RCC_APB1RSTR_I2C2RST                (0x00400000UL)
+#define  RCC_APB1RSTR_I2C3RST                (0x00800000UL)
+#define  RCC_APB1RSTR_PWRRST                 (0x10000000UL)
 
 /********************  Bit definition for RCC_APB2RSTR register  **************/
-#define  RCC_APB2RSTR_TIM1RST                ((uint32_t)0x00000001)
-#define  RCC_APB2RSTR_USART1RST              ((uint32_t)0x00000010)
-#define  RCC_APB2RSTR_USART6RST              ((uint32_t)0x00000020)
-#define  RCC_APB2RSTR_ADCRST                 ((uint32_t)0x00000100)
-#define  RCC_APB2RSTR_SDIORST                ((uint32_t)0x00000800)
-#define  RCC_APB2RSTR_SPI1RST                ((uint32_t)0x00001000)
-#define  RCC_APB2RSTR_SPI4RST                ((uint32_t)0x00002000)
-#define  RCC_APB2RSTR_SYSCFGRST              ((uint32_t)0x00004000)
-#define  RCC_APB2RSTR_TIM9RST                ((uint32_t)0x00010000)
-#define  RCC_APB2RSTR_TIM10RST               ((uint32_t)0x00020000)
-#define  RCC_APB2RSTR_TIM11RST               ((uint32_t)0x00040000)
-#define  RCC_APB2RSTR_SPI5RST                ((uint32_t)0x00100000)
+#define  RCC_APB2RSTR_TIM1RST                (0x00000001UL)
+#define  RCC_APB2RSTR_USART1RST              (0x00000010UL)
+#define  RCC_APB2RSTR_USART6RST              (0x00000020UL)
+#define  RCC_APB2RSTR_ADCRST                 (0x00000100UL)
+#define  RCC_APB2RSTR_SDIORST                (0x00000800UL)
+#define  RCC_APB2RSTR_SPI1RST                (0x00001000UL)
+#define  RCC_APB2RSTR_SPI4RST                (0x00002000UL)
+#define  RCC_APB2RSTR_SYSCFGRST              (0x00004000UL)
+#define  RCC_APB2RSTR_TIM9RST                (0x00010000UL)
+#define  RCC_APB2RSTR_TIM10RST               (0x00020000UL)
+#define  RCC_APB2RSTR_TIM11RST               (0x00040000UL)
+#define  RCC_APB2RSTR_SPI5RST                (0x00100000UL)
 
 /* Old SPI1RST bit definition, maintained for legacy purpose */
 #define  RCC_APB2RSTR_SPI1                   RCC_APB2RSTR_SPI1RST
 
 /********************  Bit definition for RCC_AHB1ENR register  ***************/
-#define  RCC_AHB1ENR_GPIOAEN                 ((uint32_t)0x00000001)
-#define  RCC_AHB1ENR_GPIOBEN                 ((uint32_t)0x00000002)
-#define  RCC_AHB1ENR_GPIOCEN                 ((uint32_t)0x00000004)
-#define  RCC_AHB1ENR_GPIODEN                 ((uint32_t)0x00000008)
-#define  RCC_AHB1ENR_GPIOEEN                 ((uint32_t)0x00000010)
-#define  RCC_AHB1ENR_GPIOHEN                 ((uint32_t)0x00000080)
-#define  RCC_AHB1ENR_CRCEN                   ((uint32_t)0x00001000)
-#define  RCC_AHB1ENR_BKPSRAMEN               ((uint32_t)0x00040000)
-#define  RCC_AHB1ENR_CCMDATARAMEN            ((uint32_t)0x00100000)
-#define  RCC_AHB1ENR_DMA1EN                  ((uint32_t)0x00200000)
-#define  RCC_AHB1ENR_DMA2EN                  ((uint32_t)0x00400000)
+#define  RCC_AHB1ENR_GPIOAEN                 (0x00000001UL)
+#define  RCC_AHB1ENR_GPIOBEN                 (0x00000002UL)
+#define  RCC_AHB1ENR_GPIOCEN                 (0x00000004UL)
+#define  RCC_AHB1ENR_GPIODEN                 (0x00000008UL)
+#define  RCC_AHB1ENR_GPIOEEN                 (0x00000010UL)
+#define  RCC_AHB1ENR_GPIOHEN                 (0x00000080UL)
+#define  RCC_AHB1ENR_CRCEN                   (0x00001000UL)
+#define  RCC_AHB1ENR_BKPSRAMEN               (0x00040000UL)
+#define  RCC_AHB1ENR_CCMDATARAMEN            (0x00100000UL)
+#define  RCC_AHB1ENR_DMA1EN                  (0x00200000UL)
+#define  RCC_AHB1ENR_DMA2EN                  (0x00400000UL)
 
 /********************  Bit definition for RCC_AHB2ENR register  ***************/
-#define  RCC_AHB2ENR_OTGFSEN                 ((uint32_t)0x00000080)
+#define  RCC_AHB2ENR_OTGFSEN                 (0x00000080UL)
 
 /********************  Bit definition for RCC_AHB3ENR register  ***************/
 
 /********************  Bit definition for RCC_APB1ENR register  ***************/
-#define  RCC_APB1ENR_TIM2EN                  ((uint32_t)0x00000001)
-#define  RCC_APB1ENR_TIM3EN                  ((uint32_t)0x00000002)
-#define  RCC_APB1ENR_TIM4EN                  ((uint32_t)0x00000004)
-#define  RCC_APB1ENR_TIM5EN                  ((uint32_t)0x00000008)
-#define  RCC_APB1ENR_WWDGEN                  ((uint32_t)0x00000800)
-#define  RCC_APB1ENR_SPI2EN                  ((uint32_t)0x00004000)
-#define  RCC_APB1ENR_SPI3EN                  ((uint32_t)0x00008000)
-#define  RCC_APB1ENR_USART2EN                ((uint32_t)0x00020000)
-#define  RCC_APB1ENR_I2C1EN                  ((uint32_t)0x00200000)
-#define  RCC_APB1ENR_I2C2EN                  ((uint32_t)0x00400000)
-#define  RCC_APB1ENR_I2C3EN                  ((uint32_t)0x00800000)
-#define  RCC_APB1ENR_PWREN                   ((uint32_t)0x10000000)
+#define  RCC_APB1ENR_TIM2EN                  (0x00000001UL)
+#define  RCC_APB1ENR_TIM3EN                  (0x00000002UL)
+#define  RCC_APB1ENR_TIM4EN                  (0x00000004UL)
+#define  RCC_APB1ENR_TIM5EN                  (0x00000008UL)
+#define  RCC_APB1ENR_WWDGEN                  (0x00000800UL)
+#define  RCC_APB1ENR_SPI2EN                  (0x00004000UL)
+#define  RCC_APB1ENR_SPI3EN                  (0x00008000UL)
+#define  RCC_APB1ENR_USART2EN                (0x00020000UL)
+#define  RCC_APB1ENR_I2C1EN                  (0x00200000UL)
+#define  RCC_APB1ENR_I2C2EN                  (0x00400000UL)
+#define  RCC_APB1ENR_I2C3EN                  (0x00800000UL)
+#define  RCC_APB1ENR_PWREN                   (0x10000000UL)
 
 /********************  Bit definition for RCC_APB2ENR register  ***************/
-#define  RCC_APB2ENR_TIM1EN                  ((uint32_t)0x00000001)
-#define  RCC_APB2ENR_USART1EN                ((uint32_t)0x00000010)
-#define  RCC_APB2ENR_USART6EN                ((uint32_t)0x00000020)
-#define  RCC_APB2ENR_ADC1EN                  ((uint32_t)0x00000100)
-#define  RCC_APB2ENR_SDIOEN                  ((uint32_t)0x00000800)
-#define  RCC_APB2ENR_SPI1EN                  ((uint32_t)0x00001000)
-#define  RCC_APB2ENR_SPI4EN                  ((uint32_t)0x00002000)
-#define  RCC_APB2ENR_SYSCFGEN                ((uint32_t)0x00004000)
-#define  RCC_APB2ENR_TIM9EN                  ((uint32_t)0x00010000)
-#define  RCC_APB2ENR_TIM10EN                 ((uint32_t)0x00020000)
-#define  RCC_APB2ENR_TIM11EN                 ((uint32_t)0x00040000)
-#define  RCC_APB2ENR_SPI5EN                  ((uint32_t)0x00100000)
+#define  RCC_APB2ENR_TIM1EN                  (0x00000001UL)
+#define  RCC_APB2ENR_USART1EN                (0x00000010UL)
+#define  RCC_APB2ENR_USART6EN                (0x00000020UL)
+#define  RCC_APB2ENR_ADC1EN                  (0x00000100UL)
+#define  RCC_APB2ENR_SDIOEN                  (0x00000800UL)
+#define  RCC_APB2ENR_SPI1EN                  (0x00001000UL)
+#define  RCC_APB2ENR_SPI4EN                  (0x00002000UL)
+#define  RCC_APB2ENR_SYSCFGEN                (0x00004000UL)
+#define  RCC_APB2ENR_TIM9EN                  (0x00010000UL)
+#define  RCC_APB2ENR_TIM10EN                 (0x00020000UL)
+#define  RCC_APB2ENR_TIM11EN                 (0x00040000UL)
+#define  RCC_APB2ENR_SPI5EN                  (0x00100000UL)
 
 /********************  Bit definition for RCC_AHB1LPENR register  *************/
-#define  RCC_AHB1LPENR_GPIOALPEN             ((uint32_t)0x00000001)
-#define  RCC_AHB1LPENR_GPIOBLPEN             ((uint32_t)0x00000002)
-#define  RCC_AHB1LPENR_GPIOCLPEN             ((uint32_t)0x00000004)
-#define  RCC_AHB1LPENR_GPIODLPEN             ((uint32_t)0x00000008)
-#define  RCC_AHB1LPENR_GPIOELPEN             ((uint32_t)0x00000010)
-#define  RCC_AHB1LPENR_GPIOHLPEN             ((uint32_t)0x00000080)
-#define  RCC_AHB1LPENR_CRCLPEN               ((uint32_t)0x00001000)
-#define  RCC_AHB1LPENR_FLITFLPEN             ((uint32_t)0x00008000)
-#define  RCC_AHB1LPENR_SRAM1LPEN             ((uint32_t)0x00010000)
-#define  RCC_AHB1LPENR_SRAM2LPEN             ((uint32_t)0x00020000)
-#define  RCC_AHB1LPENR_BKPSRAMLPEN           ((uint32_t)0x00040000)
-#define  RCC_AHB1LPENR_DMA1LPEN              ((uint32_t)0x00200000)
-#define  RCC_AHB1LPENR_DMA2LPEN              ((uint32_t)0x00400000)
+#define  RCC_AHB1LPENR_GPIOALPEN             (0x00000001UL)
+#define  RCC_AHB1LPENR_GPIOBLPEN             (0x00000002UL)
+#define  RCC_AHB1LPENR_GPIOCLPEN             (0x00000004UL)
+#define  RCC_AHB1LPENR_GPIODLPEN             (0x00000008UL)
+#define  RCC_AHB1LPENR_GPIOELPEN             (0x00000010UL)
+#define  RCC_AHB1LPENR_GPIOHLPEN             (0x00000080UL)
+#define  RCC_AHB1LPENR_CRCLPEN               (0x00001000UL)
+#define  RCC_AHB1LPENR_FLITFLPEN             (0x00008000UL)
+#define  RCC_AHB1LPENR_SRAM1LPEN             (0x00010000UL)
+#define  RCC_AHB1LPENR_SRAM2LPEN             (0x00020000UL)
+#define  RCC_AHB1LPENR_BKPSRAMLPEN           (0x00040000UL)
+#define  RCC_AHB1LPENR_DMA1LPEN              (0x00200000UL)
+#define  RCC_AHB1LPENR_DMA2LPEN              (0x00400000UL)
 
 /********************  Bit definition for RCC_AHB2LPENR register  *************/
-#define  RCC_AHB2LPENR_OTGFSLPEN             ((uint32_t)0x00000080)
+#define  RCC_AHB2LPENR_OTGFSLPEN             (0x00000080UL)
 
 /********************  Bit definition for RCC_AHB3LPENR register  *************/
 
 /********************  Bit definition for RCC_APB1LPENR register  *************/
-#define  RCC_APB1LPENR_TIM2LPEN              ((uint32_t)0x00000001)
-#define  RCC_APB1LPENR_TIM3LPEN              ((uint32_t)0x00000002)
-#define  RCC_APB1LPENR_TIM4LPEN              ((uint32_t)0x00000004)
-#define  RCC_APB1LPENR_TIM5LPEN              ((uint32_t)0x00000008)
-#define  RCC_APB1LPENR_WWDGLPEN              ((uint32_t)0x00000800)
-#define  RCC_APB1LPENR_SPI2LPEN              ((uint32_t)0x00004000)
-#define  RCC_APB1LPENR_SPI3LPEN              ((uint32_t)0x00008000)
-#define  RCC_APB1LPENR_USART2LPEN            ((uint32_t)0x00020000)
-#define  RCC_APB1LPENR_I2C1LPEN              ((uint32_t)0x00200000)
-#define  RCC_APB1LPENR_I2C2LPEN              ((uint32_t)0x00400000)
-#define  RCC_APB1LPENR_I2C3LPEN              ((uint32_t)0x00800000)
-#define  RCC_APB1LPENR_PWRLPEN               ((uint32_t)0x10000000)
-#define  RCC_APB1LPENR_DACLPEN               ((uint32_t)0x20000000)
+#define  RCC_APB1LPENR_TIM2LPEN              (0x00000001UL)
+#define  RCC_APB1LPENR_TIM3LPEN              (0x00000002UL)
+#define  RCC_APB1LPENR_TIM4LPEN              (0x00000004UL)
+#define  RCC_APB1LPENR_TIM5LPEN              (0x00000008UL)
+#define  RCC_APB1LPENR_WWDGLPEN              (0x00000800UL)
+#define  RCC_APB1LPENR_SPI2LPEN              (0x00004000UL)
+#define  RCC_APB1LPENR_SPI3LPEN              (0x00008000UL)
+#define  RCC_APB1LPENR_USART2LPEN            (0x00020000UL)
+#define  RCC_APB1LPENR_I2C1LPEN              (0x00200000UL)
+#define  RCC_APB1LPENR_I2C2LPEN              (0x00400000UL)
+#define  RCC_APB1LPENR_I2C3LPEN              (0x00800000UL)
+#define  RCC_APB1LPENR_PWRLPEN               (0x10000000UL)
+#define  RCC_APB1LPENR_DACLPEN               (0x20000000UL)
 
 /********************  Bit definition for RCC_APB2LPENR register  *************/
-#define  RCC_APB2LPENR_TIM1LPEN              ((uint32_t)0x00000001)
-#define  RCC_APB2LPENR_USART1LPEN            ((uint32_t)0x00000010)
-#define  RCC_APB2LPENR_USART6LPEN            ((uint32_t)0x00000020)
-#define  RCC_APB2LPENR_ADC1LPEN              ((uint32_t)0x00000100)
-#define  RCC_APB2LPENR_SDIOLPEN              ((uint32_t)0x00000800)
-#define  RCC_APB2LPENR_SPI1LPEN              ((uint32_t)0x00001000)
-#define  RCC_APB2LPENR_SPI4LPEN              ((uint32_t)0x00002000)
-#define  RCC_APB2LPENR_SYSCFGLPEN            ((uint32_t)0x00004000)
-#define  RCC_APB2LPENR_TIM9LPEN              ((uint32_t)0x00010000)
-#define  RCC_APB2LPENR_TIM10LPEN             ((uint32_t)0x00020000)
-#define  RCC_APB2LPENR_TIM11LPEN             ((uint32_t)0x00040000)
-#define  RCC_APB2LPENR_SPI5LPEN              ((uint32_t)0x00100000)
+#define  RCC_APB2LPENR_TIM1LPEN              (0x00000001UL)
+#define  RCC_APB2LPENR_USART1LPEN            (0x00000010UL)
+#define  RCC_APB2LPENR_USART6LPEN            (0x00000020UL)
+#define  RCC_APB2LPENR_ADC1LPEN              (0x00000100UL)
+#define  RCC_APB2LPENR_SDIOLPEN              (0x00000800UL)
+#define  RCC_APB2LPENR_SPI1LPEN              (0x00001000UL)
+#define  RCC_APB2LPENR_SPI4LPEN              (0x00002000UL)
+#define  RCC_APB2LPENR_SYSCFGLPEN            (0x00004000UL)
+#define  RCC_APB2LPENR_TIM9LPEN              (0x00010000UL)
+#define  RCC_APB2LPENR_TIM10LPEN             (0x00020000UL)
+#define  RCC_APB2LPENR_TIM11LPEN             (0x00040000UL)
+#define  RCC_APB2LPENR_SPI5LPEN              (0x00100000UL)
 
 /********************  Bit definition for RCC_BDCR register  ******************/
-#define  RCC_BDCR_LSEON                      ((uint32_t)0x00000001)
-#define  RCC_BDCR_LSERDY                     ((uint32_t)0x00000002)
-#define  RCC_BDCR_LSEBYP                     ((uint32_t)0x00000004)
-#define  RCC_BDCR_LSEMOD                     ((uint32_t)0x00000008)
+#define  RCC_BDCR_LSEON                      (0x00000001UL)
+#define  RCC_BDCR_LSERDY                     (0x00000002UL)
+#define  RCC_BDCR_LSEBYP                     (0x00000004UL)
+#define  RCC_BDCR_LSEMOD                     (0x00000008UL)
 
-#define  RCC_BDCR_RTCSEL                    ((uint32_t)0x00000300)
-#define  RCC_BDCR_RTCSEL_0                  ((uint32_t)0x00000100)
-#define  RCC_BDCR_RTCSEL_1                  ((uint32_t)0x00000200)
+#define  RCC_BDCR_RTCSEL                    (0x00000300UL)
+#define  RCC_BDCR_RTCSEL_0                  (0x00000100UL)
+#define  RCC_BDCR_RTCSEL_1                  (0x00000200UL)
 
-#define  RCC_BDCR_RTCEN                      ((uint32_t)0x00008000)
-#define  RCC_BDCR_BDRST                      ((uint32_t)0x00010000)
+#define  RCC_BDCR_RTCEN                      (0x00008000UL)
+#define  RCC_BDCR_BDRST                      (0x00010000UL)
 
 /********************  Bit definition for RCC_CSR register  *******************/
-#define  RCC_CSR_LSION                       ((uint32_t)0x00000001)
-#define  RCC_CSR_LSIRDY                      ((uint32_t)0x00000002)
-#define  RCC_CSR_RMVF                        ((uint32_t)0x01000000)
-#define  RCC_CSR_BORRSTF                     ((uint32_t)0x02000000)
-#define  RCC_CSR_PADRSTF                     ((uint32_t)0x04000000)
-#define  RCC_CSR_PORRSTF                     ((uint32_t)0x08000000)
-#define  RCC_CSR_SFTRSTF                     ((uint32_t)0x10000000)
-#define  RCC_CSR_WDGRSTF                     ((uint32_t)0x20000000)
-#define  RCC_CSR_WWDGRSTF                    ((uint32_t)0x40000000)
-#define  RCC_CSR_LPWRRSTF                    ((uint32_t)0x80000000)
+#define  RCC_CSR_LSION                       (0x00000001UL)
+#define  RCC_CSR_LSIRDY                      (0x00000002UL)
+#define  RCC_CSR_RMVF                        (0x01000000UL)
+#define  RCC_CSR_BORRSTF                     (0x02000000UL)
+#define  RCC_CSR_PADRSTF                     (0x04000000UL)
+#define  RCC_CSR_PORRSTF                     (0x08000000UL)
+#define  RCC_CSR_SFTRSTF                     (0x10000000UL)
+#define  RCC_CSR_WDGRSTF                     (0x20000000UL)
+#define  RCC_CSR_WWDGRSTF                    (0x40000000UL)
+#define  RCC_CSR_LPWRRSTF                    (0x80000000UL)
 
 /********************  Bit definition for RCC_SSCGR register  *****************/
-#define  RCC_SSCGR_MODPER                    ((uint32_t)0x00001FFF)
-#define  RCC_SSCGR_INCSTEP                   ((uint32_t)0x0FFFE000)
-#define  RCC_SSCGR_SPREADSEL                 ((uint32_t)0x40000000)
-#define  RCC_SSCGR_SSCGEN                    ((uint32_t)0x80000000)
+#define  RCC_SSCGR_MODPER                    (0x00001FFFUL)
+#define  RCC_SSCGR_INCSTEP                   (0x0FFFE000UL)
+#define  RCC_SSCGR_SPREADSEL                 (0x40000000UL)
+#define  RCC_SSCGR_SSCGEN                    (0x80000000UL)
 
 /********************  Bit definition for RCC_PLLI2SCFGR register  ************/
-#define  RCC_PLLI2SCFGR_PLLI2SM              ((uint32_t)0x0000003F)
-#define  RCC_PLLI2SCFGR_PLLI2SM_0            ((uint32_t)0x00000001)
-#define  RCC_PLLI2SCFGR_PLLI2SM_1            ((uint32_t)0x00000002)
-#define  RCC_PLLI2SCFGR_PLLI2SM_2            ((uint32_t)0x00000004)
-#define  RCC_PLLI2SCFGR_PLLI2SM_3            ((uint32_t)0x00000008)
-#define  RCC_PLLI2SCFGR_PLLI2SM_4            ((uint32_t)0x00000010)
-#define  RCC_PLLI2SCFGR_PLLI2SM_5            ((uint32_t)0x00000020)
+#define  RCC_PLLI2SCFGR_PLLI2SM              (0x0000003FUL)
+#define  RCC_PLLI2SCFGR_PLLI2SM_0            (0x00000001UL)
+#define  RCC_PLLI2SCFGR_PLLI2SM_1            (0x00000002UL)
+#define  RCC_PLLI2SCFGR_PLLI2SM_2            (0x00000004UL)
+#define  RCC_PLLI2SCFGR_PLLI2SM_3            (0x00000008UL)
+#define  RCC_PLLI2SCFGR_PLLI2SM_4            (0x00000010UL)
+#define  RCC_PLLI2SCFGR_PLLI2SM_5            (0x00000020UL)
 
-#define  RCC_PLLI2SCFGR_PLLI2SN              ((uint32_t)0x00007FC0)
-#define  RCC_PLLI2SCFGR_PLLI2SN_0            ((uint32_t)0x00000040)
-#define  RCC_PLLI2SCFGR_PLLI2SN_1            ((uint32_t)0x00000080)
-#define  RCC_PLLI2SCFGR_PLLI2SN_2            ((uint32_t)0x00000100)
-#define  RCC_PLLI2SCFGR_PLLI2SN_3            ((uint32_t)0x00000200)
-#define  RCC_PLLI2SCFGR_PLLI2SN_4            ((uint32_t)0x00000400)
-#define  RCC_PLLI2SCFGR_PLLI2SN_5            ((uint32_t)0x00000800)
-#define  RCC_PLLI2SCFGR_PLLI2SN_6            ((uint32_t)0x00001000)
-#define  RCC_PLLI2SCFGR_PLLI2SN_7            ((uint32_t)0x00002000)
-#define  RCC_PLLI2SCFGR_PLLI2SN_8            ((uint32_t)0x00004000)
+#define  RCC_PLLI2SCFGR_PLLI2SN              (0x00007FC0UL)
+#define  RCC_PLLI2SCFGR_PLLI2SN_0            (0x00000040UL)
+#define  RCC_PLLI2SCFGR_PLLI2SN_1            (0x00000080UL)
+#define  RCC_PLLI2SCFGR_PLLI2SN_2            (0x00000100UL)
+#define  RCC_PLLI2SCFGR_PLLI2SN_3            (0x00000200UL)
+#define  RCC_PLLI2SCFGR_PLLI2SN_4            (0x00000400UL)
+#define  RCC_PLLI2SCFGR_PLLI2SN_5            (0x00000800UL)
+#define  RCC_PLLI2SCFGR_PLLI2SN_6            (0x00001000UL)
+#define  RCC_PLLI2SCFGR_PLLI2SN_7            (0x00002000UL)
+#define  RCC_PLLI2SCFGR_PLLI2SN_8            (0x00004000UL)
 
-#define  RCC_PLLI2SCFGR_PLLI2SR              ((uint32_t)0x70000000)
-#define  RCC_PLLI2SCFGR_PLLI2SR_0            ((uint32_t)0x10000000)
-#define  RCC_PLLI2SCFGR_PLLI2SR_1            ((uint32_t)0x20000000)
-#define  RCC_PLLI2SCFGR_PLLI2SR_2            ((uint32_t)0x40000000)
+#define  RCC_PLLI2SCFGR_PLLI2SR              (0x70000000UL)
+#define  RCC_PLLI2SCFGR_PLLI2SR_0            (0x10000000UL)
+#define  RCC_PLLI2SCFGR_PLLI2SR_1            (0x20000000UL)
+#define  RCC_PLLI2SCFGR_PLLI2SR_2            (0x40000000UL)
 
 
 /******************************************************************************/
 /*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
+/*                           Real-Time Clock (RTCUL)                            */
 /*                                                                            */
 /******************************************************************************/
 /********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM                            ((uint32_t)0x00400000)
-#define RTC_TR_HT                            ((uint32_t)0x00300000)
-#define RTC_TR_HT_0                          ((uint32_t)0x00100000)
-#define RTC_TR_HT_1                          ((uint32_t)0x00200000)
-#define RTC_TR_HU                            ((uint32_t)0x000F0000)
-#define RTC_TR_HU_0                          ((uint32_t)0x00010000)
-#define RTC_TR_HU_1                          ((uint32_t)0x00020000)
-#define RTC_TR_HU_2                          ((uint32_t)0x00040000)
-#define RTC_TR_HU_3                          ((uint32_t)0x00080000)
-#define RTC_TR_MNT                           ((uint32_t)0x00007000)
-#define RTC_TR_MNT_0                         ((uint32_t)0x00001000)
-#define RTC_TR_MNT_1                         ((uint32_t)0x00002000)
-#define RTC_TR_MNT_2                         ((uint32_t)0x00004000)
-#define RTC_TR_MNU                           ((uint32_t)0x00000F00)
-#define RTC_TR_MNU_0                         ((uint32_t)0x00000100)
-#define RTC_TR_MNU_1                         ((uint32_t)0x00000200)
-#define RTC_TR_MNU_2                         ((uint32_t)0x00000400)
-#define RTC_TR_MNU_3                         ((uint32_t)0x00000800)
-#define RTC_TR_ST                            ((uint32_t)0x00000070)
-#define RTC_TR_ST_0                          ((uint32_t)0x00000010)
-#define RTC_TR_ST_1                          ((uint32_t)0x00000020)
-#define RTC_TR_ST_2                          ((uint32_t)0x00000040)
-#define RTC_TR_SU                            ((uint32_t)0x0000000F)
-#define RTC_TR_SU_0                          ((uint32_t)0x00000001)
-#define RTC_TR_SU_1                          ((uint32_t)0x00000002)
-#define RTC_TR_SU_2                          ((uint32_t)0x00000004)
-#define RTC_TR_SU_3                          ((uint32_t)0x00000008)
+#define RTC_TR_PM                            (0x00400000UL)
+#define RTC_TR_HT                            (0x00300000UL)
+#define RTC_TR_HT_0                          (0x00100000UL)
+#define RTC_TR_HT_1                          (0x00200000UL)
+#define RTC_TR_HU                            (0x000F0000UL)
+#define RTC_TR_HU_0                          (0x00010000UL)
+#define RTC_TR_HU_1                          (0x00020000UL)
+#define RTC_TR_HU_2                          (0x00040000UL)
+#define RTC_TR_HU_3                          (0x00080000UL)
+#define RTC_TR_MNT                           (0x00007000UL)
+#define RTC_TR_MNT_0                         (0x00001000UL)
+#define RTC_TR_MNT_1                         (0x00002000UL)
+#define RTC_TR_MNT_2                         (0x00004000UL)
+#define RTC_TR_MNU                           (0x00000F00UL)
+#define RTC_TR_MNU_0                         (0x00000100UL)
+#define RTC_TR_MNU_1                         (0x00000200UL)
+#define RTC_TR_MNU_2                         (0x00000400UL)
+#define RTC_TR_MNU_3                         (0x00000800UL)
+#define RTC_TR_ST                            (0x00000070UL)
+#define RTC_TR_ST_0                          (0x00000010UL)
+#define RTC_TR_ST_1                          (0x00000020UL)
+#define RTC_TR_ST_2                          (0x00000040UL)
+#define RTC_TR_SU                            (0x0000000FUL)
+#define RTC_TR_SU_0                          (0x00000001UL)
+#define RTC_TR_SU_1                          (0x00000002UL)
+#define RTC_TR_SU_2                          (0x00000004UL)
+#define RTC_TR_SU_3                          (0x00000008UL)
 
 /********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT                            ((uint32_t)0x00F00000)
-#define RTC_DR_YT_0                          ((uint32_t)0x00100000)
-#define RTC_DR_YT_1                          ((uint32_t)0x00200000)
-#define RTC_DR_YT_2                          ((uint32_t)0x00400000)
-#define RTC_DR_YT_3                          ((uint32_t)0x00800000)
-#define RTC_DR_YU                            ((uint32_t)0x000F0000)
-#define RTC_DR_YU_0                          ((uint32_t)0x00010000)
-#define RTC_DR_YU_1                          ((uint32_t)0x00020000)
-#define RTC_DR_YU_2                          ((uint32_t)0x00040000)
-#define RTC_DR_YU_3                          ((uint32_t)0x00080000)
-#define RTC_DR_WDU                           ((uint32_t)0x0000E000)
-#define RTC_DR_WDU_0                         ((uint32_t)0x00002000)
-#define RTC_DR_WDU_1                         ((uint32_t)0x00004000)
-#define RTC_DR_WDU_2                         ((uint32_t)0x00008000)
-#define RTC_DR_MT                            ((uint32_t)0x00001000)
-#define RTC_DR_MU                            ((uint32_t)0x00000F00)
-#define RTC_DR_MU_0                          ((uint32_t)0x00000100)
-#define RTC_DR_MU_1                          ((uint32_t)0x00000200)
-#define RTC_DR_MU_2                          ((uint32_t)0x00000400)
-#define RTC_DR_MU_3                          ((uint32_t)0x00000800)
-#define RTC_DR_DT                            ((uint32_t)0x00000030)
-#define RTC_DR_DT_0                          ((uint32_t)0x00000010)
-#define RTC_DR_DT_1                          ((uint32_t)0x00000020)
-#define RTC_DR_DU                            ((uint32_t)0x0000000F)
-#define RTC_DR_DU_0                          ((uint32_t)0x00000001)
-#define RTC_DR_DU_1                          ((uint32_t)0x00000002)
-#define RTC_DR_DU_2                          ((uint32_t)0x00000004)
-#define RTC_DR_DU_3                          ((uint32_t)0x00000008)
+#define RTC_DR_YT                            (0x00F00000UL)
+#define RTC_DR_YT_0                          (0x00100000UL)
+#define RTC_DR_YT_1                          (0x00200000UL)
+#define RTC_DR_YT_2                          (0x00400000UL)
+#define RTC_DR_YT_3                          (0x00800000UL)
+#define RTC_DR_YU                            (0x000F0000UL)
+#define RTC_DR_YU_0                          (0x00010000UL)
+#define RTC_DR_YU_1                          (0x00020000UL)
+#define RTC_DR_YU_2                          (0x00040000UL)
+#define RTC_DR_YU_3                          (0x00080000UL)
+#define RTC_DR_WDU                           (0x0000E000UL)
+#define RTC_DR_WDU_0                         (0x00002000UL)
+#define RTC_DR_WDU_1                         (0x00004000UL)
+#define RTC_DR_WDU_2                         (0x00008000UL)
+#define RTC_DR_MT                            (0x00001000UL)
+#define RTC_DR_MU                            (0x00000F00UL)
+#define RTC_DR_MU_0                          (0x00000100UL)
+#define RTC_DR_MU_1                          (0x00000200UL)
+#define RTC_DR_MU_2                          (0x00000400UL)
+#define RTC_DR_MU_3                          (0x00000800UL)
+#define RTC_DR_DT                            (0x00000030UL)
+#define RTC_DR_DT_0                          (0x00000010UL)
+#define RTC_DR_DT_1                          (0x00000020UL)
+#define RTC_DR_DU                            (0x0000000FUL)
+#define RTC_DR_DU_0                          (0x00000001UL)
+#define RTC_DR_DU_1                          (0x00000002UL)
+#define RTC_DR_DU_2                          (0x00000004UL)
+#define RTC_DR_DU_3                          (0x00000008UL)
 
 /********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE                           ((uint32_t)0x00800000)
-#define RTC_CR_OSEL                          ((uint32_t)0x00600000)
-#define RTC_CR_OSEL_0                        ((uint32_t)0x00200000)
-#define RTC_CR_OSEL_1                        ((uint32_t)0x00400000)
-#define RTC_CR_POL                           ((uint32_t)0x00100000)
-#define RTC_CR_COSEL                         ((uint32_t)0x00080000)
-#define RTC_CR_BCK                           ((uint32_t)0x00040000)
-#define RTC_CR_SUB1H                         ((uint32_t)0x00020000)
-#define RTC_CR_ADD1H                         ((uint32_t)0x00010000)
-#define RTC_CR_TSIE                          ((uint32_t)0x00008000)
-#define RTC_CR_WUTIE                         ((uint32_t)0x00004000)
-#define RTC_CR_ALRBIE                        ((uint32_t)0x00002000)
-#define RTC_CR_ALRAIE                        ((uint32_t)0x00001000)
-#define RTC_CR_TSE                           ((uint32_t)0x00000800)
-#define RTC_CR_WUTE                          ((uint32_t)0x00000400)
-#define RTC_CR_ALRBE                         ((uint32_t)0x00000200)
-#define RTC_CR_ALRAE                         ((uint32_t)0x00000100)
-#define RTC_CR_DCE                           ((uint32_t)0x00000080)
-#define RTC_CR_FMT                           ((uint32_t)0x00000040)
-#define RTC_CR_BYPSHAD                       ((uint32_t)0x00000020)
-#define RTC_CR_REFCKON                       ((uint32_t)0x00000010)
-#define RTC_CR_TSEDGE                        ((uint32_t)0x00000008)
-#define RTC_CR_WUCKSEL                       ((uint32_t)0x00000007)
-#define RTC_CR_WUCKSEL_0                     ((uint32_t)0x00000001)
-#define RTC_CR_WUCKSEL_1                     ((uint32_t)0x00000002)
-#define RTC_CR_WUCKSEL_2                     ((uint32_t)0x00000004)
+#define RTC_CR_COE                           (0x00800000UL)
+#define RTC_CR_OSEL                          (0x00600000UL)
+#define RTC_CR_OSEL_0                        (0x00200000UL)
+#define RTC_CR_OSEL_1                        (0x00400000UL)
+#define RTC_CR_POL                           (0x00100000UL)
+#define RTC_CR_COSEL                         (0x00080000UL)
+#define RTC_CR_BCK                           (0x00040000UL)
+#define RTC_CR_SUB1H                         (0x00020000UL)
+#define RTC_CR_ADD1H                         (0x00010000UL)
+#define RTC_CR_TSIE                          (0x00008000UL)
+#define RTC_CR_WUTIE                         (0x00004000UL)
+#define RTC_CR_ALRBIE                        (0x00002000UL)
+#define RTC_CR_ALRAIE                        (0x00001000UL)
+#define RTC_CR_TSE                           (0x00000800UL)
+#define RTC_CR_WUTE                          (0x00000400UL)
+#define RTC_CR_ALRBE                         (0x00000200UL)
+#define RTC_CR_ALRAE                         (0x00000100UL)
+#define RTC_CR_DCE                           (0x00000080UL)
+#define RTC_CR_FMT                           (0x00000040UL)
+#define RTC_CR_BYPSHAD                       (0x00000020UL)
+#define RTC_CR_REFCKON                       (0x00000010UL)
+#define RTC_CR_TSEDGE                        (0x00000008UL)
+#define RTC_CR_WUCKSEL                       (0x00000007UL)
+#define RTC_CR_WUCKSEL_0                     (0x00000001UL)
+#define RTC_CR_WUCKSEL_1                     (0x00000002UL)
+#define RTC_CR_WUCKSEL_2                     (0x00000004UL)
 
 /********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF                      ((uint32_t)0x00010000)
-#define RTC_ISR_TAMP1F                       ((uint32_t)0x00002000)
-#define RTC_ISR_TAMP2F                       ((uint32_t)0x00004000)
-#define RTC_ISR_TSOVF                        ((uint32_t)0x00001000)
-#define RTC_ISR_TSF                          ((uint32_t)0x00000800)
-#define RTC_ISR_WUTF                         ((uint32_t)0x00000400)
-#define RTC_ISR_ALRBF                        ((uint32_t)0x00000200)
-#define RTC_ISR_ALRAF                        ((uint32_t)0x00000100)
-#define RTC_ISR_INIT                         ((uint32_t)0x00000080)
-#define RTC_ISR_INITF                        ((uint32_t)0x00000040)
-#define RTC_ISR_RSF                          ((uint32_t)0x00000020)
-#define RTC_ISR_INITS                        ((uint32_t)0x00000010)
-#define RTC_ISR_SHPF                         ((uint32_t)0x00000008)
-#define RTC_ISR_WUTWF                        ((uint32_t)0x00000004)
-#define RTC_ISR_ALRBWF                       ((uint32_t)0x00000002)
-#define RTC_ISR_ALRAWF                       ((uint32_t)0x00000001)
+#define RTC_ISR_RECALPF                      (0x00010000UL)
+#define RTC_ISR_TAMP1F                       (0x00002000UL)
+#define RTC_ISR_TAMP2F                       (0x00004000UL)
+#define RTC_ISR_TSOVF                        (0x00001000UL)
+#define RTC_ISR_TSF                          (0x00000800UL)
+#define RTC_ISR_WUTF                         (0x00000400UL)
+#define RTC_ISR_ALRBF                        (0x00000200UL)
+#define RTC_ISR_ALRAF                        (0x00000100UL)
+#define RTC_ISR_INIT                         (0x00000080UL)
+#define RTC_ISR_INITF                        (0x00000040UL)
+#define RTC_ISR_RSF                          (0x00000020UL)
+#define RTC_ISR_INITS                        (0x00000010UL)
+#define RTC_ISR_SHPF                         (0x00000008UL)
+#define RTC_ISR_WUTWF                        (0x00000004UL)
+#define RTC_ISR_ALRBWF                       (0x00000002UL)
+#define RTC_ISR_ALRAWF                       (0x00000001UL)
 
 /********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A                    ((uint32_t)0x007F0000)
-#define RTC_PRER_PREDIV_S                    ((uint32_t)0x00007FFF)
+#define RTC_PRER_PREDIV_A                    (0x007F0000UL)
+#define RTC_PRER_PREDIV_S                    (0x00007FFFUL)
 
 /********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT                         ((uint32_t)0x0000FFFF)
+#define RTC_WUTR_WUT                         (0x0000FFFFUL)
 
 /********************  Bits definition for RTC_CALIBR register  ***************/
-#define RTC_CALIBR_DCS                       ((uint32_t)0x00000080)
-#define RTC_CALIBR_DC                        ((uint32_t)0x0000001F)
+#define RTC_CALIBR_DCS                       (0x00000080UL)
+#define RTC_CALIBR_DC                        (0x0000001FUL)
 
 /********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4                      ((uint32_t)0x80000000)
-#define RTC_ALRMAR_WDSEL                     ((uint32_t)0x40000000)
-#define RTC_ALRMAR_DT                        ((uint32_t)0x30000000)
-#define RTC_ALRMAR_DT_0                      ((uint32_t)0x10000000)
-#define RTC_ALRMAR_DT_1                      ((uint32_t)0x20000000)
-#define RTC_ALRMAR_DU                        ((uint32_t)0x0F000000)
-#define RTC_ALRMAR_DU_0                      ((uint32_t)0x01000000)
-#define RTC_ALRMAR_DU_1                      ((uint32_t)0x02000000)
-#define RTC_ALRMAR_DU_2                      ((uint32_t)0x04000000)
-#define RTC_ALRMAR_DU_3                      ((uint32_t)0x08000000)
-#define RTC_ALRMAR_MSK3                      ((uint32_t)0x00800000)
-#define RTC_ALRMAR_PM                        ((uint32_t)0x00400000)
-#define RTC_ALRMAR_HT                        ((uint32_t)0x00300000)
-#define RTC_ALRMAR_HT_0                      ((uint32_t)0x00100000)
-#define RTC_ALRMAR_HT_1                      ((uint32_t)0x00200000)
-#define RTC_ALRMAR_HU                        ((uint32_t)0x000F0000)
-#define RTC_ALRMAR_HU_0                      ((uint32_t)0x00010000)
-#define RTC_ALRMAR_HU_1                      ((uint32_t)0x00020000)
-#define RTC_ALRMAR_HU_2                      ((uint32_t)0x00040000)
-#define RTC_ALRMAR_HU_3                      ((uint32_t)0x00080000)
-#define RTC_ALRMAR_MSK2                      ((uint32_t)0x00008000)
-#define RTC_ALRMAR_MNT                       ((uint32_t)0x00007000)
-#define RTC_ALRMAR_MNT_0                     ((uint32_t)0x00001000)
-#define RTC_ALRMAR_MNT_1                     ((uint32_t)0x00002000)
-#define RTC_ALRMAR_MNT_2                     ((uint32_t)0x00004000)
-#define RTC_ALRMAR_MNU                       ((uint32_t)0x00000F00)
-#define RTC_ALRMAR_MNU_0                     ((uint32_t)0x00000100)
-#define RTC_ALRMAR_MNU_1                     ((uint32_t)0x00000200)
-#define RTC_ALRMAR_MNU_2                     ((uint32_t)0x00000400)
-#define RTC_ALRMAR_MNU_3                     ((uint32_t)0x00000800)
-#define RTC_ALRMAR_MSK1                      ((uint32_t)0x00000080)
-#define RTC_ALRMAR_ST                        ((uint32_t)0x00000070)
-#define RTC_ALRMAR_ST_0                      ((uint32_t)0x00000010)
-#define RTC_ALRMAR_ST_1                      ((uint32_t)0x00000020)
-#define RTC_ALRMAR_ST_2                      ((uint32_t)0x00000040)
-#define RTC_ALRMAR_SU                        ((uint32_t)0x0000000F)
-#define RTC_ALRMAR_SU_0                      ((uint32_t)0x00000001)
-#define RTC_ALRMAR_SU_1                      ((uint32_t)0x00000002)
-#define RTC_ALRMAR_SU_2                      ((uint32_t)0x00000004)
-#define RTC_ALRMAR_SU_3                      ((uint32_t)0x00000008)
+#define RTC_ALRMAR_MSK4                      (0x80000000UL)
+#define RTC_ALRMAR_WDSEL                     (0x40000000UL)
+#define RTC_ALRMAR_DT                        (0x30000000UL)
+#define RTC_ALRMAR_DT_0                      (0x10000000UL)
+#define RTC_ALRMAR_DT_1                      (0x20000000UL)
+#define RTC_ALRMAR_DU                        (0x0F000000UL)
+#define RTC_ALRMAR_DU_0                      (0x01000000UL)
+#define RTC_ALRMAR_DU_1                      (0x02000000UL)
+#define RTC_ALRMAR_DU_2                      (0x04000000UL)
+#define RTC_ALRMAR_DU_3                      (0x08000000UL)
+#define RTC_ALRMAR_MSK3                      (0x00800000UL)
+#define RTC_ALRMAR_PM                        (0x00400000UL)
+#define RTC_ALRMAR_HT                        (0x00300000UL)
+#define RTC_ALRMAR_HT_0                      (0x00100000UL)
+#define RTC_ALRMAR_HT_1                      (0x00200000UL)
+#define RTC_ALRMAR_HU                        (0x000F0000UL)
+#define RTC_ALRMAR_HU_0                      (0x00010000UL)
+#define RTC_ALRMAR_HU_1                      (0x00020000UL)
+#define RTC_ALRMAR_HU_2                      (0x00040000UL)
+#define RTC_ALRMAR_HU_3                      (0x00080000UL)
+#define RTC_ALRMAR_MSK2                      (0x00008000UL)
+#define RTC_ALRMAR_MNT                       (0x00007000UL)
+#define RTC_ALRMAR_MNT_0                     (0x00001000UL)
+#define RTC_ALRMAR_MNT_1                     (0x00002000UL)
+#define RTC_ALRMAR_MNT_2                     (0x00004000UL)
+#define RTC_ALRMAR_MNU                       (0x00000F00UL)
+#define RTC_ALRMAR_MNU_0                     (0x00000100UL)
+#define RTC_ALRMAR_MNU_1                     (0x00000200UL)
+#define RTC_ALRMAR_MNU_2                     (0x00000400UL)
+#define RTC_ALRMAR_MNU_3                     (0x00000800UL)
+#define RTC_ALRMAR_MSK1                      (0x00000080UL)
+#define RTC_ALRMAR_ST                        (0x00000070UL)
+#define RTC_ALRMAR_ST_0                      (0x00000010UL)
+#define RTC_ALRMAR_ST_1                      (0x00000020UL)
+#define RTC_ALRMAR_ST_2                      (0x00000040UL)
+#define RTC_ALRMAR_SU                        (0x0000000FUL)
+#define RTC_ALRMAR_SU_0                      (0x00000001UL)
+#define RTC_ALRMAR_SU_1                      (0x00000002UL)
+#define RTC_ALRMAR_SU_2                      (0x00000004UL)
+#define RTC_ALRMAR_SU_3                      (0x00000008UL)
 
 /********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4                      ((uint32_t)0x80000000)
-#define RTC_ALRMBR_WDSEL                     ((uint32_t)0x40000000)
-#define RTC_ALRMBR_DT                        ((uint32_t)0x30000000)
-#define RTC_ALRMBR_DT_0                      ((uint32_t)0x10000000)
-#define RTC_ALRMBR_DT_1                      ((uint32_t)0x20000000)
-#define RTC_ALRMBR_DU                        ((uint32_t)0x0F000000)
-#define RTC_ALRMBR_DU_0                      ((uint32_t)0x01000000)
-#define RTC_ALRMBR_DU_1                      ((uint32_t)0x02000000)
-#define RTC_ALRMBR_DU_2                      ((uint32_t)0x04000000)
-#define RTC_ALRMBR_DU_3                      ((uint32_t)0x08000000)
-#define RTC_ALRMBR_MSK3                      ((uint32_t)0x00800000)
-#define RTC_ALRMBR_PM                        ((uint32_t)0x00400000)
-#define RTC_ALRMBR_HT                        ((uint32_t)0x00300000)
-#define RTC_ALRMBR_HT_0                      ((uint32_t)0x00100000)
-#define RTC_ALRMBR_HT_1                      ((uint32_t)0x00200000)
-#define RTC_ALRMBR_HU                        ((uint32_t)0x000F0000)
-#define RTC_ALRMBR_HU_0                      ((uint32_t)0x00010000)
-#define RTC_ALRMBR_HU_1                      ((uint32_t)0x00020000)
-#define RTC_ALRMBR_HU_2                      ((uint32_t)0x00040000)
-#define RTC_ALRMBR_HU_3                      ((uint32_t)0x00080000)
-#define RTC_ALRMBR_MSK2                      ((uint32_t)0x00008000)
-#define RTC_ALRMBR_MNT                       ((uint32_t)0x00007000)
-#define RTC_ALRMBR_MNT_0                     ((uint32_t)0x00001000)
-#define RTC_ALRMBR_MNT_1                     ((uint32_t)0x00002000)
-#define RTC_ALRMBR_MNT_2                     ((uint32_t)0x00004000)
-#define RTC_ALRMBR_MNU                       ((uint32_t)0x00000F00)
-#define RTC_ALRMBR_MNU_0                     ((uint32_t)0x00000100)
-#define RTC_ALRMBR_MNU_1                     ((uint32_t)0x00000200)
-#define RTC_ALRMBR_MNU_2                     ((uint32_t)0x00000400)
-#define RTC_ALRMBR_MNU_3                     ((uint32_t)0x00000800)
-#define RTC_ALRMBR_MSK1                      ((uint32_t)0x00000080)
-#define RTC_ALRMBR_ST                        ((uint32_t)0x00000070)
-#define RTC_ALRMBR_ST_0                      ((uint32_t)0x00000010)
-#define RTC_ALRMBR_ST_1                      ((uint32_t)0x00000020)
-#define RTC_ALRMBR_ST_2                      ((uint32_t)0x00000040)
-#define RTC_ALRMBR_SU                        ((uint32_t)0x0000000F)
-#define RTC_ALRMBR_SU_0                      ((uint32_t)0x00000001)
-#define RTC_ALRMBR_SU_1                      ((uint32_t)0x00000002)
-#define RTC_ALRMBR_SU_2                      ((uint32_t)0x00000004)
-#define RTC_ALRMBR_SU_3                      ((uint32_t)0x00000008)
+#define RTC_ALRMBR_MSK4                      (0x80000000UL)
+#define RTC_ALRMBR_WDSEL                     (0x40000000UL)
+#define RTC_ALRMBR_DT                        (0x30000000UL)
+#define RTC_ALRMBR_DT_0                      (0x10000000UL)
+#define RTC_ALRMBR_DT_1                      (0x20000000UL)
+#define RTC_ALRMBR_DU                        (0x0F000000UL)
+#define RTC_ALRMBR_DU_0                      (0x01000000UL)
+#define RTC_ALRMBR_DU_1                      (0x02000000UL)
+#define RTC_ALRMBR_DU_2                      (0x04000000UL)
+#define RTC_ALRMBR_DU_3                      (0x08000000UL)
+#define RTC_ALRMBR_MSK3                      (0x00800000UL)
+#define RTC_ALRMBR_PM                        (0x00400000UL)
+#define RTC_ALRMBR_HT                        (0x00300000UL)
+#define RTC_ALRMBR_HT_0                      (0x00100000UL)
+#define RTC_ALRMBR_HT_1                      (0x00200000UL)
+#define RTC_ALRMBR_HU                        (0x000F0000UL)
+#define RTC_ALRMBR_HU_0                      (0x00010000UL)
+#define RTC_ALRMBR_HU_1                      (0x00020000UL)
+#define RTC_ALRMBR_HU_2                      (0x00040000UL)
+#define RTC_ALRMBR_HU_3                      (0x00080000UL)
+#define RTC_ALRMBR_MSK2                      (0x00008000UL)
+#define RTC_ALRMBR_MNT                       (0x00007000UL)
+#define RTC_ALRMBR_MNT_0                     (0x00001000UL)
+#define RTC_ALRMBR_MNT_1                     (0x00002000UL)
+#define RTC_ALRMBR_MNT_2                     (0x00004000UL)
+#define RTC_ALRMBR_MNU                       (0x00000F00UL)
+#define RTC_ALRMBR_MNU_0                     (0x00000100UL)
+#define RTC_ALRMBR_MNU_1                     (0x00000200UL)
+#define RTC_ALRMBR_MNU_2                     (0x00000400UL)
+#define RTC_ALRMBR_MNU_3                     (0x00000800UL)
+#define RTC_ALRMBR_MSK1                      (0x00000080UL)
+#define RTC_ALRMBR_ST                        (0x00000070UL)
+#define RTC_ALRMBR_ST_0                      (0x00000010UL)
+#define RTC_ALRMBR_ST_1                      (0x00000020UL)
+#define RTC_ALRMBR_ST_2                      (0x00000040UL)
+#define RTC_ALRMBR_SU                        (0x0000000FUL)
+#define RTC_ALRMBR_SU_0                      (0x00000001UL)
+#define RTC_ALRMBR_SU_1                      (0x00000002UL)
+#define RTC_ALRMBR_SU_2                      (0x00000004UL)
+#define RTC_ALRMBR_SU_3                      (0x00000008UL)
 
 /********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY                          ((uint32_t)0x000000FF)
+#define RTC_WPR_KEY                          (0x000000FFUL)
 
 /********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS                           ((uint32_t)0x0000FFFF)
+#define RTC_SSR_SS                           (0x0000FFFFUL)
 
 /********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS                     ((uint32_t)0x00007FFF)
-#define RTC_SHIFTR_ADD1S                     ((uint32_t)0x80000000)
+#define RTC_SHIFTR_SUBFS                     (0x00007FFFUL)
+#define RTC_SHIFTR_ADD1S                     (0x80000000UL)
 
 /********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM                          ((uint32_t)0x00400000)
-#define RTC_TSTR_HT                          ((uint32_t)0x00300000)
-#define RTC_TSTR_HT_0                        ((uint32_t)0x00100000)
-#define RTC_TSTR_HT_1                        ((uint32_t)0x00200000)
-#define RTC_TSTR_HU                          ((uint32_t)0x000F0000)
-#define RTC_TSTR_HU_0                        ((uint32_t)0x00010000)
-#define RTC_TSTR_HU_1                        ((uint32_t)0x00020000)
-#define RTC_TSTR_HU_2                        ((uint32_t)0x00040000)
-#define RTC_TSTR_HU_3                        ((uint32_t)0x00080000)
-#define RTC_TSTR_MNT                         ((uint32_t)0x00007000)
-#define RTC_TSTR_MNT_0                       ((uint32_t)0x00001000)
-#define RTC_TSTR_MNT_1                       ((uint32_t)0x00002000)
-#define RTC_TSTR_MNT_2                       ((uint32_t)0x00004000)
-#define RTC_TSTR_MNU                         ((uint32_t)0x00000F00)
-#define RTC_TSTR_MNU_0                       ((uint32_t)0x00000100)
-#define RTC_TSTR_MNU_1                       ((uint32_t)0x00000200)
-#define RTC_TSTR_MNU_2                       ((uint32_t)0x00000400)
-#define RTC_TSTR_MNU_3                       ((uint32_t)0x00000800)
-#define RTC_TSTR_ST                          ((uint32_t)0x00000070)
-#define RTC_TSTR_ST_0                        ((uint32_t)0x00000010)
-#define RTC_TSTR_ST_1                        ((uint32_t)0x00000020)
-#define RTC_TSTR_ST_2                        ((uint32_t)0x00000040)
-#define RTC_TSTR_SU                          ((uint32_t)0x0000000F)
-#define RTC_TSTR_SU_0                        ((uint32_t)0x00000001)
-#define RTC_TSTR_SU_1                        ((uint32_t)0x00000002)
-#define RTC_TSTR_SU_2                        ((uint32_t)0x00000004)
-#define RTC_TSTR_SU_3                        ((uint32_t)0x00000008)
+#define RTC_TSTR_PM                          (0x00400000UL)
+#define RTC_TSTR_HT                          (0x00300000UL)
+#define RTC_TSTR_HT_0                        (0x00100000UL)
+#define RTC_TSTR_HT_1                        (0x00200000UL)
+#define RTC_TSTR_HU                          (0x000F0000UL)
+#define RTC_TSTR_HU_0                        (0x00010000UL)
+#define RTC_TSTR_HU_1                        (0x00020000UL)
+#define RTC_TSTR_HU_2                        (0x00040000UL)
+#define RTC_TSTR_HU_3                        (0x00080000UL)
+#define RTC_TSTR_MNT                         (0x00007000UL)
+#define RTC_TSTR_MNT_0                       (0x00001000UL)
+#define RTC_TSTR_MNT_1                       (0x00002000UL)
+#define RTC_TSTR_MNT_2                       (0x00004000UL)
+#define RTC_TSTR_MNU                         (0x00000F00UL)
+#define RTC_TSTR_MNU_0                       (0x00000100UL)
+#define RTC_TSTR_MNU_1                       (0x00000200UL)
+#define RTC_TSTR_MNU_2                       (0x00000400UL)
+#define RTC_TSTR_MNU_3                       (0x00000800UL)
+#define RTC_TSTR_ST                          (0x00000070UL)
+#define RTC_TSTR_ST_0                        (0x00000010UL)
+#define RTC_TSTR_ST_1                        (0x00000020UL)
+#define RTC_TSTR_ST_2                        (0x00000040UL)
+#define RTC_TSTR_SU                          (0x0000000FUL)
+#define RTC_TSTR_SU_0                        (0x00000001UL)
+#define RTC_TSTR_SU_1                        (0x00000002UL)
+#define RTC_TSTR_SU_2                        (0x00000004UL)
+#define RTC_TSTR_SU_3                        (0x00000008UL)
 
 /********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU                         ((uint32_t)0x0000E000)
-#define RTC_TSDR_WDU_0                       ((uint32_t)0x00002000)
-#define RTC_TSDR_WDU_1                       ((uint32_t)0x00004000)
-#define RTC_TSDR_WDU_2                       ((uint32_t)0x00008000)
-#define RTC_TSDR_MT                          ((uint32_t)0x00001000)
-#define RTC_TSDR_MU                          ((uint32_t)0x00000F00)
-#define RTC_TSDR_MU_0                        ((uint32_t)0x00000100)
-#define RTC_TSDR_MU_1                        ((uint32_t)0x00000200)
-#define RTC_TSDR_MU_2                        ((uint32_t)0x00000400)
-#define RTC_TSDR_MU_3                        ((uint32_t)0x00000800)
-#define RTC_TSDR_DT                          ((uint32_t)0x00000030)
-#define RTC_TSDR_DT_0                        ((uint32_t)0x00000010)
-#define RTC_TSDR_DT_1                        ((uint32_t)0x00000020)
-#define RTC_TSDR_DU                          ((uint32_t)0x0000000F)
-#define RTC_TSDR_DU_0                        ((uint32_t)0x00000001)
-#define RTC_TSDR_DU_1                        ((uint32_t)0x00000002)
-#define RTC_TSDR_DU_2                        ((uint32_t)0x00000004)
-#define RTC_TSDR_DU_3                        ((uint32_t)0x00000008)
+#define RTC_TSDR_WDU                         (0x0000E000UL)
+#define RTC_TSDR_WDU_0                       (0x00002000UL)
+#define RTC_TSDR_WDU_1                       (0x00004000UL)
+#define RTC_TSDR_WDU_2                       (0x00008000UL)
+#define RTC_TSDR_MT                          (0x00001000UL)
+#define RTC_TSDR_MU                          (0x00000F00UL)
+#define RTC_TSDR_MU_0                        (0x00000100UL)
+#define RTC_TSDR_MU_1                        (0x00000200UL)
+#define RTC_TSDR_MU_2                        (0x00000400UL)
+#define RTC_TSDR_MU_3                        (0x00000800UL)
+#define RTC_TSDR_DT                          (0x00000030UL)
+#define RTC_TSDR_DT_0                        (0x00000010UL)
+#define RTC_TSDR_DT_1                        (0x00000020UL)
+#define RTC_TSDR_DU                          (0x0000000FUL)
+#define RTC_TSDR_DU_0                        (0x00000001UL)
+#define RTC_TSDR_DU_1                        (0x00000002UL)
+#define RTC_TSDR_DU_2                        (0x00000004UL)
+#define RTC_TSDR_DU_3                        (0x00000008UL)
 
 /********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS                         ((uint32_t)0x0000FFFF)
+#define RTC_TSSSR_SS                         (0x0000FFFFUL)
 
 /********************  Bits definition for RTC_CAL register  *****************/
-#define RTC_CALR_CALP                        ((uint32_t)0x00008000)
-#define RTC_CALR_CALW8                       ((uint32_t)0x00004000)
-#define RTC_CALR_CALW16                      ((uint32_t)0x00002000)
-#define RTC_CALR_CALM                        ((uint32_t)0x000001FF)
-#define RTC_CALR_CALM_0                      ((uint32_t)0x00000001)
-#define RTC_CALR_CALM_1                      ((uint32_t)0x00000002)
-#define RTC_CALR_CALM_2                      ((uint32_t)0x00000004)
-#define RTC_CALR_CALM_3                      ((uint32_t)0x00000008)
-#define RTC_CALR_CALM_4                      ((uint32_t)0x00000010)
-#define RTC_CALR_CALM_5                      ((uint32_t)0x00000020)
-#define RTC_CALR_CALM_6                      ((uint32_t)0x00000040)
-#define RTC_CALR_CALM_7                      ((uint32_t)0x00000080)
-#define RTC_CALR_CALM_8                      ((uint32_t)0x00000100)
+#define RTC_CALR_CALP                        (0x00008000UL)
+#define RTC_CALR_CALW8                       (0x00004000UL)
+#define RTC_CALR_CALW16                      (0x00002000UL)
+#define RTC_CALR_CALM                        (0x000001FFUL)
+#define RTC_CALR_CALM_0                      (0x00000001UL)
+#define RTC_CALR_CALM_1                      (0x00000002UL)
+#define RTC_CALR_CALM_2                      (0x00000004UL)
+#define RTC_CALR_CALM_3                      (0x00000008UL)
+#define RTC_CALR_CALM_4                      (0x00000010UL)
+#define RTC_CALR_CALM_5                      (0x00000020UL)
+#define RTC_CALR_CALM_6                      (0x00000040UL)
+#define RTC_CALR_CALM_7                      (0x00000080UL)
+#define RTC_CALR_CALM_8                      (0x00000100UL)
 
 /********************  Bits definition for RTC_TAFCR register  ****************/
-#define RTC_TAFCR_ALARMOUTTYPE               ((uint32_t)0x00040000)
-#define RTC_TAFCR_TSINSEL                    ((uint32_t)0x00020000)
-#define RTC_TAFCR_TAMPINSEL                  ((uint32_t)0x00010000)
-#define RTC_TAFCR_TAMPPUDIS                  ((uint32_t)0x00008000)
-#define RTC_TAFCR_TAMPPRCH                   ((uint32_t)0x00006000)
-#define RTC_TAFCR_TAMPPRCH_0                 ((uint32_t)0x00002000)
-#define RTC_TAFCR_TAMPPRCH_1                 ((uint32_t)0x00004000)
-#define RTC_TAFCR_TAMPFLT                    ((uint32_t)0x00001800)
-#define RTC_TAFCR_TAMPFLT_0                  ((uint32_t)0x00000800)
-#define RTC_TAFCR_TAMPFLT_1                  ((uint32_t)0x00001000)
-#define RTC_TAFCR_TAMPFREQ                   ((uint32_t)0x00000700)
-#define RTC_TAFCR_TAMPFREQ_0                 ((uint32_t)0x00000100)
-#define RTC_TAFCR_TAMPFREQ_1                 ((uint32_t)0x00000200)
-#define RTC_TAFCR_TAMPFREQ_2                 ((uint32_t)0x00000400)
-#define RTC_TAFCR_TAMPTS                     ((uint32_t)0x00000080)
-#define RTC_TAFCR_TAMP2TRG                   ((uint32_t)0x00000010)
-#define RTC_TAFCR_TAMP2E                     ((uint32_t)0x00000008)
-#define RTC_TAFCR_TAMPIE                     ((uint32_t)0x00000004)
-#define RTC_TAFCR_TAMP1TRG                   ((uint32_t)0x00000002)
-#define RTC_TAFCR_TAMP1E                     ((uint32_t)0x00000001)
+#define RTC_TAFCR_ALARMOUTTYPE               (0x00040000UL)
+#define RTC_TAFCR_TSINSEL                    (0x00020000UL)
+#define RTC_TAFCR_TAMPINSEL                  (0x00010000UL)
+#define RTC_TAFCR_TAMPPUDIS                  (0x00008000UL)
+#define RTC_TAFCR_TAMPPRCH                   (0x00006000UL)
+#define RTC_TAFCR_TAMPPRCH_0                 (0x00002000UL)
+#define RTC_TAFCR_TAMPPRCH_1                 (0x00004000UL)
+#define RTC_TAFCR_TAMPFLT                    (0x00001800UL)
+#define RTC_TAFCR_TAMPFLT_0                  (0x00000800UL)
+#define RTC_TAFCR_TAMPFLT_1                  (0x00001000UL)
+#define RTC_TAFCR_TAMPFREQ                   (0x00000700UL)
+#define RTC_TAFCR_TAMPFREQ_0                 (0x00000100UL)
+#define RTC_TAFCR_TAMPFREQ_1                 (0x00000200UL)
+#define RTC_TAFCR_TAMPFREQ_2                 (0x00000400UL)
+#define RTC_TAFCR_TAMPTS                     (0x00000080UL)
+#define RTC_TAFCR_TAMP2TRG                   (0x00000010UL)
+#define RTC_TAFCR_TAMP2E                     (0x00000008UL)
+#define RTC_TAFCR_TAMPIE                     (0x00000004UL)
+#define RTC_TAFCR_TAMP1TRG                   (0x00000002UL)
+#define RTC_TAFCR_TAMP1E                     (0x00000001UL)
 
 /********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS                  ((uint32_t)0x0F000000)
-#define RTC_ALRMASSR_MASKSS_0                ((uint32_t)0x01000000)
-#define RTC_ALRMASSR_MASKSS_1                ((uint32_t)0x02000000)
-#define RTC_ALRMASSR_MASKSS_2                ((uint32_t)0x04000000)
-#define RTC_ALRMASSR_MASKSS_3                ((uint32_t)0x08000000)
-#define RTC_ALRMASSR_SS                      ((uint32_t)0x00007FFF)
+#define RTC_ALRMASSR_MASKSS                  (0x0F000000UL)
+#define RTC_ALRMASSR_MASKSS_0                (0x01000000UL)
+#define RTC_ALRMASSR_MASKSS_1                (0x02000000UL)
+#define RTC_ALRMASSR_MASKSS_2                (0x04000000UL)
+#define RTC_ALRMASSR_MASKSS_3                (0x08000000UL)
+#define RTC_ALRMASSR_SS                      (0x00007FFFUL)
 
 /********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS                  ((uint32_t)0x0F000000)
-#define RTC_ALRMBSSR_MASKSS_0                ((uint32_t)0x01000000)
-#define RTC_ALRMBSSR_MASKSS_1                ((uint32_t)0x02000000)
-#define RTC_ALRMBSSR_MASKSS_2                ((uint32_t)0x04000000)
-#define RTC_ALRMBSSR_MASKSS_3                ((uint32_t)0x08000000)
-#define RTC_ALRMBSSR_SS                      ((uint32_t)0x00007FFF)
+#define RTC_ALRMBSSR_MASKSS                  (0x0F000000UL)
+#define RTC_ALRMBSSR_MASKSS_0                (0x01000000UL)
+#define RTC_ALRMBSSR_MASKSS_1                (0x02000000UL)
+#define RTC_ALRMBSSR_MASKSS_2                (0x04000000UL)
+#define RTC_ALRMBSSR_MASKSS_3                (0x08000000UL)
+#define RTC_ALRMBSSR_SS                      (0x00007FFFUL)
 
 /********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R                            ((uint32_t)0xFFFFFFFF)
+#define RTC_BKP0R                            (0xFFFFFFFFUL)
 
 /********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R                            ((uint32_t)0xFFFFFFFF)
+#define RTC_BKP1R                            (0xFFFFFFFFUL)
 
 /********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R                            ((uint32_t)0xFFFFFFFF)
+#define RTC_BKP2R                            (0xFFFFFFFFUL)
 
 /********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R                            ((uint32_t)0xFFFFFFFF)
+#define RTC_BKP3R                            (0xFFFFFFFFUL)
 
 /********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R                            ((uint32_t)0xFFFFFFFF)
+#define RTC_BKP4R                            (0xFFFFFFFFUL)
 
 /********************  Bits definition for RTC_BKP5R register  ****************/
-#define RTC_BKP5R                            ((uint32_t)0xFFFFFFFF)
+#define RTC_BKP5R                            (0xFFFFFFFFUL)
 
 /********************  Bits definition for RTC_BKP6R register  ****************/
-#define RTC_BKP6R                            ((uint32_t)0xFFFFFFFF)
+#define RTC_BKP6R                            (0xFFFFFFFFUL)
 
 /********************  Bits definition for RTC_BKP7R register  ****************/
-#define RTC_BKP7R                            ((uint32_t)0xFFFFFFFF)
+#define RTC_BKP7R                            (0xFFFFFFFFUL)
 
 /********************  Bits definition for RTC_BKP8R register  ****************/
-#define RTC_BKP8R                            ((uint32_t)0xFFFFFFFF)
+#define RTC_BKP8R                            (0xFFFFFFFFUL)
 
 /********************  Bits definition for RTC_BKP9R register  ****************/
-#define RTC_BKP9R                            ((uint32_t)0xFFFFFFFF)
+#define RTC_BKP9R                            (0xFFFFFFFFUL)
 
 /********************  Bits definition for RTC_BKP10R register  ***************/
-#define RTC_BKP10R                           ((uint32_t)0xFFFFFFFF)
+#define RTC_BKP10R                           (0xFFFFFFFFUL)
 
 /********************  Bits definition for RTC_BKP11R register  ***************/
-#define RTC_BKP11R                           ((uint32_t)0xFFFFFFFF)
+#define RTC_BKP11R                           (0xFFFFFFFFUL)
 
 /********************  Bits definition for RTC_BKP12R register  ***************/
-#define RTC_BKP12R                           ((uint32_t)0xFFFFFFFF)
+#define RTC_BKP12R                           (0xFFFFFFFFUL)
 
 /********************  Bits definition for RTC_BKP13R register  ***************/
-#define RTC_BKP13R                           ((uint32_t)0xFFFFFFFF)
+#define RTC_BKP13R                           (0xFFFFFFFFUL)
 
 /********************  Bits definition for RTC_BKP14R register  ***************/
-#define RTC_BKP14R                           ((uint32_t)0xFFFFFFFF)
+#define RTC_BKP14R                           (0xFFFFFFFFUL)
 
 /********************  Bits definition for RTC_BKP15R register  ***************/
-#define RTC_BKP15R                           ((uint32_t)0xFFFFFFFF)
+#define RTC_BKP15R                           (0xFFFFFFFFUL)
 
 /********************  Bits definition for RTC_BKP16R register  ***************/
-#define RTC_BKP16R                           ((uint32_t)0xFFFFFFFF)
+#define RTC_BKP16R                           (0xFFFFFFFFUL)
 
 /********************  Bits definition for RTC_BKP17R register  ***************/
-#define RTC_BKP17R                           ((uint32_t)0xFFFFFFFF)
+#define RTC_BKP17R                           (0xFFFFFFFFUL)
 
 /********************  Bits definition for RTC_BKP18R register  ***************/
-#define RTC_BKP18R                           ((uint32_t)0xFFFFFFFF)
+#define RTC_BKP18R                           (0xFFFFFFFFUL)
 
 /********************  Bits definition for RTC_BKP19R register  ***************/
-#define RTC_BKP19R                           ((uint32_t)0xFFFFFFFF)
+#define RTC_BKP19R                           (0xFFFFFFFFUL)
 
 
 
@@ -2999,157 +2995,157 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /******************  Bit definition for SDIO_POWER register  ******************/
-#define  SDIO_POWER_PWRCTRL                  ((uint32_t)0x03)               /*!<PWRCTRL[1:0] bits (Power supply control bits) */
-#define  SDIO_POWER_PWRCTRL_0                ((uint32_t)0x01)               /*!<Bit 0 */
-#define  SDIO_POWER_PWRCTRL_1                ((uint32_t)0x02)               /*!<Bit 1 */
+#define  SDIO_POWER_PWRCTRL                  (0x03UL)               /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define  SDIO_POWER_PWRCTRL_0                (0x01UL)               /*!<Bit 0 */
+#define  SDIO_POWER_PWRCTRL_1                (0x02UL)               /*!<Bit 1 */
 
 /******************  Bit definition for SDIO_CLKCR register  ******************/
-#define  SDIO_CLKCR_CLKDIV                   ((uint32_t)0x00FF)            /*!<Clock divide factor             */
-#define  SDIO_CLKCR_CLKEN                    ((uint32_t)0x0100)            /*!<Clock enable bit                */
-#define  SDIO_CLKCR_PWRSAV                   ((uint32_t)0x0200)            /*!<Power saving configuration bit  */
-#define  SDIO_CLKCR_BYPASS                   ((uint32_t)0x0400)            /*!<Clock divider bypass enable bit */
+#define  SDIO_CLKCR_CLKDIV                   (0x00FFUL)            /*!<Clock divide factor             */
+#define  SDIO_CLKCR_CLKEN                    (0x0100UL)            /*!<Clock enable bit                */
+#define  SDIO_CLKCR_PWRSAV                   (0x0200UL)            /*!<Power saving configuration bit  */
+#define  SDIO_CLKCR_BYPASS                   (0x0400UL)            /*!<Clock divider bypass enable bit */
 
-#define  SDIO_CLKCR_WIDBUS                   ((uint32_t)0x1800)            /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
-#define  SDIO_CLKCR_WIDBUS_0                 ((uint32_t)0x0800)            /*!<Bit 0 */
-#define  SDIO_CLKCR_WIDBUS_1                 ((uint32_t)0x1000)            /*!<Bit 1 */
+#define  SDIO_CLKCR_WIDBUS                   (0x1800UL)            /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define  SDIO_CLKCR_WIDBUS_0                 (0x0800UL)            /*!<Bit 0 */
+#define  SDIO_CLKCR_WIDBUS_1                 (0x1000UL)            /*!<Bit 1 */
 
-#define  SDIO_CLKCR_NEGEDGE                  ((uint32_t)0x2000)            /*!<SDIO_CK dephasing selection bit */
-#define  SDIO_CLKCR_HWFC_EN                  ((uint32_t)0x4000)            /*!<HW Flow Control enable          */
+#define  SDIO_CLKCR_NEGEDGE                  (0x2000UL)            /*!<SDIO_CK dephasing selection bit */
+#define  SDIO_CLKCR_HWFC_EN                  (0x4000UL)            /*!<HW Flow Control enable          */
 
 /*******************  Bit definition for SDIO_ARG register  *******************/
-#define  SDIO_ARG_CMDARG                     ((uint32_t)0xFFFFFFFF)            /*!<Command argument */
+#define  SDIO_ARG_CMDARG                     (0xFFFFFFFFUL)            /*!<Command argument */
 
 /*******************  Bit definition for SDIO_CMD register  *******************/
-#define  SDIO_CMD_CMDINDEX                   ((uint32_t)0x003F)            /*!<Command Index                               */
+#define  SDIO_CMD_CMDINDEX                   (0x003FUL)            /*!<Command Index                               */
 
-#define  SDIO_CMD_WAITRESP                   ((uint32_t)0x00C0)            /*!<WAITRESP[1:0] bits (Wait for response bits) */
-#define  SDIO_CMD_WAITRESP_0                 ((uint32_t)0x0040)            /*!< Bit 0 */
-#define  SDIO_CMD_WAITRESP_1                 ((uint32_t)0x0080)            /*!< Bit 1 */
+#define  SDIO_CMD_WAITRESP                   (0x00C0UL)            /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define  SDIO_CMD_WAITRESP_0                 (0x0040UL)            /*!< Bit 0 */
+#define  SDIO_CMD_WAITRESP_1                 (0x0080UL)            /*!< Bit 1 */
 
-#define  SDIO_CMD_WAITINT                    ((uint32_t)0x0100)            /*!<CPSM Waits for Interrupt Request                               */
-#define  SDIO_CMD_WAITPEND                   ((uint32_t)0x0200)            /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
-#define  SDIO_CMD_CPSMEN                     ((uint32_t)0x0400)            /*!<Command path state machine (CPSM) Enable bit                   */
-#define  SDIO_CMD_SDIOSUSPEND                ((uint32_t)0x0800)            /*!<SD I/O suspend command                                         */
-#define  SDIO_CMD_ENCMDCOMPL                 ((uint32_t)0x1000)            /*!<Enable CMD completion                                          */
-#define  SDIO_CMD_NIEN                       ((uint32_t)0x2000)            /*!<Not Interrupt Enable */
-#define  SDIO_CMD_CEATACMD                   ((uint32_t)0x4000)            /*!<CE-ATA command       */
+#define  SDIO_CMD_WAITINT                    (0x0100UL)            /*!<CPSM Waits for Interrupt Request                               */
+#define  SDIO_CMD_WAITPEND                   (0x0200UL)            /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define  SDIO_CMD_CPSMEN                     (0x0400UL)            /*!<Command path state machine (CPSM) Enable bit                   */
+#define  SDIO_CMD_SDIOSUSPEND                (0x0800UL)            /*!<SD I/O suspend command                                         */
+#define  SDIO_CMD_ENCMDCOMPL                 (0x1000UL)            /*!<Enable CMD completion                                          */
+#define  SDIO_CMD_NIEN                       (0x2000UL)            /*!<Not Interrupt Enable */
+#define  SDIO_CMD_CEATACMD                   (0x4000UL)            /*!<CE-ATA command       */
 
 /*****************  Bit definition for SDIO_RESPCMD register  *****************/
-#define  SDIO_RESPCMD_RESPCMD                ((uint32_t)0x3F)               /*!<Response command index */
+#define  SDIO_RESPCMD_RESPCMD                (0x3FUL)               /*!<Response command index */
 
 /******************  Bit definition for SDIO_RESP0 register  ******************/
-#define  SDIO_RESP0_CARDSTATUS0              ((uint32_t)0xFFFFFFFF)        /*!<Card Status */
+#define  SDIO_RESP0_CARDSTATUS0              (0xFFFFFFFFUL)        /*!<Card Status */
 
 /******************  Bit definition for SDIO_RESP1 register  ******************/
-#define  SDIO_RESP1_CARDSTATUS1              ((uint32_t)0xFFFFFFFF)        /*!<Card Status */
+#define  SDIO_RESP1_CARDSTATUS1              (0xFFFFFFFFUL)        /*!<Card Status */
 
 /******************  Bit definition for SDIO_RESP2 register  ******************/
-#define  SDIO_RESP2_CARDSTATUS2              ((uint32_t)0xFFFFFFFF)        /*!<Card Status */
+#define  SDIO_RESP2_CARDSTATUS2              (0xFFFFFFFFUL)        /*!<Card Status */
 
 /******************  Bit definition for SDIO_RESP3 register  ******************/
-#define  SDIO_RESP3_CARDSTATUS3              ((uint32_t)0xFFFFFFFF)        /*!<Card Status */
+#define  SDIO_RESP3_CARDSTATUS3              (0xFFFFFFFFUL)        /*!<Card Status */
 
 /******************  Bit definition for SDIO_RESP4 register  ******************/
-#define  SDIO_RESP4_CARDSTATUS4              ((uint32_t)0xFFFFFFFF)        /*!<Card Status */
+#define  SDIO_RESP4_CARDSTATUS4              (0xFFFFFFFFUL)        /*!<Card Status */
 
 /******************  Bit definition for SDIO_DTIMER register  *****************/
-#define  SDIO_DTIMER_DATATIME                ((uint32_t)0xFFFFFFFF)        /*!<Data timeout period. */
+#define  SDIO_DTIMER_DATATIME                (0xFFFFFFFFUL)        /*!<Data timeout period. */
 
 /******************  Bit definition for SDIO_DLEN register  *******************/
-#define  SDIO_DLEN_DATALENGTH                ((uint32_t)0x01FFFFFF)        /*!<Data length value    */
+#define  SDIO_DLEN_DATALENGTH                (0x01FFFFFFUL)        /*!<Data length value    */
 
 /******************  Bit definition for SDIO_DCTRL register  ******************/
-#define  SDIO_DCTRL_DTEN                     ((uint32_t)0x0001)            /*!<Data transfer enabled bit         */
-#define  SDIO_DCTRL_DTDIR                    ((uint32_t)0x0002)            /*!<Data transfer direction selection */
-#define  SDIO_DCTRL_DTMODE                   ((uint32_t)0x0004)            /*!<Data transfer mode selection      */
-#define  SDIO_DCTRL_DMAEN                    ((uint32_t)0x0008)            /*!<DMA enabled bit                   */
+#define  SDIO_DCTRL_DTEN                     (0x0001UL)            /*!<Data transfer enabled bit         */
+#define  SDIO_DCTRL_DTDIR                    (0x0002UL)            /*!<Data transfer direction selection */
+#define  SDIO_DCTRL_DTMODE                   (0x0004UL)            /*!<Data transfer mode selection      */
+#define  SDIO_DCTRL_DMAEN                    (0x0008UL)            /*!<DMA enabled bit                   */
 
-#define  SDIO_DCTRL_DBLOCKSIZE               ((uint32_t)0x00F0)            /*!<DBLOCKSIZE[3:0] bits (Data block size) */
-#define  SDIO_DCTRL_DBLOCKSIZE_0             ((uint32_t)0x0010)            /*!<Bit 0 */
-#define  SDIO_DCTRL_DBLOCKSIZE_1             ((uint32_t)0x0020)            /*!<Bit 1 */
-#define  SDIO_DCTRL_DBLOCKSIZE_2             ((uint32_t)0x0040)            /*!<Bit 2 */
-#define  SDIO_DCTRL_DBLOCKSIZE_3             ((uint32_t)0x0080)            /*!<Bit 3 */
+#define  SDIO_DCTRL_DBLOCKSIZE               (0x00F0UL)            /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define  SDIO_DCTRL_DBLOCKSIZE_0             (0x0010UL)            /*!<Bit 0 */
+#define  SDIO_DCTRL_DBLOCKSIZE_1             (0x0020UL)            /*!<Bit 1 */
+#define  SDIO_DCTRL_DBLOCKSIZE_2             (0x0040UL)            /*!<Bit 2 */
+#define  SDIO_DCTRL_DBLOCKSIZE_3             (0x0080UL)            /*!<Bit 3 */
 
-#define  SDIO_DCTRL_RWSTART                  ((uint32_t)0x0100)            /*!<Read wait start         */
-#define  SDIO_DCTRL_RWSTOP                   ((uint32_t)0x0200)            /*!<Read wait stop          */
-#define  SDIO_DCTRL_RWMOD                    ((uint32_t)0x0400)            /*!<Read wait mode          */
-#define  SDIO_DCTRL_SDIOEN                   ((uint32_t)0x0800)            /*!<SD I/O enable functions */
+#define  SDIO_DCTRL_RWSTART                  (0x0100UL)            /*!<Read wait start         */
+#define  SDIO_DCTRL_RWSTOP                   (0x0200UL)            /*!<Read wait stop          */
+#define  SDIO_DCTRL_RWMOD                    (0x0400UL)            /*!<Read wait mode          */
+#define  SDIO_DCTRL_SDIOEN                   (0x0800UL)            /*!<SD I/O enable functions */
 
 /******************  Bit definition for SDIO_DCOUNT register  *****************/
-#define  SDIO_DCOUNT_DATACOUNT               ((uint32_t)0x01FFFFFF)        /*!<Data count value */
+#define  SDIO_DCOUNT_DATACOUNT               (0x01FFFFFFUL)        /*!<Data count value */
 
 /******************  Bit definition for SDIO_STA register  ********************/
-#define  SDIO_STA_CCRCFAIL                   ((uint32_t)0x00000001)        /*!<Command response received (CRC check failed)  */
-#define  SDIO_STA_DCRCFAIL                   ((uint32_t)0x00000002)        /*!<Data block sent/received (CRC check failed)   */
-#define  SDIO_STA_CTIMEOUT                   ((uint32_t)0x00000004)        /*!<Command response timeout                      */
-#define  SDIO_STA_DTIMEOUT                   ((uint32_t)0x00000008)        /*!<Data timeout                                  */
-#define  SDIO_STA_TXUNDERR                   ((uint32_t)0x00000010)        /*!<Transmit FIFO underrun error                  */
-#define  SDIO_STA_RXOVERR                    ((uint32_t)0x00000020)        /*!<Received FIFO overrun error                   */
-#define  SDIO_STA_CMDREND                    ((uint32_t)0x00000040)        /*!<Command response received (CRC check passed)  */
-#define  SDIO_STA_CMDSENT                    ((uint32_t)0x00000080)        /*!<Command sent (no response required)           */
-#define  SDIO_STA_DATAEND                    ((uint32_t)0x00000100)        /*!<Data end (data counter, SDIDCOUNT, is zero)   */
-#define  SDIO_STA_STBITERR                   ((uint32_t)0x00000200)        /*!<Start bit not detected on all data signals in wide bus mode */
-#define  SDIO_STA_DBCKEND                    ((uint32_t)0x00000400)        /*!<Data block sent/received (CRC check passed)   */
-#define  SDIO_STA_CMDACT                     ((uint32_t)0x00000800)        /*!<Command transfer in progress                  */
-#define  SDIO_STA_TXACT                      ((uint32_t)0x00001000)        /*!<Data transmit in progress                     */
-#define  SDIO_STA_RXACT                      ((uint32_t)0x00002000)        /*!<Data receive in progress                      */
-#define  SDIO_STA_TXFIFOHE                   ((uint32_t)0x00004000)        /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
-#define  SDIO_STA_RXFIFOHF                   ((uint32_t)0x00008000)        /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
-#define  SDIO_STA_TXFIFOF                    ((uint32_t)0x00010000)        /*!<Transmit FIFO full                            */
-#define  SDIO_STA_RXFIFOF                    ((uint32_t)0x00020000)        /*!<Receive FIFO full                             */
-#define  SDIO_STA_TXFIFOE                    ((uint32_t)0x00040000)        /*!<Transmit FIFO empty                           */
-#define  SDIO_STA_RXFIFOE                    ((uint32_t)0x00080000)        /*!<Receive FIFO empty                            */
-#define  SDIO_STA_TXDAVL                     ((uint32_t)0x00100000)        /*!<Data available in transmit FIFO               */
-#define  SDIO_STA_RXDAVL                     ((uint32_t)0x00200000)        /*!<Data available in receive FIFO                */
-#define  SDIO_STA_SDIOIT                     ((uint32_t)0x00400000)        /*!<SDIO interrupt received                       */
-#define  SDIO_STA_CEATAEND                   ((uint32_t)0x00800000)        /*!<CE-ATA command completion signal received for CMD61 */
+#define  SDIO_STA_CCRCFAIL                   (0x00000001UL)        /*!<Command response received (CRC check failed)  */
+#define  SDIO_STA_DCRCFAIL                   (0x00000002UL)        /*!<Data block sent/received (CRC check failed)   */
+#define  SDIO_STA_CTIMEOUT                   (0x00000004UL)        /*!<Command response timeout                      */
+#define  SDIO_STA_DTIMEOUT                   (0x00000008UL)        /*!<Data timeout                                  */
+#define  SDIO_STA_TXUNDERR                   (0x00000010UL)        /*!<Transmit FIFO underrun error                  */
+#define  SDIO_STA_RXOVERR                    (0x00000020UL)        /*!<Received FIFO overrun error                   */
+#define  SDIO_STA_CMDREND                    (0x00000040UL)        /*!<Command response received (CRC check passed)  */
+#define  SDIO_STA_CMDSENT                    (0x00000080UL)        /*!<Command sent (no response required)           */
+#define  SDIO_STA_DATAEND                    (0x00000100UL)        /*!<Data end (data counter, SDIDCOUNT, is zero)   */
+#define  SDIO_STA_STBITERR                   (0x00000200UL)        /*!<Start bit not detected on all data signals in wide bus mode */
+#define  SDIO_STA_DBCKEND                    (0x00000400UL)        /*!<Data block sent/received (CRC check passed)   */
+#define  SDIO_STA_CMDACT                     (0x00000800UL)        /*!<Command transfer in progress                  */
+#define  SDIO_STA_TXACT                      (0x00001000UL)        /*!<Data transmit in progress                     */
+#define  SDIO_STA_RXACT                      (0x00002000UL)        /*!<Data receive in progress                      */
+#define  SDIO_STA_TXFIFOHE                   (0x00004000UL)        /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define  SDIO_STA_RXFIFOHF                   (0x00008000UL)        /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define  SDIO_STA_TXFIFOF                    (0x00010000UL)        /*!<Transmit FIFO full                            */
+#define  SDIO_STA_RXFIFOF                    (0x00020000UL)        /*!<Receive FIFO full                             */
+#define  SDIO_STA_TXFIFOE                    (0x00040000UL)        /*!<Transmit FIFO empty                           */
+#define  SDIO_STA_RXFIFOE                    (0x00080000UL)        /*!<Receive FIFO empty                            */
+#define  SDIO_STA_TXDAVL                     (0x00100000UL)        /*!<Data available in transmit FIFO               */
+#define  SDIO_STA_RXDAVL                     (0x00200000UL)        /*!<Data available in receive FIFO                */
+#define  SDIO_STA_SDIOIT                     (0x00400000UL)        /*!<SDIO interrupt received                       */
+#define  SDIO_STA_CEATAEND                   (0x00800000UL)        /*!<CE-ATA command completion signal received for CMD61 */
 
 /*******************  Bit definition for SDIO_ICR register  *******************/
-#define  SDIO_ICR_CCRCFAILC                  ((uint32_t)0x00000001)        /*!<CCRCFAIL flag clear bit */
-#define  SDIO_ICR_DCRCFAILC                  ((uint32_t)0x00000002)        /*!<DCRCFAIL flag clear bit */
-#define  SDIO_ICR_CTIMEOUTC                  ((uint32_t)0x00000004)        /*!<CTIMEOUT flag clear bit */
-#define  SDIO_ICR_DTIMEOUTC                  ((uint32_t)0x00000008)        /*!<DTIMEOUT flag clear bit */
-#define  SDIO_ICR_TXUNDERRC                  ((uint32_t)0x00000010)        /*!<TXUNDERR flag clear bit */
-#define  SDIO_ICR_RXOVERRC                   ((uint32_t)0x00000020)        /*!<RXOVERR flag clear bit  */
-#define  SDIO_ICR_CMDRENDC                   ((uint32_t)0x00000040)        /*!<CMDREND flag clear bit  */
-#define  SDIO_ICR_CMDSENTC                   ((uint32_t)0x00000080)        /*!<CMDSENT flag clear bit  */
-#define  SDIO_ICR_DATAENDC                   ((uint32_t)0x00000100)        /*!<DATAEND flag clear bit  */
-#define  SDIO_ICR_STBITERRC                  ((uint32_t)0x00000200)        /*!<STBITERR flag clear bit */
-#define  SDIO_ICR_DBCKENDC                   ((uint32_t)0x00000400)        /*!<DBCKEND flag clear bit  */
-#define  SDIO_ICR_SDIOITC                    ((uint32_t)0x00400000)        /*!<SDIOIT flag clear bit   */
-#define  SDIO_ICR_CEATAENDC                  ((uint32_t)0x00800000)        /*!<CEATAEND flag clear bit */
+#define  SDIO_ICR_CCRCFAILC                  (0x00000001UL)        /*!<CCRCFAIL flag clear bit */
+#define  SDIO_ICR_DCRCFAILC                  (0x00000002UL)        /*!<DCRCFAIL flag clear bit */
+#define  SDIO_ICR_CTIMEOUTC                  (0x00000004UL)        /*!<CTIMEOUT flag clear bit */
+#define  SDIO_ICR_DTIMEOUTC                  (0x00000008UL)        /*!<DTIMEOUT flag clear bit */
+#define  SDIO_ICR_TXUNDERRC                  (0x00000010UL)        /*!<TXUNDERR flag clear bit */
+#define  SDIO_ICR_RXOVERRC                   (0x00000020UL)        /*!<RXOVERR flag clear bit  */
+#define  SDIO_ICR_CMDRENDC                   (0x00000040UL)        /*!<CMDREND flag clear bit  */
+#define  SDIO_ICR_CMDSENTC                   (0x00000080UL)        /*!<CMDSENT flag clear bit  */
+#define  SDIO_ICR_DATAENDC                   (0x00000100UL)        /*!<DATAEND flag clear bit  */
+#define  SDIO_ICR_STBITERRC                  (0x00000200UL)        /*!<STBITERR flag clear bit */
+#define  SDIO_ICR_DBCKENDC                   (0x00000400UL)        /*!<DBCKEND flag clear bit  */
+#define  SDIO_ICR_SDIOITC                    (0x00400000UL)        /*!<SDIOIT flag clear bit   */
+#define  SDIO_ICR_CEATAENDC                  (0x00800000UL)        /*!<CEATAEND flag clear bit */
 
 /******************  Bit definition for SDIO_MASK register  *******************/
-#define  SDIO_MASK_CCRCFAILIE                ((uint32_t)0x00000001)        /*!<Command CRC Fail Interrupt Enable          */
-#define  SDIO_MASK_DCRCFAILIE                ((uint32_t)0x00000002)        /*!<Data CRC Fail Interrupt Enable             */
-#define  SDIO_MASK_CTIMEOUTIE                ((uint32_t)0x00000004)        /*!<Command TimeOut Interrupt Enable           */
-#define  SDIO_MASK_DTIMEOUTIE                ((uint32_t)0x00000008)        /*!<Data TimeOut Interrupt Enable              */
-#define  SDIO_MASK_TXUNDERRIE                ((uint32_t)0x00000010)        /*!<Tx FIFO UnderRun Error Interrupt Enable    */
-#define  SDIO_MASK_RXOVERRIE                 ((uint32_t)0x00000020)        /*!<Rx FIFO OverRun Error Interrupt Enable     */
-#define  SDIO_MASK_CMDRENDIE                 ((uint32_t)0x00000040)        /*!<Command Response Received Interrupt Enable */
-#define  SDIO_MASK_CMDSENTIE                 ((uint32_t)0x00000080)        /*!<Command Sent Interrupt Enable              */
-#define  SDIO_MASK_DATAENDIE                 ((uint32_t)0x00000100)        /*!<Data End Interrupt Enable                  */
-#define  SDIO_MASK_STBITERRIE                ((uint32_t)0x00000200)        /*!<Start Bit Error Interrupt Enable           */
-#define  SDIO_MASK_DBCKENDIE                 ((uint32_t)0x00000400)        /*!<Data Block End Interrupt Enable            */
-#define  SDIO_MASK_CMDACTIE                  ((uint32_t)0x00000800)        /*!<CCommand Acting Interrupt Enable           */
-#define  SDIO_MASK_TXACTIE                   ((uint32_t)0x00001000)        /*!<Data Transmit Acting Interrupt Enable      */
-#define  SDIO_MASK_RXACTIE                   ((uint32_t)0x00002000)        /*!<Data receive acting interrupt enabled      */
-#define  SDIO_MASK_TXFIFOHEIE                ((uint32_t)0x00004000)        /*!<Tx FIFO Half Empty interrupt Enable        */
-#define  SDIO_MASK_RXFIFOHFIE                ((uint32_t)0x00008000)        /*!<Rx FIFO Half Full interrupt Enable         */
-#define  SDIO_MASK_TXFIFOFIE                 ((uint32_t)0x00010000)        /*!<Tx FIFO Full interrupt Enable              */
-#define  SDIO_MASK_RXFIFOFIE                 ((uint32_t)0x00020000)        /*!<Rx FIFO Full interrupt Enable              */
-#define  SDIO_MASK_TXFIFOEIE                 ((uint32_t)0x00040000)        /*!<Tx FIFO Empty interrupt Enable             */
-#define  SDIO_MASK_RXFIFOEIE                 ((uint32_t)0x00080000)        /*!<Rx FIFO Empty interrupt Enable             */
-#define  SDIO_MASK_TXDAVLIE                  ((uint32_t)0x00100000)        /*!<Data available in Tx FIFO interrupt Enable */
-#define  SDIO_MASK_RXDAVLIE                  ((uint32_t)0x00200000)        /*!<Data available in Rx FIFO interrupt Enable */
-#define  SDIO_MASK_SDIOITIE                  ((uint32_t)0x00400000)        /*!<SDIO Mode Interrupt Received interrupt Enable */
-#define  SDIO_MASK_CEATAENDIE                ((uint32_t)0x00800000)        /*!<CE-ATA command completion signal received Interrupt Enable */
+#define  SDIO_MASK_CCRCFAILIE                (0x00000001UL)        /*!<Command CRC Fail Interrupt Enable          */
+#define  SDIO_MASK_DCRCFAILIE                (0x00000002UL)        /*!<Data CRC Fail Interrupt Enable             */
+#define  SDIO_MASK_CTIMEOUTIE                (0x00000004UL)        /*!<Command TimeOut Interrupt Enable           */
+#define  SDIO_MASK_DTIMEOUTIE                (0x00000008UL)        /*!<Data TimeOut Interrupt Enable              */
+#define  SDIO_MASK_TXUNDERRIE                (0x00000010UL)        /*!<Tx FIFO UnderRun Error Interrupt Enable    */
+#define  SDIO_MASK_RXOVERRIE                 (0x00000020UL)        /*!<Rx FIFO OverRun Error Interrupt Enable     */
+#define  SDIO_MASK_CMDRENDIE                 (0x00000040UL)        /*!<Command Response Received Interrupt Enable */
+#define  SDIO_MASK_CMDSENTIE                 (0x00000080UL)        /*!<Command Sent Interrupt Enable              */
+#define  SDIO_MASK_DATAENDIE                 (0x00000100UL)        /*!<Data End Interrupt Enable                  */
+#define  SDIO_MASK_STBITERRIE                (0x00000200UL)        /*!<Start Bit Error Interrupt Enable           */
+#define  SDIO_MASK_DBCKENDIE                 (0x00000400UL)        /*!<Data Block End Interrupt Enable            */
+#define  SDIO_MASK_CMDACTIE                  (0x00000800UL)        /*!<CCommand Acting Interrupt Enable           */
+#define  SDIO_MASK_TXACTIE                   (0x00001000UL)        /*!<Data Transmit Acting Interrupt Enable      */
+#define  SDIO_MASK_RXACTIE                   (0x00002000UL)        /*!<Data receive acting interrupt enabled      */
+#define  SDIO_MASK_TXFIFOHEIE                (0x00004000UL)        /*!<Tx FIFO Half Empty interrupt Enable        */
+#define  SDIO_MASK_RXFIFOHFIE                (0x00008000UL)        /*!<Rx FIFO Half Full interrupt Enable         */
+#define  SDIO_MASK_TXFIFOFIE                 (0x00010000UL)        /*!<Tx FIFO Full interrupt Enable              */
+#define  SDIO_MASK_RXFIFOFIE                 (0x00020000UL)        /*!<Rx FIFO Full interrupt Enable              */
+#define  SDIO_MASK_TXFIFOEIE                 (0x00040000UL)        /*!<Tx FIFO Empty interrupt Enable             */
+#define  SDIO_MASK_RXFIFOEIE                 (0x00080000UL)        /*!<Rx FIFO Empty interrupt Enable             */
+#define  SDIO_MASK_TXDAVLIE                  (0x00100000UL)        /*!<Data available in Tx FIFO interrupt Enable */
+#define  SDIO_MASK_RXDAVLIE                  (0x00200000UL)        /*!<Data available in Rx FIFO interrupt Enable */
+#define  SDIO_MASK_SDIOITIE                  (0x00400000UL)        /*!<SDIO Mode Interrupt Received interrupt Enable */
+#define  SDIO_MASK_CEATAENDIE                (0x00800000UL)        /*!<CE-ATA command completion signal received Interrupt Enable */
 
 /*****************  Bit definition for SDIO_FIFOCNT register  *****************/
-#define  SDIO_FIFOCNT_FIFOCOUNT              ((uint32_t)0x00FFFFFF)        /*!<Remaining number of words to be written to or read from the FIFO */
+#define  SDIO_FIFOCNT_FIFOCOUNT              (0x00FFFFFFUL)        /*!<Remaining number of words to be written to or read from the FIFO */
 
 /******************  Bit definition for SDIO_FIFO register  *******************/
-#define  SDIO_FIFO_FIFODATA                  ((uint32_t)0xFFFFFFFF)        /*!<Receive and transmit FIFO data */
+#define  SDIO_FIFO_FIFODATA                  (0xFFFFFFFFUL)        /*!<Receive and transmit FIFO data */
 
 /******************************************************************************/
 /*                                                                            */
@@ -3157,84 +3153,84 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for SPI_CR1 register  ********************/
-#define  SPI_CR1_CPHA                        ((uint32_t)0x00000001)            /*!<Clock Phase      */
-#define  SPI_CR1_CPOL                        ((uint32_t)0x00000002)            /*!<Clock Polarity   */
-#define  SPI_CR1_MSTR                        ((uint32_t)0x00000004)            /*!<Master Selection */
+#define  SPI_CR1_CPHA                        (0x00000001UL)            /*!<Clock Phase      */
+#define  SPI_CR1_CPOL                        (0x00000002UL)            /*!<Clock Polarity   */
+#define  SPI_CR1_MSTR                        (0x00000004UL)            /*!<Master Selection */
 
-#define  SPI_CR1_BR                          ((uint32_t)0x00000038)            /*!<BR[2:0] bits (Baud Rate Control) */
-#define  SPI_CR1_BR_0                        ((uint32_t)0x00000008)            /*!<Bit 0 */
-#define  SPI_CR1_BR_1                        ((uint32_t)0x00000010)            /*!<Bit 1 */
-#define  SPI_CR1_BR_2                        ((uint32_t)0x00000020)            /*!<Bit 2 */
+#define  SPI_CR1_BR                          (0x00000038UL)            /*!<BR[2:0] bits (Baud Rate Control) */
+#define  SPI_CR1_BR_0                        (0x00000008UL)            /*!<Bit 0 */
+#define  SPI_CR1_BR_1                        (0x00000010UL)            /*!<Bit 1 */
+#define  SPI_CR1_BR_2                        (0x00000020UL)            /*!<Bit 2 */
 
-#define  SPI_CR1_SPE                         ((uint32_t)0x00000040)            /*!<SPI Enable                          */
-#define  SPI_CR1_LSBFIRST                    ((uint32_t)0x00000080)            /*!<Frame Format                        */
-#define  SPI_CR1_SSI                         ((uint32_t)0x00000100)            /*!<Internal slave select               */
-#define  SPI_CR1_SSM                         ((uint32_t)0x00000200)            /*!<Software slave management           */
-#define  SPI_CR1_RXONLY                      ((uint32_t)0x00000400)            /*!<Receive only                        */
-#define  SPI_CR1_DFF                         ((uint32_t)0x00000800)            /*!<Data Frame Format                   */
-#define  SPI_CR1_CRCNEXT                     ((uint32_t)0x00001000)            /*!<Transmit CRC next                   */
-#define  SPI_CR1_CRCEN                       ((uint32_t)0x00002000)            /*!<Hardware CRC calculation enable     */
-#define  SPI_CR1_BIDIOE                      ((uint32_t)0x00004000)            /*!<Output enable in bidirectional mode */
-#define  SPI_CR1_BIDIMODE                    ((uint32_t)0x00008000)            /*!<Bidirectional data mode enable      */
+#define  SPI_CR1_SPE                         (0x00000040UL)            /*!<SPI Enable                          */
+#define  SPI_CR1_LSBFIRST                    (0x00000080UL)            /*!<Frame Format                        */
+#define  SPI_CR1_SSI                         (0x00000100UL)            /*!<Internal slave select               */
+#define  SPI_CR1_SSM                         (0x00000200UL)            /*!<Software slave management           */
+#define  SPI_CR1_RXONLY                      (0x00000400UL)            /*!<Receive only                        */
+#define  SPI_CR1_DFF                         (0x00000800UL)            /*!<Data Frame Format                   */
+#define  SPI_CR1_CRCNEXT                     (0x00001000UL)            /*!<Transmit CRC next                   */
+#define  SPI_CR1_CRCEN                       (0x00002000UL)            /*!<Hardware CRC calculation enable     */
+#define  SPI_CR1_BIDIOE                      (0x00004000UL)            /*!<Output enable in bidirectional mode */
+#define  SPI_CR1_BIDIMODE                    (0x00008000UL)            /*!<Bidirectional data mode enable      */
 
 /*******************  Bit definition for SPI_CR2 register  ********************/
-#define  SPI_CR2_RXDMAEN                     ((uint32_t)0x00000001)               /*!<Rx Buffer DMA Enable                 */
-#define  SPI_CR2_TXDMAEN                     ((uint32_t)0x00000002)               /*!<Tx Buffer DMA Enable                 */
-#define  SPI_CR2_SSOE                        ((uint32_t)0x00000004)               /*!<SS Output Enable                     */
-#define  SPI_CR2_FRF                         ((uint32_t)0x00000010)               /*!<Frame Format                         */
-#define  SPI_CR2_ERRIE                       ((uint32_t)0x00000020)               /*!<Error Interrupt Enable               */
-#define  SPI_CR2_RXNEIE                      ((uint32_t)0x00000040)               /*!<RX buffer Not Empty Interrupt Enable */
-#define  SPI_CR2_TXEIE                       ((uint32_t)0x00000080)               /*!<Tx buffer Empty Interrupt Enable     */
+#define  SPI_CR2_RXDMAEN                     (0x00000001UL)               /*!<Rx Buffer DMA Enable                 */
+#define  SPI_CR2_TXDMAEN                     (0x00000002UL)               /*!<Tx Buffer DMA Enable                 */
+#define  SPI_CR2_SSOE                        (0x00000004UL)               /*!<SS Output Enable                     */
+#define  SPI_CR2_FRF                         (0x00000010UL)               /*!<Frame Format                         */
+#define  SPI_CR2_ERRIE                       (0x00000020UL)               /*!<Error Interrupt Enable               */
+#define  SPI_CR2_RXNEIE                      (0x00000040UL)               /*!<RX buffer Not Empty Interrupt Enable */
+#define  SPI_CR2_TXEIE                       (0x00000080UL)               /*!<Tx buffer Empty Interrupt Enable     */
 
 /********************  Bit definition for SPI_SR register  ********************/
-#define  SPI_SR_RXNE                         ((uint32_t)0x00000001)               /*!<Receive buffer Not Empty */
-#define  SPI_SR_TXE                          ((uint32_t)0x00000002)               /*!<Transmit buffer Empty    */
-#define  SPI_SR_CHSIDE                       ((uint32_t)0x00000004)               /*!<Channel side             */
-#define  SPI_SR_UDR                          ((uint32_t)0x00000008)               /*!<Underrun flag            */
-#define  SPI_SR_CRCERR                       ((uint32_t)0x00000010)               /*!<CRC Error flag           */
-#define  SPI_SR_MODF                         ((uint32_t)0x00000020)               /*!<Mode fault               */
-#define  SPI_SR_OVR                          ((uint32_t)0x00000040)               /*!<Overrun flag             */
-#define  SPI_SR_BSY                          ((uint32_t)0x00000080)               /*!<Busy flag                */
-#define  SPI_SR_FRE                          ((uint32_t)0x00000100)               /*!<Frame format error flag  */
+#define  SPI_SR_RXNE                         (0x00000001UL)               /*!<Receive buffer Not Empty */
+#define  SPI_SR_TXE                          (0x00000002UL)               /*!<Transmit buffer Empty    */
+#define  SPI_SR_CHSIDE                       (0x00000004UL)               /*!<Channel side             */
+#define  SPI_SR_UDR                          (0x00000008UL)               /*!<Underrun flag            */
+#define  SPI_SR_CRCERR                       (0x00000010UL)               /*!<CRC Error flag           */
+#define  SPI_SR_MODF                         (0x00000020UL)               /*!<Mode fault               */
+#define  SPI_SR_OVR                          (0x00000040UL)               /*!<Overrun flag             */
+#define  SPI_SR_BSY                          (0x00000080UL)               /*!<Busy flag                */
+#define  SPI_SR_FRE                          (0x00000100UL)               /*!<Frame format error flag  */
 
 /********************  Bit definition for SPI_DR register  ********************/
-#define  SPI_DR_DR                           ((uint32_t)0x0000FFFF)            /*!<Data Register           */
+#define  SPI_DR_DR                           (0x0000FFFFUL)            /*!<Data Register           */
 
 /*******************  Bit definition for SPI_CRCPR register  ******************/
-#define  SPI_CRCPR_CRCPOLY                   ((uint32_t)0x0000FFFF)            /*!<CRC polynomial register */
+#define  SPI_CRCPR_CRCPOLY                   (0x0000FFFFUL)            /*!<CRC polynomial register */
 
 /******************  Bit definition for SPI_RXCRCR register  ******************/
-#define  SPI_RXCRCR_RXCRC                    ((uint32_t)0x0000FFFF)            /*!<Rx CRC Register         */
+#define  SPI_RXCRCR_RXCRC                    (0x0000FFFFUL)            /*!<Rx CRC Register         */
 
 /******************  Bit definition for SPI_TXCRCR register  ******************/
-#define  SPI_TXCRCR_TXCRC                    ((uint32_t)0x0000FFFF)            /*!<Tx CRC Register         */
+#define  SPI_TXCRCR_TXCRC                    (0x0000FFFFUL)            /*!<Tx CRC Register         */
 
 /******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define  SPI_I2SCFGR_CHLEN                   ((uint32_t)0x00000001)            /*!<Channel length (number of bits per audio channel) */
+#define  SPI_I2SCFGR_CHLEN                   (0x00000001UL)            /*!<Channel length (number of bits per audio channel) */
 
-#define  SPI_I2SCFGR_DATLEN                  ((uint32_t)0x00000006)            /*!<DATLEN[1:0] bits (Data length to be transferred)  */
-#define  SPI_I2SCFGR_DATLEN_0                ((uint32_t)0x00000002)            /*!<Bit 0 */
-#define  SPI_I2SCFGR_DATLEN_1                ((uint32_t)0x00000004)            /*!<Bit 1 */
+#define  SPI_I2SCFGR_DATLEN                  (0x00000006UL)            /*!<DATLEN[1:0] bits (Data length to be transferred)  */
+#define  SPI_I2SCFGR_DATLEN_0                (0x00000002UL)            /*!<Bit 0 */
+#define  SPI_I2SCFGR_DATLEN_1                (0x00000004UL)            /*!<Bit 1 */
 
-#define  SPI_I2SCFGR_CKPOL                   ((uint32_t)0x00000008)            /*!<steady state clock polarity               */
+#define  SPI_I2SCFGR_CKPOL                   (0x00000008UL)            /*!<steady state clock polarity               */
 
-#define  SPI_I2SCFGR_I2SSTD                  ((uint32_t)0x00000030)            /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define  SPI_I2SCFGR_I2SSTD_0                ((uint32_t)0x00000010)            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SSTD_1                ((uint32_t)0x00000020)            /*!<Bit 1 */
+#define  SPI_I2SCFGR_I2SSTD                  (0x00000030UL)            /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define  SPI_I2SCFGR_I2SSTD_0                (0x00000010UL)            /*!<Bit 0 */
+#define  SPI_I2SCFGR_I2SSTD_1                (0x00000020UL)            /*!<Bit 1 */
 
-#define  SPI_I2SCFGR_PCMSYNC                 ((uint32_t)0x00000080)            /*!<PCM frame synchronization                 */
+#define  SPI_I2SCFGR_PCMSYNC                 (0x00000080UL)            /*!<PCM frame synchronization                 */
 
-#define  SPI_I2SCFGR_I2SCFG                  ((uint32_t)0x00000300)            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define  SPI_I2SCFGR_I2SCFG_0                ((uint32_t)0x00000100)            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SCFG_1                ((uint32_t)0x00000200)            /*!<Bit 1 */
+#define  SPI_I2SCFGR_I2SCFG                  (0x00000300UL)            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define  SPI_I2SCFGR_I2SCFG_0                (0x00000100UL)            /*!<Bit 0 */
+#define  SPI_I2SCFGR_I2SCFG_1                (0x00000200UL)            /*!<Bit 1 */
 
-#define  SPI_I2SCFGR_I2SE                    ((uint32_t)0x00000400)            /*!<I2S Enable         */
-#define  SPI_I2SCFGR_I2SMOD                  ((uint32_t)0x00000800)            /*!<I2S mode selection */
+#define  SPI_I2SCFGR_I2SE                    (0x00000400UL)            /*!<I2S Enable         */
+#define  SPI_I2SCFGR_I2SMOD                  (0x00000800UL)            /*!<I2S mode selection */
 
 /******************  Bit definition for SPI_I2SPR register  *******************/
-#define  SPI_I2SPR_I2SDIV                    ((uint32_t)0x000000FF)            /*!<I2S Linear prescaler         */
-#define  SPI_I2SPR_ODD                       ((uint32_t)0x00000100)            /*!<Odd factor for the prescaler */
-#define  SPI_I2SPR_MCKOE                     ((uint32_t)0x00000200)            /*!<Master Clock Output Enable   */
+#define  SPI_I2SPR_I2SDIV                    (0x000000FFUL)            /*!<I2S Linear prescaler         */
+#define  SPI_I2SPR_ODD                       (0x00000100UL)            /*!<Odd factor for the prescaler */
+#define  SPI_I2SPR_MCKOE                     (0x00000200UL)            /*!<Master Clock Output Enable   */
 
 /******************************************************************************/
 /*                                                                            */
@@ -3242,199 +3238,199 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /******************  Bit definition for SYSCFG_MEMRMP register  ***************/
-#define SYSCFG_MEMRMP_MEM_MODE          ((uint32_t)0x00000007) /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_MEMRMP_MEM_MODE_0        ((uint32_t)0x00000001)
-#define SYSCFG_MEMRMP_MEM_MODE_1        ((uint32_t)0x00000002)
-#define SYSCFG_MEMRMP_MEM_MODE_2        ((uint32_t)0x00000004)
+#define SYSCFG_MEMRMP_MEM_MODE          (0x00000007UL) /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0        (0x00000001UL)
+#define SYSCFG_MEMRMP_MEM_MODE_1        (0x00000002UL)
+#define SYSCFG_MEMRMP_MEM_MODE_2        (0x00000004UL)
 
 /******************  Bit definition for SYSCFG_PMC register  ******************/
-#define SYSCFG_PMC_ADC1DC2              ((uint32_t)0x00010000) /*!< Refer to AN4073 on how to use this bit  */
+#define SYSCFG_PMC_ADC1DC2              (0x00010000UL) /*!< Refer to AN4073 on how to use this bit  */
 
 /*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0            ((uint32_t)0x000F) /*!<EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1            ((uint32_t)0x00F0) /*!<EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2            ((uint32_t)0x0F00) /*!<EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3            ((uint32_t)0xF000) /*!<EXTI 3 configuration */
+#define SYSCFG_EXTICR1_EXTI0            (0x000FUL) /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1            (0x00F0UL) /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2            (0x0F00UL) /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3            (0xF000UL) /*!<EXTI 3 configuration */
 /**
   * @brief   EXTI0 configuration
   */
-#define SYSCFG_EXTICR1_EXTI0_PA         ((uint32_t)0x0000) /*!<PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         ((uint32_t)0x0001) /*!<PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         ((uint32_t)0x0002) /*!<PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         ((uint32_t)0x0003) /*!<PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         ((uint32_t)0x0004) /*!<PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         ((uint32_t)0x0007) /*!<PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PA         (0x0000UL) /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB         (0x0001UL) /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC         (0x0002UL) /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD         (0x0003UL) /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE         (0x0004UL) /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH         (0x0007UL) /*!<PH[0] pin */
 
 /**
   * @brief   EXTI1 configuration
   */
-#define SYSCFG_EXTICR1_EXTI1_PA         ((uint32_t)0x0000) /*!<PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         ((uint32_t)0x0010) /*!<PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         ((uint32_t)0x0020) /*!<PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         ((uint32_t)0x0030) /*!<PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         ((uint32_t)0x0040) /*!<PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         ((uint32_t)0x0070) /*!<PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PA         (0x0000UL) /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB         (0x0010UL) /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC         (0x0020UL) /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD         (0x0030UL) /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE         (0x0040UL) /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH         (0x0070UL) /*!<PH[1] pin */
 
 /**
   * @brief   EXTI2 configuration
   */
-#define SYSCFG_EXTICR1_EXTI2_PA         ((uint32_t)0x0000) /*!<PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         ((uint32_t)0x0100) /*!<PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         ((uint32_t)0x0200) /*!<PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         ((uint32_t)0x0300) /*!<PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         ((uint32_t)0x0400) /*!<PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         ((uint32_t)0x0700) /*!<PH[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PA         (0x0000UL) /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB         (0x0100UL) /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC         (0x0200UL) /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD         (0x0300UL) /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE         (0x0400UL) /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH         (0x0700UL) /*!<PH[2] pin */
 
 /**
   * @brief   EXTI3 configuration
   */
-#define SYSCFG_EXTICR1_EXTI3_PA         ((uint32_t)0x0000) /*!<PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         ((uint32_t)0x1000) /*!<PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         ((uint32_t)0x2000) /*!<PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         ((uint32_t)0x3000) /*!<PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         ((uint32_t)0x4000) /*!<PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PH         ((uint32_t)0x7000) /*!<PH[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PA         (0x0000UL) /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB         (0x1000UL) /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC         (0x2000UL) /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD         (0x3000UL) /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE         (0x4000UL) /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH         (0x7000UL) /*!<PH[3] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
-#define SYSCFG_EXTICR2_EXTI4            ((uint32_t)0x000F) /*!<EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5            ((uint32_t)0x00F0) /*!<EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6            ((uint32_t)0x0F00) /*!<EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7            ((uint32_t)0xF000) /*!<EXTI 7 configuration */
+#define SYSCFG_EXTICR2_EXTI4            (0x000FUL) /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5            (0x00F0UL) /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6            (0x0F00UL) /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7            (0xF000UL) /*!<EXTI 7 configuration */
 /**
   * @brief   EXTI4 configuration
   */
-#define SYSCFG_EXTICR2_EXTI4_PA         ((uint32_t)0x0000) /*!<PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         ((uint32_t)0x0001) /*!<PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         ((uint32_t)0x0002) /*!<PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         ((uint32_t)0x0003) /*!<PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         ((uint32_t)0x0004) /*!<PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PH         ((uint32_t)0x0007) /*!<PH[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PA         (0x0000UL) /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB         (0x0001UL) /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC         (0x0002UL) /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD         (0x0003UL) /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE         (0x0004UL) /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH         (0x0007UL) /*!<PH[4] pin */
 
 /**
   * @brief   EXTI5 configuration
   */
-#define SYSCFG_EXTICR2_EXTI5_PA         ((uint32_t)0x0000) /*!<PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         ((uint32_t)0x0010) /*!<PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         ((uint32_t)0x0020) /*!<PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         ((uint32_t)0x0030) /*!<PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         ((uint32_t)0x0040) /*!<PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PH         ((uint32_t)0x0070) /*!<PH[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PA         (0x0000UL) /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB         (0x0010UL) /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC         (0x0020UL) /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD         (0x0030UL) /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE         (0x0040UL) /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH         (0x0070UL) /*!<PH[5] pin */
 
 /**
   * @brief   EXTI6 configuration
   */
-#define SYSCFG_EXTICR2_EXTI6_PA         ((uint32_t)0x0000) /*!<PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         ((uint32_t)0x0100) /*!<PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         ((uint32_t)0x0200) /*!<PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         ((uint32_t)0x0300) /*!<PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         ((uint32_t)0x0400) /*!<PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PH         ((uint32_t)0x0700) /*!<PH[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PA         (0x0000UL) /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB         (0x0100UL) /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC         (0x0200UL) /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD         (0x0300UL) /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE         (0x0400UL) /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH         (0x0700UL) /*!<PH[6] pin */
 
 /**
   * @brief   EXTI7 configuration
   */
-#define SYSCFG_EXTICR2_EXTI7_PA         ((uint32_t)0x0000) /*!<PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         ((uint32_t)0x1000) /*!<PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         ((uint32_t)0x2000) /*!<PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         ((uint32_t)0x3000) /*!<PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         ((uint32_t)0x4000) /*!<PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PH         ((uint32_t)0x7000) /*!<PH[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PA         (0x0000UL) /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB         (0x1000UL) /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC         (0x2000UL) /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD         (0x3000UL) /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE         (0x4000UL) /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH         (0x7000UL) /*!<PH[7] pin */
 
 
 /*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
-#define SYSCFG_EXTICR3_EXTI8            ((uint32_t)0x000F) /*!<EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9            ((uint32_t)0x00F0) /*!<EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10           ((uint32_t)0x0F00) /*!<EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11           ((uint32_t)0xF000) /*!<EXTI 11 configuration */
+#define SYSCFG_EXTICR3_EXTI8            (0x000FUL) /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9            (0x00F0UL) /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10           (0x0F00UL) /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11           (0xF000UL) /*!<EXTI 11 configuration */
 
 /**
   * @brief   EXTI8 configuration
   */
-#define SYSCFG_EXTICR3_EXTI8_PA         ((uint32_t)0x0000) /*!<PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         ((uint32_t)0x0001) /*!<PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         ((uint32_t)0x0002) /*!<PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         ((uint32_t)0x0003) /*!<PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         ((uint32_t)0x0004) /*!<PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PH         ((uint32_t)0x0007) /*!<PH[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PA         (0x0000UL) /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB         (0x0001UL) /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC         (0x0002UL) /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD         (0x0003UL) /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE         (0x0004UL) /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH         (0x0007UL) /*!<PH[8] pin */
 
 /**
   * @brief   EXTI9 configuration
   */
-#define SYSCFG_EXTICR3_EXTI9_PA         ((uint32_t)0x0000) /*!<PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         ((uint32_t)0x0010) /*!<PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         ((uint32_t)0x0020) /*!<PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         ((uint32_t)0x0030) /*!<PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         ((uint32_t)0x0040) /*!<PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PH         ((uint32_t)0x0070) /*!<PH[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PA         (0x0000UL) /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB         (0x0010UL) /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC         (0x0020UL) /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD         (0x0030UL) /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE         (0x0040UL) /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH         (0x0070UL) /*!<PH[9] pin */
 
 /**
   * @brief   EXTI10 configuration
   */
-#define SYSCFG_EXTICR3_EXTI10_PA        ((uint32_t)0x0000) /*!<PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        ((uint32_t)0x0100) /*!<PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        ((uint32_t)0x0200) /*!<PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        ((uint32_t)0x0300) /*!<PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        ((uint32_t)0x0400) /*!<PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PH        ((uint32_t)0x0700) /*!<PH[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PA        (0x0000UL) /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB        (0x0100UL) /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC        (0x0200UL) /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD        (0x0300UL) /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE        (0x0400UL) /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH        (0x0700UL) /*!<PH[10] pin */
 
 /**
   * @brief   EXTI11 configuration
   */
-#define SYSCFG_EXTICR3_EXTI11_PA        ((uint32_t)0x0000) /*!<PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        ((uint32_t)0x1000) /*!<PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        ((uint32_t)0x2000) /*!<PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        ((uint32_t)0x3000) /*!<PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        ((uint32_t)0x4000) /*!<PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PH        ((uint32_t)0x7000) /*!<PH[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PA        (0x0000UL) /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB        (0x1000UL) /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC        (0x2000UL) /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD        (0x3000UL) /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE        (0x4000UL) /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH        (0x7000UL) /*!<PH[11] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
-#define SYSCFG_EXTICR4_EXTI12           ((uint32_t)0x000F) /*!<EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13           ((uint32_t)0x00F0) /*!<EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14           ((uint32_t)0x0F00) /*!<EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15           ((uint32_t)0xF000) /*!<EXTI 15 configuration */
+#define SYSCFG_EXTICR4_EXTI12           (0x000FUL) /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13           (0x00F0UL) /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14           (0x0F00UL) /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15           (0xF000UL) /*!<EXTI 15 configuration */
 /**
   * @brief   EXTI12 configuration
   */
-#define SYSCFG_EXTICR4_EXTI12_PA        ((uint32_t)0x0000) /*!<PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        ((uint32_t)0x0001) /*!<PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        ((uint32_t)0x0002) /*!<PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        ((uint32_t)0x0003) /*!<PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        ((uint32_t)0x0004) /*!<PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PH        ((uint32_t)0x0007) /*!<PH[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PA        (0x0000UL) /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB        (0x0001UL) /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC        (0x0002UL) /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD        (0x0003UL) /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE        (0x0004UL) /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH        (0x0007UL) /*!<PH[12] pin */
 
 /**
   * @brief   EXTI13 configuration
   */
-#define SYSCFG_EXTICR4_EXTI13_PA        ((uint32_t)0x0000) /*!<PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        ((uint32_t)0x0010) /*!<PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        ((uint32_t)0x0020) /*!<PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        ((uint32_t)0x0030) /*!<PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        ((uint32_t)0x0040) /*!<PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PH        ((uint32_t)0x0070) /*!<PH[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PA        (0x0000UL) /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB        (0x0010UL) /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC        (0x0020UL) /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD        (0x0030UL) /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE        (0x0040UL) /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH        (0x0070UL) /*!<PH[13] pin */
 
 /**
   * @brief   EXTI14 configuration
   */
-#define SYSCFG_EXTICR4_EXTI14_PA        ((uint32_t)0x0000) /*!<PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        ((uint32_t)0x0100) /*!<PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        ((uint32_t)0x0200) /*!<PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        ((uint32_t)0x0300) /*!<PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        ((uint32_t)0x0400) /*!<PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PH        ((uint32_t)0x0700) /*!<PH[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PA        (0x0000UL) /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB        (0x0100UL) /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC        (0x0200UL) /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD        (0x0300UL) /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE        (0x0400UL) /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH        (0x0700UL) /*!<PH[14] pin */
 
 /**
   * @brief   EXTI15 configuration
   */
-#define SYSCFG_EXTICR4_EXTI15_PA        ((uint32_t)0x0000) /*!<PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        ((uint32_t)0x1000) /*!<PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        ((uint32_t)0x2000) /*!<PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        ((uint32_t)0x3000) /*!<PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        ((uint32_t)0x4000) /*!<PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PH        ((uint32_t)0x7000) /*!<PH[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PA        (0x0000UL) /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB        (0x1000UL) /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC        (0x2000UL) /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD        (0x3000UL) /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE        (0x4000UL) /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH        (0x7000UL) /*!<PH[15] pin */
 
 /******************  Bit definition for SYSCFG_CMPCR register  ****************/
-#define SYSCFG_CMPCR_CMP_PD             ((uint32_t)0x00000001) /*!<Compensation cell ready flag */
-#define SYSCFG_CMPCR_READY              ((uint32_t)0x00000100) /*!<Compensation cell power-down */
+#define SYSCFG_CMPCR_CMP_PD             (0x00000001UL) /*!<Compensation cell ready flag */
+#define SYSCFG_CMPCR_READY              (0x00000100UL) /*!<Compensation cell power-down */
 
 /******************************************************************************/
 /*                                                                            */
@@ -3442,298 +3438,298 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for TIM_CR1 register  ********************/
-#define  TIM_CR1_CEN                         ((uint32_t)0x0001)            /*!<Counter enable        */
-#define  TIM_CR1_UDIS                        ((uint32_t)0x0002)            /*!<Update disable        */
-#define  TIM_CR1_URS                         ((uint32_t)0x0004)            /*!<Update request source */
-#define  TIM_CR1_OPM                         ((uint32_t)0x0008)            /*!<One pulse mode        */
-#define  TIM_CR1_DIR                         ((uint32_t)0x0010)            /*!<Direction             */
+#define  TIM_CR1_CEN                         (0x0001UL)            /*!<Counter enable        */
+#define  TIM_CR1_UDIS                        (0x0002UL)            /*!<Update disable        */
+#define  TIM_CR1_URS                         (0x0004UL)            /*!<Update request source */
+#define  TIM_CR1_OPM                         (0x0008UL)            /*!<One pulse mode        */
+#define  TIM_CR1_DIR                         (0x0010UL)            /*!<Direction             */
 
-#define  TIM_CR1_CMS                         ((uint32_t)0x0060)            /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define  TIM_CR1_CMS_0                       ((uint32_t)0x0020)            /*!<Bit 0 */
-#define  TIM_CR1_CMS_1                       ((uint32_t)0x0040)            /*!<Bit 1 */
+#define  TIM_CR1_CMS                         (0x0060UL)            /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define  TIM_CR1_CMS_0                       (0x0020UL)            /*!<Bit 0 */
+#define  TIM_CR1_CMS_1                       (0x0040UL)            /*!<Bit 1 */
 
-#define  TIM_CR1_ARPE                        ((uint32_t)0x0080)            /*!<Auto-reload preload enable     */
+#define  TIM_CR1_ARPE                        (0x0080UL)            /*!<Auto-reload preload enable     */
 
-#define  TIM_CR1_CKD                         ((uint32_t)0x0300)            /*!<CKD[1:0] bits (clock division) */
-#define  TIM_CR1_CKD_0                       ((uint32_t)0x0100)            /*!<Bit 0 */
-#define  TIM_CR1_CKD_1                       ((uint32_t)0x0200)            /*!<Bit 1 */
+#define  TIM_CR1_CKD                         (0x0300UL)            /*!<CKD[1:0] bits (clock division) */
+#define  TIM_CR1_CKD_0                       (0x0100UL)            /*!<Bit 0 */
+#define  TIM_CR1_CKD_1                       (0x0200UL)            /*!<Bit 1 */
 
 /*******************  Bit definition for TIM_CR2 register  ********************/
-#define  TIM_CR2_CCPC                        ((uint32_t)0x0001)            /*!<Capture/Compare Preloaded Control        */
-#define  TIM_CR2_CCUS                        ((uint32_t)0x0004)            /*!<Capture/Compare Control Update Selection */
-#define  TIM_CR2_CCDS                        ((uint32_t)0x0008)            /*!<Capture/Compare DMA Selection            */
+#define  TIM_CR2_CCPC                        (0x0001UL)            /*!<Capture/Compare Preloaded Control        */
+#define  TIM_CR2_CCUS                        (0x0004UL)            /*!<Capture/Compare Control Update Selection */
+#define  TIM_CR2_CCDS                        (0x0008UL)            /*!<Capture/Compare DMA Selection            */
 
-#define  TIM_CR2_MMS                         ((uint32_t)0x0070)            /*!<MMS[2:0] bits (Master Mode Selection) */
-#define  TIM_CR2_MMS_0                       ((uint32_t)0x0010)            /*!<Bit 0 */
-#define  TIM_CR2_MMS_1                       ((uint32_t)0x0020)            /*!<Bit 1 */
-#define  TIM_CR2_MMS_2                       ((uint32_t)0x0040)            /*!<Bit 2 */
+#define  TIM_CR2_MMS                         (0x0070UL)            /*!<MMS[2:0] bits (Master Mode Selection) */
+#define  TIM_CR2_MMS_0                       (0x0010UL)            /*!<Bit 0 */
+#define  TIM_CR2_MMS_1                       (0x0020UL)            /*!<Bit 1 */
+#define  TIM_CR2_MMS_2                       (0x0040UL)            /*!<Bit 2 */
 
-#define  TIM_CR2_TI1S                        ((uint32_t)0x0080)            /*!<TI1 Selection */
-#define  TIM_CR2_OIS1                        ((uint32_t)0x0100)            /*!<Output Idle state 1 (OC1 output)  */
-#define  TIM_CR2_OIS1N                       ((uint32_t)0x0200)            /*!<Output Idle state 1 (OC1N output) */
-#define  TIM_CR2_OIS2                        ((uint32_t)0x0400)            /*!<Output Idle state 2 (OC2 output)  */
-#define  TIM_CR2_OIS2N                       ((uint32_t)0x0800)            /*!<Output Idle state 2 (OC2N output) */
-#define  TIM_CR2_OIS3                        ((uint32_t)0x1000)            /*!<Output Idle state 3 (OC3 output)  */
-#define  TIM_CR2_OIS3N                       ((uint32_t)0x2000)            /*!<Output Idle state 3 (OC3N output) */
-#define  TIM_CR2_OIS4                        ((uint32_t)0x4000)            /*!<Output Idle state 4 (OC4 output)  */
+#define  TIM_CR2_TI1S                        (0x0080UL)            /*!<TI1 Selection */
+#define  TIM_CR2_OIS1                        (0x0100UL)            /*!<Output Idle state 1 (OC1 output)  */
+#define  TIM_CR2_OIS1N                       (0x0200UL)            /*!<Output Idle state 1 (OC1N output) */
+#define  TIM_CR2_OIS2                        (0x0400UL)            /*!<Output Idle state 2 (OC2 output)  */
+#define  TIM_CR2_OIS2N                       (0x0800UL)            /*!<Output Idle state 2 (OC2N output) */
+#define  TIM_CR2_OIS3                        (0x1000UL)            /*!<Output Idle state 3 (OC3 output)  */
+#define  TIM_CR2_OIS3N                       (0x2000UL)            /*!<Output Idle state 3 (OC3N output) */
+#define  TIM_CR2_OIS4                        (0x4000UL)            /*!<Output Idle state 4 (OC4 output)  */
 
 /*******************  Bit definition for TIM_SMCR register  *******************/
-#define  TIM_SMCR_SMS                        ((uint32_t)0x0007)            /*!<SMS[2:0] bits (Slave mode selection)    */
-#define  TIM_SMCR_SMS_0                      ((uint32_t)0x0001)            /*!<Bit 0 */
-#define  TIM_SMCR_SMS_1                      ((uint32_t)0x0002)            /*!<Bit 1 */
-#define  TIM_SMCR_SMS_2                      ((uint32_t)0x0004)            /*!<Bit 2 */
+#define  TIM_SMCR_SMS                        (0x0007UL)            /*!<SMS[2:0] bits (Slave mode selection)    */
+#define  TIM_SMCR_SMS_0                      (0x0001UL)            /*!<Bit 0 */
+#define  TIM_SMCR_SMS_1                      (0x0002UL)            /*!<Bit 1 */
+#define  TIM_SMCR_SMS_2                      (0x0004UL)            /*!<Bit 2 */
 
-#define  TIM_SMCR_TS                         ((uint32_t)0x0070)            /*!<TS[2:0] bits (Trigger selection)        */
-#define  TIM_SMCR_TS_0                       ((uint32_t)0x0010)            /*!<Bit 0 */
-#define  TIM_SMCR_TS_1                       ((uint32_t)0x0020)            /*!<Bit 1 */
-#define  TIM_SMCR_TS_2                       ((uint32_t)0x0040)            /*!<Bit 2 */
+#define  TIM_SMCR_TS                         (0x0070UL)            /*!<TS[2:0] bits (Trigger selection)        */
+#define  TIM_SMCR_TS_0                       (0x0010UL)            /*!<Bit 0 */
+#define  TIM_SMCR_TS_1                       (0x0020UL)            /*!<Bit 1 */
+#define  TIM_SMCR_TS_2                       (0x0040UL)            /*!<Bit 2 */
 
-#define  TIM_SMCR_MSM                        ((uint32_t)0x0080)            /*!<Master/slave mode                       */
+#define  TIM_SMCR_MSM                        (0x0080UL)            /*!<Master/slave mode                       */
 
-#define  TIM_SMCR_ETF                        ((uint32_t)0x0F00)            /*!<ETF[3:0] bits (External trigger filter) */
-#define  TIM_SMCR_ETF_0                      ((uint32_t)0x0100)            /*!<Bit 0 */
-#define  TIM_SMCR_ETF_1                      ((uint32_t)0x0200)            /*!<Bit 1 */
-#define  TIM_SMCR_ETF_2                      ((uint32_t)0x0400)            /*!<Bit 2 */
-#define  TIM_SMCR_ETF_3                      ((uint32_t)0x0800)            /*!<Bit 3 */
+#define  TIM_SMCR_ETF                        (0x0F00UL)            /*!<ETF[3:0] bits (External trigger filter) */
+#define  TIM_SMCR_ETF_0                      (0x0100UL)            /*!<Bit 0 */
+#define  TIM_SMCR_ETF_1                      (0x0200UL)            /*!<Bit 1 */
+#define  TIM_SMCR_ETF_2                      (0x0400UL)            /*!<Bit 2 */
+#define  TIM_SMCR_ETF_3                      (0x0800UL)            /*!<Bit 3 */
 
-#define  TIM_SMCR_ETPS                       ((uint32_t)0x3000)            /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define  TIM_SMCR_ETPS_0                     ((uint32_t)0x1000)            /*!<Bit 0 */
-#define  TIM_SMCR_ETPS_1                     ((uint32_t)0x2000)            /*!<Bit 1 */
+#define  TIM_SMCR_ETPS                       (0x3000UL)            /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define  TIM_SMCR_ETPS_0                     (0x1000UL)            /*!<Bit 0 */
+#define  TIM_SMCR_ETPS_1                     (0x2000UL)            /*!<Bit 1 */
 
-#define  TIM_SMCR_ECE                        ((uint32_t)0x4000)            /*!<External clock enable     */
-#define  TIM_SMCR_ETP                        ((uint32_t)0x8000)            /*!<External trigger polarity */
+#define  TIM_SMCR_ECE                        (0x4000UL)            /*!<External clock enable     */
+#define  TIM_SMCR_ETP                        (0x8000UL)            /*!<External trigger polarity */
 
 /*******************  Bit definition for TIM_DIER register  *******************/
-#define  TIM_DIER_UIE                        ((uint32_t)0x0001)            /*!<Update interrupt enable */
-#define  TIM_DIER_CC1IE                      ((uint32_t)0x0002)            /*!<Capture/Compare 1 interrupt enable   */
-#define  TIM_DIER_CC2IE                      ((uint32_t)0x0004)            /*!<Capture/Compare 2 interrupt enable   */
-#define  TIM_DIER_CC3IE                      ((uint32_t)0x0008)            /*!<Capture/Compare 3 interrupt enable   */
-#define  TIM_DIER_CC4IE                      ((uint32_t)0x0010)            /*!<Capture/Compare 4 interrupt enable   */
-#define  TIM_DIER_COMIE                      ((uint32_t)0x0020)            /*!<COM interrupt enable                 */
-#define  TIM_DIER_TIE                        ((uint32_t)0x0040)            /*!<Trigger interrupt enable             */
-#define  TIM_DIER_BIE                        ((uint32_t)0x0080)            /*!<Break interrupt enable               */
-#define  TIM_DIER_UDE                        ((uint32_t)0x0100)            /*!<Update DMA request enable            */
-#define  TIM_DIER_CC1DE                      ((uint32_t)0x0200)            /*!<Capture/Compare 1 DMA request enable */
-#define  TIM_DIER_CC2DE                      ((uint32_t)0x0400)            /*!<Capture/Compare 2 DMA request enable */
-#define  TIM_DIER_CC3DE                      ((uint32_t)0x0800)            /*!<Capture/Compare 3 DMA request enable */
-#define  TIM_DIER_CC4DE                      ((uint32_t)0x1000)            /*!<Capture/Compare 4 DMA request enable */
-#define  TIM_DIER_COMDE                      ((uint32_t)0x2000)            /*!<COM DMA request enable               */
-#define  TIM_DIER_TDE                        ((uint32_t)0x4000)            /*!<Trigger DMA request enable           */
+#define  TIM_DIER_UIE                        (0x0001UL)            /*!<Update interrupt enable */
+#define  TIM_DIER_CC1IE                      (0x0002UL)            /*!<Capture/Compare 1 interrupt enable   */
+#define  TIM_DIER_CC2IE                      (0x0004UL)            /*!<Capture/Compare 2 interrupt enable   */
+#define  TIM_DIER_CC3IE                      (0x0008UL)            /*!<Capture/Compare 3 interrupt enable   */
+#define  TIM_DIER_CC4IE                      (0x0010UL)            /*!<Capture/Compare 4 interrupt enable   */
+#define  TIM_DIER_COMIE                      (0x0020UL)            /*!<COM interrupt enable                 */
+#define  TIM_DIER_TIE                        (0x0040UL)            /*!<Trigger interrupt enable             */
+#define  TIM_DIER_BIE                        (0x0080UL)            /*!<Break interrupt enable               */
+#define  TIM_DIER_UDE                        (0x0100UL)            /*!<Update DMA request enable            */
+#define  TIM_DIER_CC1DE                      (0x0200UL)            /*!<Capture/Compare 1 DMA request enable */
+#define  TIM_DIER_CC2DE                      (0x0400UL)            /*!<Capture/Compare 2 DMA request enable */
+#define  TIM_DIER_CC3DE                      (0x0800UL)            /*!<Capture/Compare 3 DMA request enable */
+#define  TIM_DIER_CC4DE                      (0x1000UL)            /*!<Capture/Compare 4 DMA request enable */
+#define  TIM_DIER_COMDE                      (0x2000UL)            /*!<COM DMA request enable               */
+#define  TIM_DIER_TDE                        (0x4000UL)            /*!<Trigger DMA request enable           */
 
 /********************  Bit definition for TIM_SR register  ********************/
-#define  TIM_SR_UIF                          ((uint32_t)0x0001)            /*!<Update interrupt Flag              */
-#define  TIM_SR_CC1IF                        ((uint32_t)0x0002)            /*!<Capture/Compare 1 interrupt Flag   */
-#define  TIM_SR_CC2IF                        ((uint32_t)0x0004)            /*!<Capture/Compare 2 interrupt Flag   */
-#define  TIM_SR_CC3IF                        ((uint32_t)0x0008)            /*!<Capture/Compare 3 interrupt Flag   */
-#define  TIM_SR_CC4IF                        ((uint32_t)0x0010)            /*!<Capture/Compare 4 interrupt Flag   */
-#define  TIM_SR_COMIF                        ((uint32_t)0x0020)            /*!<COM interrupt Flag                 */
-#define  TIM_SR_TIF                          ((uint32_t)0x0040)            /*!<Trigger interrupt Flag             */
-#define  TIM_SR_BIF                          ((uint32_t)0x0080)            /*!<Break interrupt Flag               */
-#define  TIM_SR_CC1OF                        ((uint32_t)0x0200)            /*!<Capture/Compare 1 Overcapture Flag */
-#define  TIM_SR_CC2OF                        ((uint32_t)0x0400)            /*!<Capture/Compare 2 Overcapture Flag */
-#define  TIM_SR_CC3OF                        ((uint32_t)0x0800)            /*!<Capture/Compare 3 Overcapture Flag */
-#define  TIM_SR_CC4OF                        ((uint32_t)0x1000)            /*!<Capture/Compare 4 Overcapture Flag */
+#define  TIM_SR_UIF                          (0x0001UL)            /*!<Update interrupt Flag              */
+#define  TIM_SR_CC1IF                        (0x0002UL)            /*!<Capture/Compare 1 interrupt Flag   */
+#define  TIM_SR_CC2IF                        (0x0004UL)            /*!<Capture/Compare 2 interrupt Flag   */
+#define  TIM_SR_CC3IF                        (0x0008UL)            /*!<Capture/Compare 3 interrupt Flag   */
+#define  TIM_SR_CC4IF                        (0x0010UL)            /*!<Capture/Compare 4 interrupt Flag   */
+#define  TIM_SR_COMIF                        (0x0020UL)            /*!<COM interrupt Flag                 */
+#define  TIM_SR_TIF                          (0x0040UL)            /*!<Trigger interrupt Flag             */
+#define  TIM_SR_BIF                          (0x0080UL)            /*!<Break interrupt Flag               */
+#define  TIM_SR_CC1OF                        (0x0200UL)            /*!<Capture/Compare 1 Overcapture Flag */
+#define  TIM_SR_CC2OF                        (0x0400UL)            /*!<Capture/Compare 2 Overcapture Flag */
+#define  TIM_SR_CC3OF                        (0x0800UL)            /*!<Capture/Compare 3 Overcapture Flag */
+#define  TIM_SR_CC4OF                        (0x1000UL)            /*!<Capture/Compare 4 Overcapture Flag */
 
 /*******************  Bit definition for TIM_EGR register  ********************/
-#define  TIM_EGR_UG                          ((uint32_t)0x01)               /*!<Update Generation                         */
-#define  TIM_EGR_CC1G                        ((uint32_t)0x02)               /*!<Capture/Compare 1 Generation              */
-#define  TIM_EGR_CC2G                        ((uint32_t)0x04)               /*!<Capture/Compare 2 Generation              */
-#define  TIM_EGR_CC3G                        ((uint32_t)0x08)               /*!<Capture/Compare 3 Generation              */
-#define  TIM_EGR_CC4G                        ((uint32_t)0x10)               /*!<Capture/Compare 4 Generation              */
-#define  TIM_EGR_COMG                        ((uint32_t)0x20)               /*!<Capture/Compare Control Update Generation */
-#define  TIM_EGR_TG                          ((uint32_t)0x40)               /*!<Trigger Generation                        */
-#define  TIM_EGR_BG                          ((uint32_t)0x80)               /*!<Break Generation                          */
+#define  TIM_EGR_UG                          (0x01UL)               /*!<Update Generation                         */
+#define  TIM_EGR_CC1G                        (0x02UL)               /*!<Capture/Compare 1 Generation              */
+#define  TIM_EGR_CC2G                        (0x04UL)               /*!<Capture/Compare 2 Generation              */
+#define  TIM_EGR_CC3G                        (0x08UL)               /*!<Capture/Compare 3 Generation              */
+#define  TIM_EGR_CC4G                        (0x10UL)               /*!<Capture/Compare 4 Generation              */
+#define  TIM_EGR_COMG                        (0x20UL)               /*!<Capture/Compare Control Update Generation */
+#define  TIM_EGR_TG                          (0x40UL)               /*!<Trigger Generation                        */
+#define  TIM_EGR_BG                          (0x80UL)               /*!<Break Generation                          */
 
 /******************  Bit definition for TIM_CCMR1 register  *******************/
-#define  TIM_CCMR1_CC1S                      ((uint32_t)0x0003)            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define  TIM_CCMR1_CC1S_0                    ((uint32_t)0x0001)            /*!<Bit 0 */
-#define  TIM_CCMR1_CC1S_1                    ((uint32_t)0x0002)            /*!<Bit 1 */
+#define  TIM_CCMR1_CC1S                      (0x0003UL)            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define  TIM_CCMR1_CC1S_0                    (0x0001UL)            /*!<Bit 0 */
+#define  TIM_CCMR1_CC1S_1                    (0x0002UL)            /*!<Bit 1 */
 
-#define  TIM_CCMR1_OC1FE                     ((uint32_t)0x0004)            /*!<Output Compare 1 Fast enable                 */
-#define  TIM_CCMR1_OC1PE                     ((uint32_t)0x0008)            /*!<Output Compare 1 Preload enable              */
+#define  TIM_CCMR1_OC1FE                     (0x0004UL)            /*!<Output Compare 1 Fast enable                 */
+#define  TIM_CCMR1_OC1PE                     (0x0008UL)            /*!<Output Compare 1 Preload enable              */
 
-#define  TIM_CCMR1_OC1M                      ((uint32_t)0x0070)            /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */
-#define  TIM_CCMR1_OC1M_0                    ((uint32_t)0x0010)            /*!<Bit 0 */
-#define  TIM_CCMR1_OC1M_1                    ((uint32_t)0x0020)            /*!<Bit 1 */
-#define  TIM_CCMR1_OC1M_2                    ((uint32_t)0x0040)            /*!<Bit 2 */
+#define  TIM_CCMR1_OC1M                      (0x0070UL)            /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */
+#define  TIM_CCMR1_OC1M_0                    (0x0010UL)            /*!<Bit 0 */
+#define  TIM_CCMR1_OC1M_1                    (0x0020UL)            /*!<Bit 1 */
+#define  TIM_CCMR1_OC1M_2                    (0x0040UL)            /*!<Bit 2 */
 
-#define  TIM_CCMR1_OC1CE                     ((uint32_t)0x0080)            /*!<Output Compare 1Clear Enable                 */
+#define  TIM_CCMR1_OC1CE                     (0x0080UL)            /*!<Output Compare 1Clear Enable                 */
 
-#define  TIM_CCMR1_CC2S                      ((uint32_t)0x0300)            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define  TIM_CCMR1_CC2S_0                    ((uint32_t)0x0100)            /*!<Bit 0 */
-#define  TIM_CCMR1_CC2S_1                    ((uint32_t)0x0200)            /*!<Bit 1 */
+#define  TIM_CCMR1_CC2S                      (0x0300UL)            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define  TIM_CCMR1_CC2S_0                    (0x0100UL)            /*!<Bit 0 */
+#define  TIM_CCMR1_CC2S_1                    (0x0200UL)            /*!<Bit 1 */
 
-#define  TIM_CCMR1_OC2FE                     ((uint32_t)0x0400)            /*!<Output Compare 2 Fast enable                 */
-#define  TIM_CCMR1_OC2PE                     ((uint32_t)0x0800)            /*!<Output Compare 2 Preload enable              */
+#define  TIM_CCMR1_OC2FE                     (0x0400UL)            /*!<Output Compare 2 Fast enable                 */
+#define  TIM_CCMR1_OC2PE                     (0x0800UL)            /*!<Output Compare 2 Preload enable              */
 
-#define  TIM_CCMR1_OC2M                      ((uint32_t)0x7000)            /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */
-#define  TIM_CCMR1_OC2M_0                    ((uint32_t)0x1000)            /*!<Bit 0 */
-#define  TIM_CCMR1_OC2M_1                    ((uint32_t)0x2000)            /*!<Bit 1 */
-#define  TIM_CCMR1_OC2M_2                    ((uint32_t)0x4000)            /*!<Bit 2 */
+#define  TIM_CCMR1_OC2M                      (0x7000UL)            /*!<OC2M[2:0] bits (Output Compare 2 Mode3       */
+#define  TIM_CCMR1_OC2M_0                    (0x1000UL)            /*!<Bit 0 */
+#define  TIM_CCMR1_OC2M_1                    (0x2000UL)            /*!<Bit 1 */
+#define  TIM_CCMR1_OC2M_2                    (0x4000UL)            /*!<Bit 2 */
 
-#define  TIM_CCMR1_OC2CE                     ((uint32_t)0x8000)            /*!<Output Compare 2 Clear Enable */
+#define  TIM_CCMR1_OC2CE                     (0x8000UL)            /*!<Output Compare 2 Clear Enable */
 
 /*----------------------------------------------------------------------------*/
 
-#define  TIM_CCMR1_IC1PSC                    ((uint32_t)0x000C)            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define  TIM_CCMR1_IC1PSC_0                  ((uint32_t)0x0004)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1PSC_1                  ((uint32_t)0x0008)            /*!<Bit 1 */
+#define  TIM_CCMR1_IC1PSC                    (0x000CUL)            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define  TIM_CCMR1_IC1PSC_0                  (0x0004UL)            /*!<Bit 0 */
+#define  TIM_CCMR1_IC1PSC_1                  (0x0008UL)            /*!<Bit 1 */
 
-#define  TIM_CCMR1_IC1F                      ((uint32_t)0x00F0)            /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */
-#define  TIM_CCMR1_IC1F_0                    ((uint32_t)0x0010)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1F_1                    ((uint32_t)0x0020)            /*!<Bit 1 */
-#define  TIM_CCMR1_IC1F_2                    ((uint32_t)0x0040)            /*!<Bit 2 */
-#define  TIM_CCMR1_IC1F_3                    ((uint32_t)0x0080)            /*!<Bit 3 */
+#define  TIM_CCMR1_IC1F                      (0x00F0UL)            /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */
+#define  TIM_CCMR1_IC1F_0                    (0x0010UL)            /*!<Bit 0 */
+#define  TIM_CCMR1_IC1F_1                    (0x0020UL)            /*!<Bit 1 */
+#define  TIM_CCMR1_IC1F_2                    (0x0040UL)            /*!<Bit 2 */
+#define  TIM_CCMR1_IC1F_3                    (0x0080UL)            /*!<Bit 3 */
 
-#define  TIM_CCMR1_IC2PSC                    ((uint32_t)0x0C00)            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */
-#define  TIM_CCMR1_IC2PSC_0                  ((uint32_t)0x0400)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2PSC_1                  ((uint32_t)0x0800)            /*!<Bit 1 */
+#define  TIM_CCMR1_IC2PSC                    (0x0C00UL)            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */
+#define  TIM_CCMR1_IC2PSC_0                  (0x0400UL)            /*!<Bit 0 */
+#define  TIM_CCMR1_IC2PSC_1                  (0x0800UL)            /*!<Bit 1 */
 
-#define  TIM_CCMR1_IC2F                      ((uint32_t)0xF000)            /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */
-#define  TIM_CCMR1_IC2F_0                    ((uint32_t)0x1000)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2F_1                    ((uint32_t)0x2000)            /*!<Bit 1 */
-#define  TIM_CCMR1_IC2F_2                    ((uint32_t)0x4000)            /*!<Bit 2 */
-#define  TIM_CCMR1_IC2F_3                    ((uint32_t)0x8000)            /*!<Bit 3 */
+#define  TIM_CCMR1_IC2F                      (0xF000UL)            /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */
+#define  TIM_CCMR1_IC2F_0                    (0x1000UL)            /*!<Bit 0 */
+#define  TIM_CCMR1_IC2F_1                    (0x2000UL)            /*!<Bit 1 */
+#define  TIM_CCMR1_IC2F_2                    (0x4000UL)            /*!<Bit 2 */
+#define  TIM_CCMR1_IC2F_3                    (0x8000UL)            /*!<Bit 3 */
 
 /******************  Bit definition for TIM_CCMR2 register  *******************/
-#define  TIM_CCMR2_CC3S                      ((uint32_t)0x0003)            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */
-#define  TIM_CCMR2_CC3S_0                    ((uint32_t)0x0001)            /*!<Bit 0 */
-#define  TIM_CCMR2_CC3S_1                    ((uint32_t)0x0002)            /*!<Bit 1 */
+#define  TIM_CCMR2_CC3S                      (0x0003UL)            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */
+#define  TIM_CCMR2_CC3S_0                    (0x0001UL)            /*!<Bit 0 */
+#define  TIM_CCMR2_CC3S_1                    (0x0002UL)            /*!<Bit 1 */
 
-#define  TIM_CCMR2_OC3FE                     ((uint32_t)0x0004)            /*!<Output Compare 3 Fast enable           */
-#define  TIM_CCMR2_OC3PE                     ((uint32_t)0x0008)            /*!<Output Compare 3 Preload enable        */
+#define  TIM_CCMR2_OC3FE                     (0x0004UL)            /*!<Output Compare 3 Fast enable           */
+#define  TIM_CCMR2_OC3PE                     (0x0008UL)            /*!<Output Compare 3 Preload enable        */
 
-#define  TIM_CCMR2_OC3M                      ((uint32_t)0x0070)            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define  TIM_CCMR2_OC3M_0                    ((uint32_t)0x0010)            /*!<Bit 0 */
-#define  TIM_CCMR2_OC3M_1                    ((uint32_t)0x0020)            /*!<Bit 1 */
-#define  TIM_CCMR2_OC3M_2                    ((uint32_t)0x0040)            /*!<Bit 2 */
+#define  TIM_CCMR2_OC3M                      (0x0070UL)            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define  TIM_CCMR2_OC3M_0                    (0x0010UL)            /*!<Bit 0 */
+#define  TIM_CCMR2_OC3M_1                    (0x0020UL)            /*!<Bit 1 */
+#define  TIM_CCMR2_OC3M_2                    (0x0040UL)            /*!<Bit 2 */
 
-#define  TIM_CCMR2_OC3CE                     ((uint32_t)0x0080)            /*!<Output Compare 3 Clear Enable */
+#define  TIM_CCMR2_OC3CE                     (0x0080UL)            /*!<Output Compare 3 Clear Enable */
 
-#define  TIM_CCMR2_CC4S                      ((uint32_t)0x0300)            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define  TIM_CCMR2_CC4S_0                    ((uint32_t)0x0100)            /*!<Bit 0 */
-#define  TIM_CCMR2_CC4S_1                    ((uint32_t)0x0200)            /*!<Bit 1 */
+#define  TIM_CCMR2_CC4S                      (0x0300UL)            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define  TIM_CCMR2_CC4S_0                    (0x0100UL)            /*!<Bit 0 */
+#define  TIM_CCMR2_CC4S_1                    (0x0200UL)            /*!<Bit 1 */
 
-#define  TIM_CCMR2_OC4FE                     ((uint32_t)0x0400)            /*!<Output Compare 4 Fast enable    */
-#define  TIM_CCMR2_OC4PE                     ((uint32_t)0x0800)            /*!<Output Compare 4 Preload enable */
+#define  TIM_CCMR2_OC4FE                     (0x0400UL)            /*!<Output Compare 4 Fast enable    */
+#define  TIM_CCMR2_OC4PE                     (0x0800UL)            /*!<Output Compare 4 Preload enable */
 
-#define  TIM_CCMR2_OC4M                      ((uint32_t)0x7000)            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define  TIM_CCMR2_OC4M_0                    ((uint32_t)0x1000)            /*!<Bit 0 */
-#define  TIM_CCMR2_OC4M_1                    ((uint32_t)0x2000)            /*!<Bit 1 */
-#define  TIM_CCMR2_OC4M_2                    ((uint32_t)0x4000)            /*!<Bit 2 */
+#define  TIM_CCMR2_OC4M                      (0x7000UL)            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define  TIM_CCMR2_OC4M_0                    (0x1000UL)            /*!<Bit 0 */
+#define  TIM_CCMR2_OC4M_1                    (0x2000UL)            /*!<Bit 1 */
+#define  TIM_CCMR2_OC4M_2                    (0x4000UL)            /*!<Bit 2 */
 
-#define  TIM_CCMR2_OC4CE                     ((uint32_t)0x8000)            /*!<Output Compare 4 Clear Enable */
+#define  TIM_CCMR2_OC4CE                     (0x8000UL)            /*!<Output Compare 4 Clear Enable */
 
 /*----------------------------------------------------------------------------*/
 
-#define  TIM_CCMR2_IC3PSC                    ((uint32_t)0x000C)            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define  TIM_CCMR2_IC3PSC_0                  ((uint32_t)0x0004)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3PSC_1                  ((uint32_t)0x0008)            /*!<Bit 1 */
+#define  TIM_CCMR2_IC3PSC                    (0x000CUL)            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define  TIM_CCMR2_IC3PSC_0                  (0x0004UL)            /*!<Bit 0 */
+#define  TIM_CCMR2_IC3PSC_1                  (0x0008UL)            /*!<Bit 1 */
 
-#define  TIM_CCMR2_IC3F                      ((uint32_t)0x00F0)            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define  TIM_CCMR2_IC3F_0                    ((uint32_t)0x0010)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3F_1                    ((uint32_t)0x0020)            /*!<Bit 1 */
-#define  TIM_CCMR2_IC3F_2                    ((uint32_t)0x0040)            /*!<Bit 2 */
-#define  TIM_CCMR2_IC3F_3                    ((uint32_t)0x0080)            /*!<Bit 3 */
+#define  TIM_CCMR2_IC3F                      (0x00F0UL)            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define  TIM_CCMR2_IC3F_0                    (0x0010UL)            /*!<Bit 0 */
+#define  TIM_CCMR2_IC3F_1                    (0x0020UL)            /*!<Bit 1 */
+#define  TIM_CCMR2_IC3F_2                    (0x0040UL)            /*!<Bit 2 */
+#define  TIM_CCMR2_IC3F_3                    (0x0080UL)            /*!<Bit 3 */
 
-#define  TIM_CCMR2_IC4PSC                    ((uint32_t)0x0C00)            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define  TIM_CCMR2_IC4PSC_0                  ((uint32_t)0x0400)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4PSC_1                  ((uint32_t)0x0800)            /*!<Bit 1 */
+#define  TIM_CCMR2_IC4PSC                    (0x0C00UL)            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define  TIM_CCMR2_IC4PSC_0                  (0x0400UL)            /*!<Bit 0 */
+#define  TIM_CCMR2_IC4PSC_1                  (0x0800UL)            /*!<Bit 1 */
 
-#define  TIM_CCMR2_IC4F                      ((uint32_t)0xF000)            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define  TIM_CCMR2_IC4F_0                    ((uint32_t)0x1000)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4F_1                    ((uint32_t)0x2000)            /*!<Bit 1 */
-#define  TIM_CCMR2_IC4F_2                    ((uint32_t)0x4000)            /*!<Bit 2 */
-#define  TIM_CCMR2_IC4F_3                    ((uint32_t)0x8000)            /*!<Bit 3 */
+#define  TIM_CCMR2_IC4F                      (0xF000UL)            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define  TIM_CCMR2_IC4F_0                    (0x1000UL)            /*!<Bit 0 */
+#define  TIM_CCMR2_IC4F_1                    (0x2000UL)            /*!<Bit 1 */
+#define  TIM_CCMR2_IC4F_2                    (0x4000UL)            /*!<Bit 2 */
+#define  TIM_CCMR2_IC4F_3                    (0x8000UL)            /*!<Bit 3 */
 
 /*******************  Bit definition for TIM_CCER register  *******************/
-#define  TIM_CCER_CC1E                       ((uint32_t)0x0001)            /*!<Capture/Compare 1 output enable                 */
-#define  TIM_CCER_CC1P                       ((uint32_t)0x0002)            /*!<Capture/Compare 1 output Polarity               */
-#define  TIM_CCER_CC1NE                      ((uint32_t)0x0004)            /*!<Capture/Compare 1 Complementary output enable   */
-#define  TIM_CCER_CC1NP                      ((uint32_t)0x0008)            /*!<Capture/Compare 1 Complementary output Polarity */
-#define  TIM_CCER_CC2E                       ((uint32_t)0x0010)            /*!<Capture/Compare 2 output enable                 */
-#define  TIM_CCER_CC2P                       ((uint32_t)0x0020)            /*!<Capture/Compare 2 output Polarity               */
-#define  TIM_CCER_CC2NE                      ((uint32_t)0x0040)            /*!<Capture/Compare 2 Complementary output enable   */
-#define  TIM_CCER_CC2NP                      ((uint32_t)0x0080)            /*!<Capture/Compare 2 Complementary output Polarity */
-#define  TIM_CCER_CC3E                       ((uint32_t)0x0100)            /*!<Capture/Compare 3 output enable                 */
-#define  TIM_CCER_CC3P                       ((uint32_t)0x0200)            /*!<Capture/Compare 3 output Polarity               */
-#define  TIM_CCER_CC3NE                      ((uint32_t)0x0400)            /*!<Capture/Compare 3 Complementary output enable   */
-#define  TIM_CCER_CC3NP                      ((uint32_t)0x0800)            /*!<Capture/Compare 3 Complementary output Polarity */
-#define  TIM_CCER_CC4E                       ((uint32_t)0x1000)            /*!<Capture/Compare 4 output enable                 */
-#define  TIM_CCER_CC4P                       ((uint32_t)0x2000)            /*!<Capture/Compare 4 output Polarity               */
-#define  TIM_CCER_CC4NP                      ((uint32_t)0x8000)            /*!<Capture/Compare 4 Complementary output Polarity */
+#define  TIM_CCER_CC1E                       (0x0001UL)            /*!<Capture/Compare 1 output enable                 */
+#define  TIM_CCER_CC1P                       (0x0002UL)            /*!<Capture/Compare 1 output Polarity               */
+#define  TIM_CCER_CC1NE                      (0x0004UL)            /*!<Capture/Compare 1 Complementary output enable   */
+#define  TIM_CCER_CC1NP                      (0x0008UL)            /*!<Capture/Compare 1 Complementary output Polarity */
+#define  TIM_CCER_CC2E                       (0x0010UL)            /*!<Capture/Compare 2 output enable                 */
+#define  TIM_CCER_CC2P                       (0x0020UL)            /*!<Capture/Compare 2 output Polarity               */
+#define  TIM_CCER_CC2NE                      (0x0040UL)            /*!<Capture/Compare 2 Complementary output enable   */
+#define  TIM_CCER_CC2NP                      (0x0080UL)            /*!<Capture/Compare 2 Complementary output Polarity */
+#define  TIM_CCER_CC3E                       (0x0100UL)            /*!<Capture/Compare 3 output enable                 */
+#define  TIM_CCER_CC3P                       (0x0200UL)            /*!<Capture/Compare 3 output Polarity               */
+#define  TIM_CCER_CC3NE                      (0x0400UL)            /*!<Capture/Compare 3 Complementary output enable   */
+#define  TIM_CCER_CC3NP                      (0x0800UL)            /*!<Capture/Compare 3 Complementary output Polarity */
+#define  TIM_CCER_CC4E                       (0x1000UL)            /*!<Capture/Compare 4 output enable                 */
+#define  TIM_CCER_CC4P                       (0x2000UL)            /*!<Capture/Compare 4 output Polarity               */
+#define  TIM_CCER_CC4NP                      (0x8000UL)            /*!<Capture/Compare 4 Complementary output Polarity */
 
 /*******************  Bit definition for TIM_CNT register  ********************/
-#define  TIM_CNT_CNT                         ((uint32_t)0xFFFF)            /*!<Counter Value            */
+#define  TIM_CNT_CNT                         (0xFFFFUL)            /*!<Counter Value            */
 
 /*******************  Bit definition for TIM_PSC register  ********************/
-#define  TIM_PSC_PSC                         ((uint32_t)0xFFFF)            /*!<Prescaler Value          */
+#define  TIM_PSC_PSC                         (0xFFFFUL)            /*!<Prescaler Value          */
 
 /*******************  Bit definition for TIM_ARR register  ********************/
-#define  TIM_ARR_ARR                         ((uint32_t)0xFFFF)            /*!<actual auto-reload Value */
+#define  TIM_ARR_ARR                         (0xFFFFUL)            /*!<actual auto-reload Value */
 
 /*******************  Bit definition for TIM_RCR register  ********************/
-#define  TIM_RCR_REP                         ((uint32_t)0xFF)               /*!<Repetition Counter Value */
+#define  TIM_RCR_REP                         (0xFFUL)               /*!<Repetition Counter Value */
 
 /*******************  Bit definition for TIM_CCR1 register  *******************/
-#define  TIM_CCR1_CCR1                       ((uint32_t)0xFFFF)            /*!<Capture/Compare 1 Value  */
+#define  TIM_CCR1_CCR1                       (0xFFFFUL)            /*!<Capture/Compare 1 Value  */
 
 /*******************  Bit definition for TIM_CCR2 register  *******************/
-#define  TIM_CCR2_CCR2                       ((uint32_t)0xFFFF)            /*!<Capture/Compare 2 Value  */
+#define  TIM_CCR2_CCR2                       (0xFFFFUL)            /*!<Capture/Compare 2 Value  */
 
 /*******************  Bit definition for TIM_CCR3 register  *******************/
-#define  TIM_CCR3_CCR3                       ((uint32_t)0xFFFF)            /*!<Capture/Compare 3 Value  */
+#define  TIM_CCR3_CCR3                       (0xFFFFUL)            /*!<Capture/Compare 3 Value  */
 
 /*******************  Bit definition for TIM_CCR4 register  *******************/
-#define  TIM_CCR4_CCR4                       ((uint32_t)0xFFFF)            /*!<Capture/Compare 4 Value  */
+#define  TIM_CCR4_CCR4                       (0xFFFFUL)            /*!<Capture/Compare 4 Value  */
 
 /*******************  Bit definition for TIM_BDTR register  *******************/
-#define  TIM_BDTR_DTG                        ((uint32_t)0x00FF)            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
-#define  TIM_BDTR_DTG_0                      ((uint32_t)0x0001)            /*!<Bit 0 */
-#define  TIM_BDTR_DTG_1                      ((uint32_t)0x0002)            /*!<Bit 1 */
-#define  TIM_BDTR_DTG_2                      ((uint32_t)0x0004)            /*!<Bit 2 */
-#define  TIM_BDTR_DTG_3                      ((uint32_t)0x0008)            /*!<Bit 3 */
-#define  TIM_BDTR_DTG_4                      ((uint32_t)0x0010)            /*!<Bit 4 */
-#define  TIM_BDTR_DTG_5                      ((uint32_t)0x0020)            /*!<Bit 5 */
-#define  TIM_BDTR_DTG_6                      ((uint32_t)0x0040)            /*!<Bit 6 */
-#define  TIM_BDTR_DTG_7                      ((uint32_t)0x0080)            /*!<Bit 7 */
+#define  TIM_BDTR_DTG                        (0x00FFUL)            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define  TIM_BDTR_DTG_0                      (0x0001UL)            /*!<Bit 0 */
+#define  TIM_BDTR_DTG_1                      (0x0002UL)            /*!<Bit 1 */
+#define  TIM_BDTR_DTG_2                      (0x0004UL)            /*!<Bit 2 */
+#define  TIM_BDTR_DTG_3                      (0x0008UL)            /*!<Bit 3 */
+#define  TIM_BDTR_DTG_4                      (0x0010UL)            /*!<Bit 4 */
+#define  TIM_BDTR_DTG_5                      (0x0020UL)            /*!<Bit 5 */
+#define  TIM_BDTR_DTG_6                      (0x0040UL)            /*!<Bit 6 */
+#define  TIM_BDTR_DTG_7                      (0x0080UL)            /*!<Bit 7 */
 
-#define  TIM_BDTR_LOCK                       ((uint32_t)0x0300)            /*!<LOCK[1:0] bits (Lock Configuration) */
-#define  TIM_BDTR_LOCK_0                     ((uint32_t)0x0100)            /*!<Bit 0 */
-#define  TIM_BDTR_LOCK_1                     ((uint32_t)0x0200)            /*!<Bit 1 */
+#define  TIM_BDTR_LOCK                       (0x0300UL)            /*!<LOCK[1:0] bits (Lock Configuration) */
+#define  TIM_BDTR_LOCK_0                     (0x0100UL)            /*!<Bit 0 */
+#define  TIM_BDTR_LOCK_1                     (0x0200UL)            /*!<Bit 1 */
 
-#define  TIM_BDTR_OSSI                       ((uint32_t)0x0400)            /*!<Off-State Selection for Idle mode */
-#define  TIM_BDTR_OSSR                       ((uint32_t)0x0800)            /*!<Off-State Selection for Run mode  */
-#define  TIM_BDTR_BKE                        ((uint32_t)0x1000)            /*!<Break enable                      */
-#define  TIM_BDTR_BKP                        ((uint32_t)0x2000)            /*!<Break Polarity                    */
-#define  TIM_BDTR_AOE                        ((uint32_t)0x4000)            /*!<Automatic Output enable           */
-#define  TIM_BDTR_MOE                        ((uint32_t)0x8000)            /*!<Main Output enable                */
+#define  TIM_BDTR_OSSI                       (0x0400UL)            /*!<Off-State Selection for Idle mode */
+#define  TIM_BDTR_OSSR                       (0x0800UL)            /*!<Off-State Selection for Run mode  */
+#define  TIM_BDTR_BKE                        (0x1000UL)            /*!<Break enable                      */
+#define  TIM_BDTR_BKP                        (0x2000UL)            /*!<Break Polarity                    */
+#define  TIM_BDTR_AOE                        (0x4000UL)            /*!<Automatic Output enable           */
+#define  TIM_BDTR_MOE                        (0x8000UL)            /*!<Main Output enable                */
 
 /*******************  Bit definition for TIM_DCR register  ********************/
-#define  TIM_DCR_DBA                         ((uint32_t)0x001F)            /*!<DBA[4:0] bits (DMA Base Address) */
-#define  TIM_DCR_DBA_0                       ((uint32_t)0x0001)            /*!<Bit 0 */
-#define  TIM_DCR_DBA_1                       ((uint32_t)0x0002)            /*!<Bit 1 */
-#define  TIM_DCR_DBA_2                       ((uint32_t)0x0004)            /*!<Bit 2 */
-#define  TIM_DCR_DBA_3                       ((uint32_t)0x0008)            /*!<Bit 3 */
-#define  TIM_DCR_DBA_4                       ((uint32_t)0x0010)            /*!<Bit 4 */
+#define  TIM_DCR_DBA                         (0x001FUL)            /*!<DBA[4:0] bits (DMA Base Address) */
+#define  TIM_DCR_DBA_0                       (0x0001UL)            /*!<Bit 0 */
+#define  TIM_DCR_DBA_1                       (0x0002UL)            /*!<Bit 1 */
+#define  TIM_DCR_DBA_2                       (0x0004UL)            /*!<Bit 2 */
+#define  TIM_DCR_DBA_3                       (0x0008UL)            /*!<Bit 3 */
+#define  TIM_DCR_DBA_4                       (0x0010UL)            /*!<Bit 4 */
 
-#define  TIM_DCR_DBL                         ((uint32_t)0x1F00)            /*!<DBL[4:0] bits (DMA Burst Length) */
-#define  TIM_DCR_DBL_0                       ((uint32_t)0x0100)            /*!<Bit 0 */
-#define  TIM_DCR_DBL_1                       ((uint32_t)0x0200)            /*!<Bit 1 */
-#define  TIM_DCR_DBL_2                       ((uint32_t)0x0400)            /*!<Bit 2 */
-#define  TIM_DCR_DBL_3                       ((uint32_t)0x0800)            /*!<Bit 3 */
-#define  TIM_DCR_DBL_4                       ((uint32_t)0x1000)            /*!<Bit 4 */
+#define  TIM_DCR_DBL                         (0x1F00UL)            /*!<DBL[4:0] bits (DMA Burst Length) */
+#define  TIM_DCR_DBL_0                       (0x0100UL)            /*!<Bit 0 */
+#define  TIM_DCR_DBL_1                       (0x0200UL)            /*!<Bit 1 */
+#define  TIM_DCR_DBL_2                       (0x0400UL)            /*!<Bit 2 */
+#define  TIM_DCR_DBL_3                       (0x0800UL)            /*!<Bit 3 */
+#define  TIM_DCR_DBL_4                       (0x1000UL)            /*!<Bit 4 */
 
 /*******************  Bit definition for TIM_DMAR register  *******************/
-#define  TIM_DMAR_DMAB                       ((uint32_t)0xFFFF)            /*!<DMA register for burst accesses                    */
+#define  TIM_DMAR_DMAB                       (0xFFFFUL)            /*!<DMA register for burst accesses                    */
 
 /*******************  Bit definition for TIM_OR register  *********************/
-#define TIM_OR_TI4_RMP                       ((uint32_t)0x00C0)            /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */
-#define TIM_OR_TI4_RMP_0                     ((uint32_t)0x0040)            /*!<Bit 0 */
-#define TIM_OR_TI4_RMP_1                     ((uint32_t)0x0080)            /*!<Bit 1 */
-#define TIM_OR_ITR1_RMP                      ((uint32_t)0x0C00)            /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
-#define TIM_OR_ITR1_RMP_0                    ((uint32_t)0x0400)            /*!<Bit 0 */
-#define TIM_OR_ITR1_RMP_1                    ((uint32_t)0x0800)            /*!<Bit 1 */
+#define TIM_OR_TI4_RMP                       (0x00C0UL)            /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */
+#define TIM_OR_TI4_RMP_0                     (0x0040UL)            /*!<Bit 0 */
+#define TIM_OR_TI4_RMP_1                     (0x0080UL)            /*!<Bit 1 */
+#define TIM_OR_ITR1_RMP                      (0x0C00UL)            /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
+#define TIM_OR_ITR1_RMP_0                    (0x0400UL)            /*!<Bit 0 */
+#define TIM_OR_ITR1_RMP_1                    (0x0800UL)            /*!<Bit 1 */
 
 
 /******************************************************************************/
@@ -3742,82 +3738,82 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for USART_SR register  *******************/
-#define  USART_SR_PE                         ((uint32_t)0x0001)            /*!<Parity Error                 */
-#define  USART_SR_FE                         ((uint32_t)0x0002)            /*!<Framing Error                */
-#define  USART_SR_NE                         ((uint32_t)0x0004)            /*!<Noise Error Flag             */
-#define  USART_SR_ORE                        ((uint32_t)0x0008)            /*!<OverRun Error                */
-#define  USART_SR_IDLE                       ((uint32_t)0x0010)            /*!<IDLE line detected           */
-#define  USART_SR_RXNE                       ((uint32_t)0x0020)            /*!<Read Data Register Not Empty */
-#define  USART_SR_TC                         ((uint32_t)0x0040)            /*!<Transmission Complete        */
-#define  USART_SR_TXE                        ((uint32_t)0x0080)            /*!<Transmit Data Register Empty */
-#define  USART_SR_LBD                        ((uint32_t)0x0100)            /*!<LIN Break Detection Flag     */
-#define  USART_SR_CTS                        ((uint32_t)0x0200)            /*!<CTS Flag                     */
+#define  USART_SR_PE                         (0x0001UL)            /*!<Parity Error                 */
+#define  USART_SR_FE                         (0x0002UL)            /*!<Framing Error                */
+#define  USART_SR_NE                         (0x0004UL)            /*!<Noise Error Flag             */
+#define  USART_SR_ORE                        (0x0008UL)            /*!<OverRun Error                */
+#define  USART_SR_IDLE                       (0x0010UL)            /*!<IDLE line detected           */
+#define  USART_SR_RXNE                       (0x0020UL)            /*!<Read Data Register Not Empty */
+#define  USART_SR_TC                         (0x0040UL)            /*!<Transmission Complete        */
+#define  USART_SR_TXE                        (0x0080UL)            /*!<Transmit Data Register Empty */
+#define  USART_SR_LBD                        (0x0100UL)            /*!<LIN Break Detection Flag     */
+#define  USART_SR_CTS                        (0x0200UL)            /*!<CTS Flag                     */
 
 /*******************  Bit definition for USART_DR register  *******************/
-#define  USART_DR_DR                         ((uint32_t)0x01FF)            /*!<Data value */
+#define  USART_DR_DR                         (0x01FFUL)            /*!<Data value */
 
 /******************  Bit definition for USART_BRR register  *******************/
-#define  USART_BRR_DIV_Fraction              ((uint32_t)0x000F)            /*!<Fraction of USARTDIV */
-#define  USART_BRR_DIV_Mantissa              ((uint32_t)0xFFF0)            /*!<Mantissa of USARTDIV */
+#define  USART_BRR_DIV_Fraction              (0x000FUL)            /*!<Fraction of USARTDIV */
+#define  USART_BRR_DIV_Mantissa              (0xFFF0UL)            /*!<Mantissa of USARTDIV */
 
 /******************  Bit definition for USART_CR1 register  *******************/
-#define  USART_CR1_SBK                       ((uint32_t)0x0001)            /*!<Send Break                             */
-#define  USART_CR1_RWU                       ((uint32_t)0x0002)            /*!<Receiver wakeup                        */
-#define  USART_CR1_RE                        ((uint32_t)0x0004)            /*!<Receiver Enable                        */
-#define  USART_CR1_TE                        ((uint32_t)0x0008)            /*!<Transmitter Enable                     */
-#define  USART_CR1_IDLEIE                    ((uint32_t)0x0010)            /*!<IDLE Interrupt Enable                  */
-#define  USART_CR1_RXNEIE                    ((uint32_t)0x0020)            /*!<RXNE Interrupt Enable                  */
-#define  USART_CR1_TCIE                      ((uint32_t)0x0040)            /*!<Transmission Complete Interrupt Enable */
-#define  USART_CR1_TXEIE                     ((uint32_t)0x0080)            /*!<PE Interrupt Enable                    */
-#define  USART_CR1_PEIE                      ((uint32_t)0x0100)            /*!<PE Interrupt Enable                    */
-#define  USART_CR1_PS                        ((uint32_t)0x0200)            /*!<Parity Selection                       */
-#define  USART_CR1_PCE                       ((uint32_t)0x0400)            /*!<Parity Control Enable                  */
-#define  USART_CR1_WAKE                      ((uint32_t)0x0800)            /*!<Wakeup method                          */
-#define  USART_CR1_M                         ((uint32_t)0x1000)            /*!<Word length                            */
-#define  USART_CR1_UE                        ((uint32_t)0x2000)            /*!<USART Enable                           */
-#define  USART_CR1_OVER8                     ((uint32_t)0x8000)            /*!<USART Oversampling by 8 enable         */
+#define  USART_CR1_SBK                       (0x0001UL)            /*!<Send Break                             */
+#define  USART_CR1_RWU                       (0x0002UL)            /*!<Receiver wakeup                        */
+#define  USART_CR1_RE                        (0x0004UL)            /*!<Receiver Enable                        */
+#define  USART_CR1_TE                        (0x0008UL)            /*!<Transmitter Enable                     */
+#define  USART_CR1_IDLEIE                    (0x0010UL)            /*!<IDLE Interrupt Enable                  */
+#define  USART_CR1_RXNEIE                    (0x0020UL)            /*!<RXNE Interrupt Enable                  */
+#define  USART_CR1_TCIE                      (0x0040UL)            /*!<Transmission Complete Interrupt Enable */
+#define  USART_CR1_TXEIE                     (0x0080UL)            /*!<PE Interrupt Enable                    */
+#define  USART_CR1_PEIE                      (0x0100UL)            /*!<PE Interrupt Enable                    */
+#define  USART_CR1_PS                        (0x0200UL)            /*!<Parity Selection                       */
+#define  USART_CR1_PCE                       (0x0400UL)            /*!<Parity Control Enable                  */
+#define  USART_CR1_WAKE                      (0x0800UL)            /*!<Wakeup method                          */
+#define  USART_CR1_M                         (0x1000UL)            /*!<Word length                            */
+#define  USART_CR1_UE                        (0x2000UL)            /*!<USART Enable                           */
+#define  USART_CR1_OVER8                     (0x8000UL)            /*!<USART Oversampling by 8 enable         */
 
 /******************  Bit definition for USART_CR2 register  *******************/
-#define  USART_CR2_ADD                       ((uint32_t)0x000F)            /*!<Address of the USART node            */
-#define  USART_CR2_LBDL                      ((uint32_t)0x0020)            /*!<LIN Break Detection Length           */
-#define  USART_CR2_LBDIE                     ((uint32_t)0x0040)            /*!<LIN Break Detection Interrupt Enable */
-#define  USART_CR2_LBCL                      ((uint32_t)0x0100)            /*!<Last Bit Clock pulse                 */
-#define  USART_CR2_CPHA                      ((uint32_t)0x0200)            /*!<Clock Phase                          */
-#define  USART_CR2_CPOL                      ((uint32_t)0x0400)            /*!<Clock Polarity                       */
-#define  USART_CR2_CLKEN                     ((uint32_t)0x0800)            /*!<Clock Enable                         */
+#define  USART_CR2_ADD                       (0x000FUL)            /*!<Address of the USART node            */
+#define  USART_CR2_LBDL                      (0x0020UL)            /*!<LIN Break Detection Length           */
+#define  USART_CR2_LBDIE                     (0x0040UL)            /*!<LIN Break Detection Interrupt Enable */
+#define  USART_CR2_LBCL                      (0x0100UL)            /*!<Last Bit Clock pulse                 */
+#define  USART_CR2_CPHA                      (0x0200UL)            /*!<Clock Phase                          */
+#define  USART_CR2_CPOL                      (0x0400UL)            /*!<Clock Polarity                       */
+#define  USART_CR2_CLKEN                     (0x0800UL)            /*!<Clock Enable                         */
 
-#define  USART_CR2_STOP                      ((uint32_t)0x3000)            /*!<STOP[1:0] bits (STOP bits) */
-#define  USART_CR2_STOP_0                    ((uint32_t)0x1000)            /*!<Bit 0 */
-#define  USART_CR2_STOP_1                    ((uint32_t)0x2000)            /*!<Bit 1 */
+#define  USART_CR2_STOP                      (0x3000UL)            /*!<STOP[1:0] bits (STOP bits) */
+#define  USART_CR2_STOP_0                    (0x1000UL)            /*!<Bit 0 */
+#define  USART_CR2_STOP_1                    (0x2000UL)            /*!<Bit 1 */
 
-#define  USART_CR2_LINEN                     ((uint32_t)0x4000)            /*!<LIN mode enable */
+#define  USART_CR2_LINEN                     (0x4000UL)            /*!<LIN mode enable */
 
 /******************  Bit definition for USART_CR3 register  *******************/
-#define  USART_CR3_EIE                       ((uint32_t)0x0001)            /*!<Error Interrupt Enable      */
-#define  USART_CR3_IREN                      ((uint32_t)0x0002)            /*!<IrDA mode Enable            */
-#define  USART_CR3_IRLP                      ((uint32_t)0x0004)            /*!<IrDA Low-Power              */
-#define  USART_CR3_HDSEL                     ((uint32_t)0x0008)            /*!<Half-Duplex Selection       */
-#define  USART_CR3_NACK                      ((uint32_t)0x0010)            /*!<Smartcard NACK enable       */
-#define  USART_CR3_SCEN                      ((uint32_t)0x0020)            /*!<Smartcard mode enable       */
-#define  USART_CR3_DMAR                      ((uint32_t)0x0040)            /*!<DMA Enable Receiver         */
-#define  USART_CR3_DMAT                      ((uint32_t)0x0080)            /*!<DMA Enable Transmitter      */
-#define  USART_CR3_RTSE                      ((uint32_t)0x0100)            /*!<RTS Enable                  */
-#define  USART_CR3_CTSE                      ((uint32_t)0x0200)            /*!<CTS Enable                  */
-#define  USART_CR3_CTSIE                     ((uint32_t)0x0400)            /*!<CTS Interrupt Enable        */
-#define  USART_CR3_ONEBIT                    ((uint32_t)0x0800)            /*!<USART One bit method enable */
+#define  USART_CR3_EIE                       (0x0001UL)            /*!<Error Interrupt Enable      */
+#define  USART_CR3_IREN                      (0x0002UL)            /*!<IrDA mode Enable            */
+#define  USART_CR3_IRLP                      (0x0004UL)            /*!<IrDA Low-Power              */
+#define  USART_CR3_HDSEL                     (0x0008UL)            /*!<Half-Duplex Selection       */
+#define  USART_CR3_NACK                      (0x0010UL)            /*!<Smartcard NACK enable       */
+#define  USART_CR3_SCEN                      (0x0020UL)            /*!<Smartcard mode enable       */
+#define  USART_CR3_DMAR                      (0x0040UL)            /*!<DMA Enable Receiver         */
+#define  USART_CR3_DMAT                      (0x0080UL)            /*!<DMA Enable Transmitter      */
+#define  USART_CR3_RTSE                      (0x0100UL)            /*!<RTS Enable                  */
+#define  USART_CR3_CTSE                      (0x0200UL)            /*!<CTS Enable                  */
+#define  USART_CR3_CTSIE                     (0x0400UL)            /*!<CTS Interrupt Enable        */
+#define  USART_CR3_ONEBIT                    (0x0800UL)            /*!<USART One bit method enable */
 
 /******************  Bit definition for USART_GTPR register  ******************/
-#define  USART_GTPR_PSC                      ((uint32_t)0x00FF)            /*!<PSC[7:0] bits (Prescaler value) */
-#define  USART_GTPR_PSC_0                    ((uint32_t)0x0001)            /*!<Bit 0 */
-#define  USART_GTPR_PSC_1                    ((uint32_t)0x0002)            /*!<Bit 1 */
-#define  USART_GTPR_PSC_2                    ((uint32_t)0x0004)            /*!<Bit 2 */
-#define  USART_GTPR_PSC_3                    ((uint32_t)0x0008)            /*!<Bit 3 */
-#define  USART_GTPR_PSC_4                    ((uint32_t)0x0010)            /*!<Bit 4 */
-#define  USART_GTPR_PSC_5                    ((uint32_t)0x0020)            /*!<Bit 5 */
-#define  USART_GTPR_PSC_6                    ((uint32_t)0x0040)            /*!<Bit 6 */
-#define  USART_GTPR_PSC_7                    ((uint32_t)0x0080)            /*!<Bit 7 */
+#define  USART_GTPR_PSC                      (0x00FFUL)            /*!<PSC[7:0] bits (Prescaler value) */
+#define  USART_GTPR_PSC_0                    (0x0001UL)            /*!<Bit 0 */
+#define  USART_GTPR_PSC_1                    (0x0002UL)            /*!<Bit 1 */
+#define  USART_GTPR_PSC_2                    (0x0004UL)            /*!<Bit 2 */
+#define  USART_GTPR_PSC_3                    (0x0008UL)            /*!<Bit 3 */
+#define  USART_GTPR_PSC_4                    (0x0010UL)            /*!<Bit 4 */
+#define  USART_GTPR_PSC_5                    (0x0020UL)            /*!<Bit 5 */
+#define  USART_GTPR_PSC_6                    (0x0040UL)            /*!<Bit 6 */
+#define  USART_GTPR_PSC_7                    (0x0080UL)            /*!<Bit 7 */
 
-#define  USART_GTPR_GT                       ((uint32_t)0xFF00)            /*!<Guard time value */
+#define  USART_GTPR_GT                       (0xFF00UL)            /*!<Guard time value */
 
 /******************************************************************************/
 /*                                                                            */
@@ -3825,35 +3821,35 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for WWDG_CR register  ********************/
-#define  WWDG_CR_T                           ((uint32_t)0x7F)               /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define  WWDG_CR_T0                          ((uint32_t)0x01)               /*!<Bit 0 */
-#define  WWDG_CR_T1                          ((uint32_t)0x02)               /*!<Bit 1 */
-#define  WWDG_CR_T2                          ((uint32_t)0x04)               /*!<Bit 2 */
-#define  WWDG_CR_T3                          ((uint32_t)0x08)               /*!<Bit 3 */
-#define  WWDG_CR_T4                          ((uint32_t)0x10)               /*!<Bit 4 */
-#define  WWDG_CR_T5                          ((uint32_t)0x20)               /*!<Bit 5 */
-#define  WWDG_CR_T6                          ((uint32_t)0x40)               /*!<Bit 6 */
+#define  WWDG_CR_T                           (0x7FUL)               /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define  WWDG_CR_T0                          (0x01UL)               /*!<Bit 0 */
+#define  WWDG_CR_T1                          (0x02UL)               /*!<Bit 1 */
+#define  WWDG_CR_T2                          (0x04UL)               /*!<Bit 2 */
+#define  WWDG_CR_T3                          (0x08UL)               /*!<Bit 3 */
+#define  WWDG_CR_T4                          (0x10UL)               /*!<Bit 4 */
+#define  WWDG_CR_T5                          (0x20UL)               /*!<Bit 5 */
+#define  WWDG_CR_T6                          (0x40UL)               /*!<Bit 6 */
 
-#define  WWDG_CR_WDGA                        ((uint32_t)0x80)               /*!<Activation bit */
+#define  WWDG_CR_WDGA                        (0x80UL)               /*!<Activation bit */
 
 /*******************  Bit definition for WWDG_CFR register  *******************/
-#define  WWDG_CFR_W                          ((uint32_t)0x007F)            /*!<W[6:0] bits (7-bit window value) */
-#define  WWDG_CFR_W0                         ((uint32_t)0x0001)            /*!<Bit 0 */
-#define  WWDG_CFR_W1                         ((uint32_t)0x0002)            /*!<Bit 1 */
-#define  WWDG_CFR_W2                         ((uint32_t)0x0004)            /*!<Bit 2 */
-#define  WWDG_CFR_W3                         ((uint32_t)0x0008)            /*!<Bit 3 */
-#define  WWDG_CFR_W4                         ((uint32_t)0x0010)            /*!<Bit 4 */
-#define  WWDG_CFR_W5                         ((uint32_t)0x0020)            /*!<Bit 5 */
-#define  WWDG_CFR_W6                         ((uint32_t)0x0040)            /*!<Bit 6 */
+#define  WWDG_CFR_W                          (0x007FUL)            /*!<W[6:0] bits (7-bit window value) */
+#define  WWDG_CFR_W0                         (0x0001UL)            /*!<Bit 0 */
+#define  WWDG_CFR_W1                         (0x0002UL)            /*!<Bit 1 */
+#define  WWDG_CFR_W2                         (0x0004UL)            /*!<Bit 2 */
+#define  WWDG_CFR_W3                         (0x0008UL)            /*!<Bit 3 */
+#define  WWDG_CFR_W4                         (0x0010UL)            /*!<Bit 4 */
+#define  WWDG_CFR_W5                         (0x0020UL)            /*!<Bit 5 */
+#define  WWDG_CFR_W6                         (0x0040UL)            /*!<Bit 6 */
 
-#define  WWDG_CFR_WDGTB                      ((uint32_t)0x0180)            /*!<WDGTB[1:0] bits (Timer Base) */
-#define  WWDG_CFR_WDGTB0                     ((uint32_t)0x0080)            /*!<Bit 0 */
-#define  WWDG_CFR_WDGTB1                     ((uint32_t)0x0100)            /*!<Bit 1 */
+#define  WWDG_CFR_WDGTB                      (0x0180UL)            /*!<WDGTB[1:0] bits (Timer Base) */
+#define  WWDG_CFR_WDGTB0                     (0x0080UL)            /*!<Bit 0 */
+#define  WWDG_CFR_WDGTB1                     (0x0100UL)            /*!<Bit 1 */
 
-#define  WWDG_CFR_EWI                        ((uint32_t)0x0200)            /*!<Early Wakeup Interrupt */
+#define  WWDG_CFR_EWI                        (0x0200UL)            /*!<Early Wakeup Interrupt */
 
 /*******************  Bit definition for WWDG_SR register  ********************/
-#define  WWDG_SR_EWIF                        ((uint32_t)0x01)               /*!<Early Wakeup Interrupt Flag */
+#define  WWDG_SR_EWIF                        (0x01UL)               /*!<Early Wakeup Interrupt Flag */
 
 
 /******************************************************************************/
@@ -3862,46 +3858,46 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for DBGMCU_IDCODE register  *************/
-#define  DBGMCU_IDCODE_DEV_ID                ((uint32_t)0x00000FFF)
-#define  DBGMCU_IDCODE_REV_ID                ((uint32_t)0xFFFF0000)
+#define  DBGMCU_IDCODE_DEV_ID                (0x00000FFFUL)
+#define  DBGMCU_IDCODE_REV_ID                (0xFFFF0000UL)
 
 /********************  Bit definition for DBGMCU_CR register  *****************/
-#define  DBGMCU_CR_DBG_SLEEP                 ((uint32_t)0x00000001)
-#define  DBGMCU_CR_DBG_STOP                  ((uint32_t)0x00000002)
-#define  DBGMCU_CR_DBG_STANDBY               ((uint32_t)0x00000004)
-#define  DBGMCU_CR_TRACE_IOEN                ((uint32_t)0x00000020)
+#define  DBGMCU_CR_DBG_SLEEP                 (0x00000001UL)
+#define  DBGMCU_CR_DBG_STOP                  (0x00000002UL)
+#define  DBGMCU_CR_DBG_STANDBY               (0x00000004UL)
+#define  DBGMCU_CR_TRACE_IOEN                (0x00000020UL)
 
-#define  DBGMCU_CR_TRACE_MODE                ((uint32_t)0x000000C0)
-#define  DBGMCU_CR_TRACE_MODE_0              ((uint32_t)0x00000040)/*!<Bit 0 */
-#define  DBGMCU_CR_TRACE_MODE_1              ((uint32_t)0x00000080)/*!<Bit 1 */
+#define  DBGMCU_CR_TRACE_MODE                (0x000000C0UL)
+#define  DBGMCU_CR_TRACE_MODE_0              (0x00000040UL)/*!<Bit 0 */
+#define  DBGMCU_CR_TRACE_MODE_1              (0x00000080UL)/*!<Bit 1 */
 
 /********************  Bit definition for DBGMCU_APB1_FZ register  ************/
-#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP            ((uint32_t)0x00000001)
-#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP            ((uint32_t)0x00000002)
-#define  DBGMCU_APB1_FZ_DBG_TIM4_STOP            ((uint32_t)0x00000004)
-#define  DBGMCU_APB1_FZ_DBG_TIM5_STOP            ((uint32_t)0x00000008)
-#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP            ((uint32_t)0x00000010)
-#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP            ((uint32_t)0x00000020)
-#define  DBGMCU_APB1_FZ_DBG_TIM12_STOP           ((uint32_t)0x00000040)
-#define  DBGMCU_APB1_FZ_DBG_TIM13_STOP           ((uint32_t)0x00000080)
-#define  DBGMCU_APB1_FZ_DBG_TIM14_STOP           ((uint32_t)0x00000100)
-#define  DBGMCU_APB1_FZ_DBG_RTC_STOP             ((uint32_t)0x00000400)
-#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP            ((uint32_t)0x00000800)
-#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP            ((uint32_t)0x00001000)
-#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   ((uint32_t)0x00200000)
-#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   ((uint32_t)0x00400000)
-#define  DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT   ((uint32_t)0x00800000)
-#define  DBGMCU_APB1_FZ_DBG_CAN1_STOP            ((uint32_t)0x02000000)
-#define  DBGMCU_APB1_FZ_DBG_CAN2_STOP            ((uint32_t)0x04000000)
+#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP            (0x00000001UL)
+#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP            (0x00000002UL)
+#define  DBGMCU_APB1_FZ_DBG_TIM4_STOP            (0x00000004UL)
+#define  DBGMCU_APB1_FZ_DBG_TIM5_STOP            (0x00000008UL)
+#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP            (0x00000010UL)
+#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP            (0x00000020UL)
+#define  DBGMCU_APB1_FZ_DBG_TIM12_STOP           (0x00000040UL)
+#define  DBGMCU_APB1_FZ_DBG_TIM13_STOP           (0x00000080UL)
+#define  DBGMCU_APB1_FZ_DBG_TIM14_STOP           (0x00000100UL)
+#define  DBGMCU_APB1_FZ_DBG_RTC_STOP             (0x00000400UL)
+#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP            (0x00000800UL)
+#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP            (0x00001000UL)
+#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   (0x00200000UL)
+#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   (0x00400000UL)
+#define  DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT   (0x00800000UL)
+#define  DBGMCU_APB1_FZ_DBG_CAN1_STOP            (0x02000000UL)
+#define  DBGMCU_APB1_FZ_DBG_CAN2_STOP            (0x04000000UL)
 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
 #define  DBGMCU_APB1_FZ_DBG_IWDEG_STOP           DBGMCU_APB1_FZ_DBG_IWDG_STOP
 
 /********************  Bit definition for DBGMCU_APB2_FZ register  ************/
-#define  DBGMCU_APB2_FZ_DBG_TIM1_STOP        ((uint32_t)0x00000001)
-#define  DBGMCU_APB2_FZ_DBG_TIM8_STOP        ((uint32_t)0x00000002)
-#define  DBGMCU_APB2_FZ_DBG_TIM9_STOP        ((uint32_t)0x00010000)
-#define  DBGMCU_APB2_FZ_DBG_TIM10_STOP       ((uint32_t)0x00020000)
-#define  DBGMCU_APB2_FZ_DBG_TIM11_STOP       ((uint32_t)0x00040000)
+#define  DBGMCU_APB2_FZ_DBG_TIM1_STOP        (0x00000001UL)
+#define  DBGMCU_APB2_FZ_DBG_TIM8_STOP        (0x00000002UL)
+#define  DBGMCU_APB2_FZ_DBG_TIM9_STOP        (0x00010000UL)
+#define  DBGMCU_APB2_FZ_DBG_TIM10_STOP       (0x00020000UL)
+#define  DBGMCU_APB2_FZ_DBG_TIM11_STOP       (0x00040000UL)
 
 /******************************************************************************/
 /*                                                                            */
@@ -3909,930 +3905,654 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition forUSB_OTG_GOTGCTL register  ********************/
-#define USB_OTG_GOTGCTL_SRQSCS                  ((uint32_t)0x00000001)            /*!< Session request success */
-#define USB_OTG_GOTGCTL_SRQ                     ((uint32_t)0x00000002)            /*!< Session request */
-#define USB_OTG_GOTGCTL_HNGSCS                  ((uint32_t)0x00000100)            /*!< Host negotiation success */
-#define USB_OTG_GOTGCTL_HNPRQ                   ((uint32_t)0x00000200)            /*!< HNP request */
-#define USB_OTG_GOTGCTL_HSHNPEN                 ((uint32_t)0x00000400)            /*!< Host set HNP enable */
-#define USB_OTG_GOTGCTL_DHNPEN                  ((uint32_t)0x00000800)            /*!< Device HNP enabled */
-#define USB_OTG_GOTGCTL_CIDSTS                  ((uint32_t)0x00010000)            /*!< Connector ID status */
-#define USB_OTG_GOTGCTL_DBCT                    ((uint32_t)0x00020000)            /*!< Long/short debounce time */
-#define USB_OTG_GOTGCTL_ASVLD                   ((uint32_t)0x00040000)            /*!< A-session valid */
-#define USB_OTG_GOTGCTL_BSVLD                   ((uint32_t)0x00080000)            /*!< B-session valid */
+#define USB_OTG_GOTGCTL_SRQSCS                  (0x00000001UL)            /*!< Session request success */
+#define USB_OTG_GOTGCTL_SRQ                     (0x00000002UL)            /*!< Session request */
+#define USB_OTG_GOTGCTL_HNGSCS                  (0x00000100UL)            /*!< Host negotiation success */
+#define USB_OTG_GOTGCTL_HNPRQ                   (0x00000200UL)            /*!< HNP request */
+#define USB_OTG_GOTGCTL_HSHNPEN                 (0x00000400UL)            /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_DHNPEN                  (0x00000800UL)            /*!< Device HNP enabled */
+#define USB_OTG_GOTGCTL_CIDSTS                  (0x00010000UL)            /*!< Connector ID status */
+#define USB_OTG_GOTGCTL_DBCT                    (0x00020000UL)            /*!< Long/short debounce time */
+#define USB_OTG_GOTGCTL_ASVLD                   (0x00040000UL)            /*!< A-session valid */
+#define USB_OTG_GOTGCTL_BSVLD                   (0x00080000UL)            /*!< B-session valid */
 
 /********************  Bit definition forUSB_OTG_HCFG register  ********************/
 
-#define USB_OTG_HCFG_FSLSPCS                 ((uint32_t)0x00000003)            /*!< FS/LS PHY clock select */
-#define USB_OTG_HCFG_FSLSPCS_0               ((uint32_t)0x00000001)            /*!<Bit 0 */
-#define USB_OTG_HCFG_FSLSPCS_1               ((uint32_t)0x00000002)            /*!<Bit 1 */
-#define USB_OTG_HCFG_FSLSS                   ((uint32_t)0x00000004)            /*!< FS- and LS-only support */
+#define USB_OTG_HCFG_FSLSPCS                 (0x00000003UL)            /*!< FS/LS PHY clock select */
+#define USB_OTG_HCFG_FSLSPCS_0               (0x00000001UL)            /*!<Bit 0 */
+#define USB_OTG_HCFG_FSLSPCS_1               (0x00000002UL)            /*!<Bit 1 */
+#define USB_OTG_HCFG_FSLSS                   (0x00000004UL)            /*!< FS- and LS-only support */
 
 /********************  Bit definition forUSB_OTG_DCFG register  ********************/
 
-#define USB_OTG_DCFG_DSPD                    ((uint32_t)0x00000003)            /*!< Device speed */
-#define USB_OTG_DCFG_DSPD_0                  ((uint32_t)0x00000001)            /*!<Bit 0 */
-#define USB_OTG_DCFG_DSPD_1                  ((uint32_t)0x00000002)            /*!<Bit 1 */
-#define USB_OTG_DCFG_NZLSOHSK                ((uint32_t)0x00000004)            /*!< Nonzero-length status OUT handshake */
+#define USB_OTG_DCFG_DSPD                    (0x00000003UL)            /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0                  (0x00000001UL)            /*!<Bit 0 */
+#define USB_OTG_DCFG_DSPD_1                  (0x00000002UL)            /*!<Bit 1 */
+#define USB_OTG_DCFG_NZLSOHSK                (0x00000004UL)            /*!< Nonzero-length status OUT handshake */
 
-#define USB_OTG_DCFG_DAD                     ((uint32_t)0x000007F0)            /*!< Device address */
-#define USB_OTG_DCFG_DAD_0                   ((uint32_t)0x00000010)            /*!<Bit 0 */
-#define USB_OTG_DCFG_DAD_1                   ((uint32_t)0x00000020)            /*!<Bit 1 */
-#define USB_OTG_DCFG_DAD_2                   ((uint32_t)0x00000040)            /*!<Bit 2 */
-#define USB_OTG_DCFG_DAD_3                   ((uint32_t)0x00000080)            /*!<Bit 3 */
-#define USB_OTG_DCFG_DAD_4                   ((uint32_t)0x00000100)            /*!<Bit 4 */
-#define USB_OTG_DCFG_DAD_5                   ((uint32_t)0x00000200)            /*!<Bit 5 */
-#define USB_OTG_DCFG_DAD_6                   ((uint32_t)0x00000400)            /*!<Bit 6 */
+#define USB_OTG_DCFG_DAD                     (0x000007F0UL)            /*!< Device address */
+#define USB_OTG_DCFG_DAD_0                   (0x00000010UL)            /*!<Bit 0 */
+#define USB_OTG_DCFG_DAD_1                   (0x00000020UL)            /*!<Bit 1 */
+#define USB_OTG_DCFG_DAD_2                   (0x00000040UL)            /*!<Bit 2 */
+#define USB_OTG_DCFG_DAD_3                   (0x00000080UL)            /*!<Bit 3 */
+#define USB_OTG_DCFG_DAD_4                   (0x00000100UL)            /*!<Bit 4 */
+#define USB_OTG_DCFG_DAD_5                   (0x00000200UL)            /*!<Bit 5 */
+#define USB_OTG_DCFG_DAD_6                   (0x00000400UL)            /*!<Bit 6 */
 
-#define USB_OTG_DCFG_PFIVL                   ((uint32_t)0x00001800)            /*!< Periodic (micro)frame interval */
-#define USB_OTG_DCFG_PFIVL_0                 ((uint32_t)0x00000800)            /*!<Bit 0 */
-#define USB_OTG_DCFG_PFIVL_1                 ((uint32_t)0x00001000)            /*!<Bit 1 */
+#define USB_OTG_DCFG_PFIVL                   (0x00001800UL)            /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0                 (0x00000800UL)            /*!<Bit 0 */
+#define USB_OTG_DCFG_PFIVL_1                 (0x00001000UL)            /*!<Bit 1 */
 
-#define USB_OTG_DCFG_PERSCHIVL               ((uint32_t)0x03000000)            /*!< Periodic scheduling interval */
-#define USB_OTG_DCFG_PERSCHIVL_0             ((uint32_t)0x01000000)            /*!<Bit 0 */
-#define USB_OTG_DCFG_PERSCHIVL_1             ((uint32_t)0x02000000)            /*!<Bit 1 */
+#define USB_OTG_DCFG_PERSCHIVL               (0x03000000UL)            /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0             (0x01000000UL)            /*!<Bit 0 */
+#define USB_OTG_DCFG_PERSCHIVL_1             (0x02000000UL)            /*!<Bit 1 */
 
 /********************  Bit definition forUSB_OTG_PCGCR register  ********************/
-#define USB_OTG_PCGCR_STPPCLK                 ((uint32_t)0x00000001)            /*!< Stop PHY clock */
-#define USB_OTG_PCGCR_GATEHCLK                ((uint32_t)0x00000002)            /*!< Gate HCLK */
-#define USB_OTG_PCGCR_PHYSUSP                 ((uint32_t)0x00000010)            /*!< PHY suspended */
+#define USB_OTG_PCGCR_STPPCLK                 (0x00000001UL)            /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK                (0x00000002UL)            /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP                 (0x00000010UL)            /*!< PHY suspended */
 
 /********************  Bit definition forUSB_OTG_GOTGINT register  ********************/
-#define USB_OTG_GOTGINT_SEDET                   ((uint32_t)0x00000004)            /*!< Session end detected */
-#define USB_OTG_GOTGINT_SRSSCHG                 ((uint32_t)0x00000100)            /*!< Session request success status change */
-#define USB_OTG_GOTGINT_HNSSCHG                 ((uint32_t)0x00000200)            /*!< Host negotiation success status change */
-#define USB_OTG_GOTGINT_HNGDET                  ((uint32_t)0x00020000)            /*!< Host negotiation detected */
-#define USB_OTG_GOTGINT_ADTOCHG                 ((uint32_t)0x00040000)            /*!< A-device timeout change */
-#define USB_OTG_GOTGINT_DBCDNE                  ((uint32_t)0x00080000)            /*!< Debounce done */
+#define USB_OTG_GOTGINT_SEDET                   (0x00000004UL)            /*!< Session end detected */
+#define USB_OTG_GOTGINT_SRSSCHG                 (0x00000100UL)            /*!< Session request success status change */
+#define USB_OTG_GOTGINT_HNSSCHG                 (0x00000200UL)            /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET                  (0x00020000UL)            /*!< Host negotiation detected */
+#define USB_OTG_GOTGINT_ADTOCHG                 (0x00040000UL)            /*!< A-device timeout change */
+#define USB_OTG_GOTGINT_DBCDNE                  (0x00080000UL)            /*!< Debounce done */
 
 /********************  Bit definition forUSB_OTG_DCTL register  ********************/
-#define USB_OTG_DCTL_RWUSIG                  ((uint32_t)0x00000001)            /*!< Remote wakeup signaling */
-#define USB_OTG_DCTL_SDIS                    ((uint32_t)0x00000002)            /*!< Soft disconnect */
-#define USB_OTG_DCTL_GINSTS                  ((uint32_t)0x00000004)            /*!< Global IN NAK status */
-#define USB_OTG_DCTL_GONSTS                  ((uint32_t)0x00000008)            /*!< Global OUT NAK status */
+#define USB_OTG_DCTL_RWUSIG                  (0x00000001UL)            /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS                    (0x00000002UL)            /*!< Soft disconnect */
+#define USB_OTG_DCTL_GINSTS                  (0x00000004UL)            /*!< Global IN NAK status */
+#define USB_OTG_DCTL_GONSTS                  (0x00000008UL)            /*!< Global OUT NAK status */
 
-#define USB_OTG_DCTL_TCTL                    ((uint32_t)0x00000070)            /*!< Test control */
-#define USB_OTG_DCTL_TCTL_0                  ((uint32_t)0x00000010)            /*!<Bit 0 */
-#define USB_OTG_DCTL_TCTL_1                  ((uint32_t)0x00000020)            /*!<Bit 1 */
-#define USB_OTG_DCTL_TCTL_2                  ((uint32_t)0x00000040)            /*!<Bit 2 */
-#define USB_OTG_DCTL_SGINAK                  ((uint32_t)0x00000080)            /*!< Set global IN NAK */
-#define USB_OTG_DCTL_CGINAK                  ((uint32_t)0x00000100)            /*!< Clear global IN NAK */
-#define USB_OTG_DCTL_SGONAK                  ((uint32_t)0x00000200)            /*!< Set global OUT NAK */
-#define USB_OTG_DCTL_CGONAK                  ((uint32_t)0x00000400)            /*!< Clear global OUT NAK */
-#define USB_OTG_DCTL_POPRGDNE                ((uint32_t)0x00000800)            /*!< Power-on programming done */
+#define USB_OTG_DCTL_TCTL                    (0x00000070UL)            /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0                  (0x00000010UL)            /*!<Bit 0 */
+#define USB_OTG_DCTL_TCTL_1                  (0x00000020UL)            /*!<Bit 1 */
+#define USB_OTG_DCTL_TCTL_2                  (0x00000040UL)            /*!<Bit 2 */
+#define USB_OTG_DCTL_SGINAK                  (0x00000080UL)            /*!< Set global IN NAK */
+#define USB_OTG_DCTL_CGINAK                  (0x00000100UL)            /*!< Clear global IN NAK */
+#define USB_OTG_DCTL_SGONAK                  (0x00000200UL)            /*!< Set global OUT NAK */
+#define USB_OTG_DCTL_CGONAK                  (0x00000400UL)            /*!< Clear global OUT NAK */
+#define USB_OTG_DCTL_POPRGDNE                (0x00000800UL)            /*!< Power-on programming done */
 
 /********************  Bit definition forUSB_OTG_HFIR register  ********************/
-#define USB_OTG_HFIR_FRIVL                   ((uint32_t)0x0000FFFF)            /*!< Frame interval */
+#define USB_OTG_HFIR_FRIVL                   (0x0000FFFFUL)            /*!< Frame interval */
 
 /********************  Bit definition forUSB_OTG_HFNUM register  ********************/
-#define USB_OTG_HFNUM_FRNUM                   ((uint32_t)0x0000FFFF)            /*!< Frame number */
-#define USB_OTG_HFNUM_FTREM                   ((uint32_t)0xFFFF0000)            /*!< Frame time remaining */
+#define USB_OTG_HFNUM_FRNUM                   (0x0000FFFFUL)            /*!< Frame number */
+#define USB_OTG_HFNUM_FTREM                   (0xFFFF0000UL)            /*!< Frame time remaining */
 
 /********************  Bit definition forUSB_OTG_DSTS register  ********************/
-#define USB_OTG_DSTS_SUSPSTS                 ((uint32_t)0x00000001)            /*!< Suspend status */
+#define USB_OTG_DSTS_SUSPSTS                 (0x00000001UL)            /*!< Suspend status */
 
-#define USB_OTG_DSTS_ENUMSPD                 ((uint32_t)0x00000006)            /*!< Enumerated speed */
-#define USB_OTG_DSTS_ENUMSPD_0               ((uint32_t)0x00000002)            /*!<Bit 0 */
-#define USB_OTG_DSTS_ENUMSPD_1               ((uint32_t)0x00000004)            /*!<Bit 1 */
-#define USB_OTG_DSTS_EERR                    ((uint32_t)0x00000008)            /*!< Erratic error */
-#define USB_OTG_DSTS_FNSOF                   ((uint32_t)0x003FFF00)            /*!< Frame number of the received SOF */
+#define USB_OTG_DSTS_ENUMSPD                 (0x00000006UL)            /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0               (0x00000002UL)            /*!<Bit 0 */
+#define USB_OTG_DSTS_ENUMSPD_1               (0x00000004UL)            /*!<Bit 1 */
+#define USB_OTG_DSTS_EERR                    (0x00000008UL)            /*!< Erratic error */
+#define USB_OTG_DSTS_FNSOF                   (0x003FFF00UL)            /*!< Frame number of the received SOF */
 
 /********************  Bit definition forUSB_OTG_GAHBCFG register  ********************/
-#define USB_OTG_GAHBCFG_GINT                    ((uint32_t)0x00000001)            /*!< Global interrupt mask */
+#define USB_OTG_GAHBCFG_GINT                    (0x00000001UL)            /*!< Global interrupt mask */
 
-#define USB_OTG_GAHBCFG_HBSTLEN                 ((uint32_t)0x0000001E)            /*!< Burst length/type */
-#define USB_OTG_GAHBCFG_HBSTLEN_0               ((uint32_t)0x00000002)            /*!<Bit 0 */
-#define USB_OTG_GAHBCFG_HBSTLEN_1               ((uint32_t)0x00000004)            /*!<Bit 1 */
-#define USB_OTG_GAHBCFG_HBSTLEN_2               ((uint32_t)0x00000008)            /*!<Bit 2 */
-#define USB_OTG_GAHBCFG_HBSTLEN_3               ((uint32_t)0x00000010)            /*!<Bit 3 */
-#define USB_OTG_GAHBCFG_DMAEN                   ((uint32_t)0x00000020)            /*!< DMA enable */
-#define USB_OTG_GAHBCFG_TXFELVL                 ((uint32_t)0x00000080)            /*!< TxFIFO empty level */
-#define USB_OTG_GAHBCFG_PTXFELVL                ((uint32_t)0x00000100)            /*!< Periodic TxFIFO empty level */
+#define USB_OTG_GAHBCFG_HBSTLEN                 (0x0000001EUL)            /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0               (0x00000002UL)            /*!<Bit 0 */
+#define USB_OTG_GAHBCFG_HBSTLEN_1               (0x00000004UL)            /*!<Bit 1 */
+#define USB_OTG_GAHBCFG_HBSTLEN_2               (0x00000008UL)            /*!<Bit 2 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3               (0x00000010UL)            /*!<Bit 3 */
+#define USB_OTG_GAHBCFG_DMAEN                   (0x00000020UL)            /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL                 (0x00000080UL)            /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL                (0x00000100UL)            /*!< Periodic TxFIFO empty level */
 
 /********************  Bit definition forUSB_OTG_GUSBCFG register  ********************/
 
-#define USB_OTG_GUSBCFG_TOCAL                   ((uint32_t)0x00000007)            /*!< FS timeout calibration */
-#define USB_OTG_GUSBCFG_TOCAL_0                 ((uint32_t)0x00000001)            /*!<Bit 0 */
-#define USB_OTG_GUSBCFG_TOCAL_1                 ((uint32_t)0x00000002)            /*!<Bit 1 */
-#define USB_OTG_GUSBCFG_TOCAL_2                 ((uint32_t)0x00000004)            /*!<Bit 2 */
-#define USB_OTG_GUSBCFG_PHYSEL                  ((uint32_t)0x00000040)            /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
-#define USB_OTG_GUSBCFG_SRPCAP                  ((uint32_t)0x00000100)            /*!< SRP-capable */
-#define USB_OTG_GUSBCFG_HNPCAP                  ((uint32_t)0x00000200)            /*!< HNP-capable */
+#define USB_OTG_GUSBCFG_TOCAL                   (0x00000007UL)            /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0                 (0x00000001UL)            /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TOCAL_1                 (0x00000002UL)            /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TOCAL_2                 (0x00000004UL)            /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_PHYSEL                  (0x00000040UL)            /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP                  (0x00000100UL)            /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP                  (0x00000200UL)            /*!< HNP-capable */
 
-#define USB_OTG_GUSBCFG_TRDT                    ((uint32_t)0x00003C00)            /*!< USB turnaround time */
-#define USB_OTG_GUSBCFG_TRDT_0                  ((uint32_t)0x00000400)            /*!<Bit 0 */
-#define USB_OTG_GUSBCFG_TRDT_1                  ((uint32_t)0x00000800)            /*!<Bit 1 */
-#define USB_OTG_GUSBCFG_TRDT_2                  ((uint32_t)0x00001000)            /*!<Bit 2 */
-#define USB_OTG_GUSBCFG_TRDT_3                  ((uint32_t)0x00002000)            /*!<Bit 3 */
-#define USB_OTG_GUSBCFG_PHYLPCS                 ((uint32_t)0x00008000)            /*!< PHY Low-power clock select */
-#define USB_OTG_GUSBCFG_ULPIFSLS                ((uint32_t)0x00020000)            /*!< ULPI FS/LS select */
-#define USB_OTG_GUSBCFG_ULPIAR                  ((uint32_t)0x00040000)            /*!< ULPI Auto-resume */
-#define USB_OTG_GUSBCFG_ULPICSM                 ((uint32_t)0x00080000)            /*!< ULPI Clock SuspendM */
-#define USB_OTG_GUSBCFG_ULPIEVBUSD              ((uint32_t)0x00100000)            /*!< ULPI External VBUS Drive */
-#define USB_OTG_GUSBCFG_ULPIEVBUSI              ((uint32_t)0x00200000)            /*!< ULPI external VBUS indicator */
-#define USB_OTG_GUSBCFG_TSDPS                   ((uint32_t)0x00400000)            /*!< TermSel DLine pulsing selection */
-#define USB_OTG_GUSBCFG_PCCI                    ((uint32_t)0x00800000)            /*!< Indicator complement */
-#define USB_OTG_GUSBCFG_PTCI                    ((uint32_t)0x01000000)            /*!< Indicator pass through */
-#define USB_OTG_GUSBCFG_ULPIIPD                 ((uint32_t)0x02000000)            /*!< ULPI interface protect disable */
-#define USB_OTG_GUSBCFG_FHMOD                   ((uint32_t)0x20000000)            /*!< Forced host mode */
-#define USB_OTG_GUSBCFG_FDMOD                   ((uint32_t)0x40000000)            /*!< Forced peripheral mode */
-#define USB_OTG_GUSBCFG_CTXPKT                  ((uint32_t)0x80000000)            /*!< Corrupt Tx packet */
+#define USB_OTG_GUSBCFG_TRDT                    (0x00003C00UL)            /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0                  (0x00000400UL)            /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TRDT_1                  (0x00000800UL)            /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TRDT_2                  (0x00001000UL)            /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_TRDT_3                  (0x00002000UL)            /*!<Bit 3 */
+#define USB_OTG_GUSBCFG_PHYLPCS                 (0x00008000UL)            /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS                (0x00020000UL)            /*!< ULPI FS/LS select */
+#define USB_OTG_GUSBCFG_ULPIAR                  (0x00040000UL)            /*!< ULPI Auto-resume */
+#define USB_OTG_GUSBCFG_ULPICSM                 (0x00080000UL)            /*!< ULPI Clock SuspendM */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD              (0x00100000UL)            /*!< ULPI External VBUS Drive */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI              (0x00200000UL)            /*!< ULPI external VBUS indicator */
+#define USB_OTG_GUSBCFG_TSDPS                   (0x00400000UL)            /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI                    (0x00800000UL)            /*!< Indicator complement */
+#define USB_OTG_GUSBCFG_PTCI                    (0x01000000UL)            /*!< Indicator pass through */
+#define USB_OTG_GUSBCFG_ULPIIPD                 (0x02000000UL)            /*!< ULPI interface protect disable */
+#define USB_OTG_GUSBCFG_FHMOD                   (0x20000000UL)            /*!< Forced host mode */
+#define USB_OTG_GUSBCFG_FDMOD                   (0x40000000UL)            /*!< Forced peripheral mode */
+#define USB_OTG_GUSBCFG_CTXPKT                  (0x80000000UL)            /*!< Corrupt Tx packet */
 
 /********************  Bit definition forUSB_OTG_GRSTCTL register  ********************/
-#define USB_OTG_GRSTCTL_CSRST                   ((uint32_t)0x00000001)            /*!< Core soft reset */
-#define USB_OTG_GRSTCTL_HSRST                   ((uint32_t)0x00000002)            /*!< HCLK soft reset */
-#define USB_OTG_GRSTCTL_FCRST                   ((uint32_t)0x00000004)            /*!< Host frame counter reset */
-#define USB_OTG_GRSTCTL_RXFFLSH                 ((uint32_t)0x00000010)            /*!< RxFIFO flush */
-#define USB_OTG_GRSTCTL_TXFFLSH                 ((uint32_t)0x00000020)            /*!< TxFIFO flush */
+#define USB_OTG_GRSTCTL_CSRST                   (0x00000001UL)            /*!< Core soft reset */
+#define USB_OTG_GRSTCTL_HSRST                   (0x00000002UL)            /*!< HCLK soft reset */
+#define USB_OTG_GRSTCTL_FCRST                   (0x00000004UL)            /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH                 (0x00000010UL)            /*!< RxFIFO flush */
+#define USB_OTG_GRSTCTL_TXFFLSH                 (0x00000020UL)            /*!< TxFIFO flush */
 
-#define USB_OTG_GRSTCTL_TXFNUM                  ((uint32_t)0x000007C0)            /*!< TxFIFO number */
-#define USB_OTG_GRSTCTL_TXFNUM_0                ((uint32_t)0x00000040)            /*!<Bit 0 */
-#define USB_OTG_GRSTCTL_TXFNUM_1                ((uint32_t)0x00000080)            /*!<Bit 1 */
-#define USB_OTG_GRSTCTL_TXFNUM_2                ((uint32_t)0x00000100)            /*!<Bit 2 */
-#define USB_OTG_GRSTCTL_TXFNUM_3                ((uint32_t)0x00000200)            /*!<Bit 3 */
-#define USB_OTG_GRSTCTL_TXFNUM_4                ((uint32_t)0x00000400)            /*!<Bit 4 */
-#define USB_OTG_GRSTCTL_DMAREQ                  ((uint32_t)0x40000000)            /*!< DMA request signal */
-#define USB_OTG_GRSTCTL_AHBIDL                  ((uint32_t)0x80000000)            /*!< AHB master idle */
+#define USB_OTG_GRSTCTL_TXFNUM                  (0x000007C0UL)            /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0                (0x00000040UL)            /*!<Bit 0 */
+#define USB_OTG_GRSTCTL_TXFNUM_1                (0x00000080UL)            /*!<Bit 1 */
+#define USB_OTG_GRSTCTL_TXFNUM_2                (0x00000100UL)            /*!<Bit 2 */
+#define USB_OTG_GRSTCTL_TXFNUM_3                (0x00000200UL)            /*!<Bit 3 */
+#define USB_OTG_GRSTCTL_TXFNUM_4                (0x00000400UL)            /*!<Bit 4 */
+#define USB_OTG_GRSTCTL_DMAREQ                  (0x40000000UL)            /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL                  (0x80000000UL)            /*!< AHB master idle */
 
 /********************  Bit definition forUSB_OTG_DIEPMSK register  ********************/
-#define USB_OTG_DIEPMSK_XFRCM                   ((uint32_t)0x00000001)            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DIEPMSK_EPDM                    ((uint32_t)0x00000002)            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DIEPMSK_TOM                     ((uint32_t)0x00000008)            /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPMSK_ITTXFEMSK               ((uint32_t)0x00000010)            /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DIEPMSK_INEPNMM                 ((uint32_t)0x00000020)            /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DIEPMSK_INEPNEM                 ((uint32_t)0x00000040)            /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DIEPMSK_TXFURM                  ((uint32_t)0x00000100)            /*!< FIFO underrun mask */
-#define USB_OTG_DIEPMSK_BIM                     ((uint32_t)0x00000200)            /*!< BNA interrupt mask */
+#define USB_OTG_DIEPMSK_XFRCM                   (0x00000001UL)            /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPMSK_EPDM                    (0x00000002UL)            /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPMSK_TOM                     (0x00000008UL)            /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK               (0x00000010UL)            /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPMSK_INEPNMM                 (0x00000020UL)            /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPMSK_INEPNEM                 (0x00000040UL)            /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPMSK_TXFURM                  (0x00000100UL)            /*!< FIFO underrun mask */
+#define USB_OTG_DIEPMSK_BIM                     (0x00000200UL)            /*!< BNA interrupt mask */
 
 /********************  Bit definition forUSB_OTG_HPTXSTS register  ********************/
-#define USB_OTG_HPTXSTS_PTXFSAVL                ((uint32_t)0x0000FFFF)            /*!< Periodic transmit data FIFO space available */
+#define USB_OTG_HPTXSTS_PTXFSAVL                (0x0000FFFFUL)            /*!< Periodic transmit data FIFO space available */
 
-#define USB_OTG_HPTXSTS_PTXQSAV                 ((uint32_t)0x00FF0000)            /*!< Periodic transmit request queue space available */
-#define USB_OTG_HPTXSTS_PTXQSAV_0               ((uint32_t)0x00010000)            /*!<Bit 0 */
-#define USB_OTG_HPTXSTS_PTXQSAV_1               ((uint32_t)0x00020000)            /*!<Bit 1 */
-#define USB_OTG_HPTXSTS_PTXQSAV_2               ((uint32_t)0x00040000)            /*!<Bit 2 */
-#define USB_OTG_HPTXSTS_PTXQSAV_3               ((uint32_t)0x00080000)            /*!<Bit 3 */
-#define USB_OTG_HPTXSTS_PTXQSAV_4               ((uint32_t)0x00100000)            /*!<Bit 4 */
-#define USB_OTG_HPTXSTS_PTXQSAV_5               ((uint32_t)0x00200000)            /*!<Bit 5 */
-#define USB_OTG_HPTXSTS_PTXQSAV_6               ((uint32_t)0x00400000)            /*!<Bit 6 */
-#define USB_OTG_HPTXSTS_PTXQSAV_7               ((uint32_t)0x00800000)            /*!<Bit 7 */
+#define USB_OTG_HPTXSTS_PTXQSAV                 (0x00FF0000UL)            /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0               (0x00010000UL)            /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1               (0x00020000UL)            /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2               (0x00040000UL)            /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3               (0x00080000UL)            /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4               (0x00100000UL)            /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5               (0x00200000UL)            /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6               (0x00400000UL)            /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7               (0x00800000UL)            /*!<Bit 7 */
 
-#define USB_OTG_HPTXSTS_PTXQTOP                 ((uint32_t)0xFF000000)            /*!< Top of the periodic transmit request queue */
-#define USB_OTG_HPTXSTS_PTXQTOP_0               ((uint32_t)0x01000000)            /*!<Bit 0 */
-#define USB_OTG_HPTXSTS_PTXQTOP_1               ((uint32_t)0x02000000)            /*!<Bit 1 */
-#define USB_OTG_HPTXSTS_PTXQTOP_2               ((uint32_t)0x04000000)            /*!<Bit 2 */
-#define USB_OTG_HPTXSTS_PTXQTOP_3               ((uint32_t)0x08000000)            /*!<Bit 3 */
-#define USB_OTG_HPTXSTS_PTXQTOP_4               ((uint32_t)0x10000000)            /*!<Bit 4 */
-#define USB_OTG_HPTXSTS_PTXQTOP_5               ((uint32_t)0x20000000)            /*!<Bit 5 */
-#define USB_OTG_HPTXSTS_PTXQTOP_6               ((uint32_t)0x40000000)            /*!<Bit 6 */
-#define USB_OTG_HPTXSTS_PTXQTOP_7               ((uint32_t)0x80000000)            /*!<Bit 7 */
+#define USB_OTG_HPTXSTS_PTXQTOP                 (0xFF000000UL)            /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0               (0x01000000UL)            /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1               (0x02000000UL)            /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2               (0x04000000UL)            /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3               (0x08000000UL)            /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4               (0x10000000UL)            /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5               (0x20000000UL)            /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6               (0x40000000UL)            /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7               (0x80000000UL)            /*!<Bit 7 */
 
 /********************  Bit definition forUSB_OTG_HAINT register  ********************/
-#define USB_OTG_HAINT_HAINT                   ((uint32_t)0x0000FFFF)            /*!< Channel interrupts */
+#define USB_OTG_HAINT_HAINT                   (0x0000FFFFUL)            /*!< Channel interrupts */
 
 /********************  Bit definition forUSB_OTG_DOEPMSK register  ********************/
-#define USB_OTG_DOEPMSK_XFRCM                   ((uint32_t)0x00000001)            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DOEPMSK_EPDM                    ((uint32_t)0x00000002)            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DOEPMSK_STUPM                   ((uint32_t)0x00000008)            /*!< SETUP phase done mask */
-#define USB_OTG_DOEPMSK_OTEPDM                  ((uint32_t)0x00000010)            /*!< OUT token received when endpoint disabled mask */
-#define USB_OTG_DOEPMSK_B2BSTUP                 ((uint32_t)0x00000040)            /*!< Back-to-back SETUP packets received mask */
-#define USB_OTG_DOEPMSK_OPEM                    ((uint32_t)0x00000100)            /*!< OUT packet error mask */
-#define USB_OTG_DOEPMSK_BOIM                    ((uint32_t)0x00000200)            /*!< BNA interrupt mask */
+#define USB_OTG_DOEPMSK_XFRCM                   (0x00000001UL)            /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM                    (0x00000002UL)            /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPMSK_STUPM                   (0x00000008UL)            /*!< SETUP phase done mask */
+#define USB_OTG_DOEPMSK_OTEPDM                  (0x00000010UL)            /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_B2BSTUP                 (0x00000040UL)            /*!< Back-to-back SETUP packets received mask */
+#define USB_OTG_DOEPMSK_OPEM                    (0x00000100UL)            /*!< OUT packet error mask */
+#define USB_OTG_DOEPMSK_BOIM                    (0x00000200UL)            /*!< BNA interrupt mask */
 
 /********************  Bit definition forUSB_OTG_GINTSTS register  ********************/
-#define USB_OTG_GINTSTS_CMOD                    ((uint32_t)0x00000001)            /*!< Current mode of operation */
-#define USB_OTG_GINTSTS_MMIS                    ((uint32_t)0x00000002)            /*!< Mode mismatch interrupt */
-#define USB_OTG_GINTSTS_OTGINT                  ((uint32_t)0x00000004)            /*!< OTG interrupt */
-#define USB_OTG_GINTSTS_SOF                     ((uint32_t)0x00000008)            /*!< Start of frame */
-#define USB_OTG_GINTSTS_RXFLVL                  ((uint32_t)0x00000010)            /*!< RxFIFO nonempty */
-#define USB_OTG_GINTSTS_NPTXFE                  ((uint32_t)0x00000020)            /*!< Nonperiodic TxFIFO empty */
-#define USB_OTG_GINTSTS_GINAKEFF                ((uint32_t)0x00000040)            /*!< Global IN nonperiodic NAK effective */
-#define USB_OTG_GINTSTS_BOUTNAKEFF              ((uint32_t)0x00000080)            /*!< Global OUT NAK effective */
-#define USB_OTG_GINTSTS_ESUSP                   ((uint32_t)0x00000400)            /*!< Early suspend */
-#define USB_OTG_GINTSTS_USBSUSP                 ((uint32_t)0x00000800)            /*!< USB suspend */
-#define USB_OTG_GINTSTS_USBRST                  ((uint32_t)0x00001000)            /*!< USB reset */
-#define USB_OTG_GINTSTS_ENUMDNE                 ((uint32_t)0x00002000)            /*!< Enumeration done */
-#define USB_OTG_GINTSTS_ISOODRP                 ((uint32_t)0x00004000)            /*!< Isochronous OUT packet dropped interrupt */
-#define USB_OTG_GINTSTS_EOPF                    ((uint32_t)0x00008000)            /*!< End of periodic frame interrupt */
-#define USB_OTG_GINTSTS_IEPINT                  ((uint32_t)0x00040000)            /*!< IN endpoint interrupt */
-#define USB_OTG_GINTSTS_OEPINT                  ((uint32_t)0x00080000)            /*!< OUT endpoint interrupt */
-#define USB_OTG_GINTSTS_IISOIXFR                ((uint32_t)0x00100000)            /*!< Incomplete isochronous IN transfer */
-#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT       ((uint32_t)0x00200000)            /*!< Incomplete periodic transfer */
-#define USB_OTG_GINTSTS_DATAFSUSP               ((uint32_t)0x00400000)            /*!< Data fetch suspended */
-#define USB_OTG_GINTSTS_HPRTINT                 ((uint32_t)0x01000000)            /*!< Host port interrupt */
-#define USB_OTG_GINTSTS_HCINT                   ((uint32_t)0x02000000)            /*!< Host channels interrupt */
-#define USB_OTG_GINTSTS_PTXFE                   ((uint32_t)0x04000000)            /*!< Periodic TxFIFO empty */
-#define USB_OTG_GINTSTS_CIDSCHG                 ((uint32_t)0x10000000)            /*!< Connector ID status change */
-#define USB_OTG_GINTSTS_DISCINT                 ((uint32_t)0x20000000)            /*!< Disconnect detected interrupt */
-#define USB_OTG_GINTSTS_SRQINT                  ((uint32_t)0x40000000)            /*!< Session request/new session detected interrupt */
-#define USB_OTG_GINTSTS_WKUINT                  ((uint32_t)0x80000000)            /*!< Resume/remote wakeup detected interrupt */
+#define USB_OTG_GINTSTS_CMOD                    (0x00000001UL)            /*!< Current mode of operation */
+#define USB_OTG_GINTSTS_MMIS                    (0x00000002UL)            /*!< Mode mismatch interrupt */
+#define USB_OTG_GINTSTS_OTGINT                  (0x00000004UL)            /*!< OTG interrupt */
+#define USB_OTG_GINTSTS_SOF                     (0x00000008UL)            /*!< Start of frame */
+#define USB_OTG_GINTSTS_RXFLVL                  (0x00000010UL)            /*!< RxFIFO nonempty */
+#define USB_OTG_GINTSTS_NPTXFE                  (0x00000020UL)            /*!< Nonperiodic TxFIFO empty */
+#define USB_OTG_GINTSTS_GINAKEFF                (0x00000040UL)            /*!< Global IN nonperiodic NAK effective */
+#define USB_OTG_GINTSTS_BOUTNAKEFF              (0x00000080UL)            /*!< Global OUT NAK effective */
+#define USB_OTG_GINTSTS_ESUSP                   (0x00000400UL)            /*!< Early suspend */
+#define USB_OTG_GINTSTS_USBSUSP                 (0x00000800UL)            /*!< USB suspend */
+#define USB_OTG_GINTSTS_USBRST                  (0x00001000UL)            /*!< USB reset */
+#define USB_OTG_GINTSTS_ENUMDNE                 (0x00002000UL)            /*!< Enumeration done */
+#define USB_OTG_GINTSTS_ISOODRP                 (0x00004000UL)            /*!< Isochronous OUT packet dropped interrupt */
+#define USB_OTG_GINTSTS_EOPF                    (0x00008000UL)            /*!< End of periodic frame interrupt */
+#define USB_OTG_GINTSTS_IEPINT                  (0x00040000UL)            /*!< IN endpoint interrupt */
+#define USB_OTG_GINTSTS_OEPINT                  (0x00080000UL)            /*!< OUT endpoint interrupt */
+#define USB_OTG_GINTSTS_IISOIXFR                (0x00100000UL)            /*!< Incomplete isochronous IN transfer */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT       (0x00200000UL)            /*!< Incomplete periodic transfer */
+#define USB_OTG_GINTSTS_DATAFSUSP               (0x00400000UL)            /*!< Data fetch suspended */
+#define USB_OTG_GINTSTS_HPRTINT                 (0x01000000UL)            /*!< Host port interrupt */
+#define USB_OTG_GINTSTS_HCINT                   (0x02000000UL)            /*!< Host channels interrupt */
+#define USB_OTG_GINTSTS_PTXFE                   (0x04000000UL)            /*!< Periodic TxFIFO empty */
+#define USB_OTG_GINTSTS_CIDSCHG                 (0x10000000UL)            /*!< Connector ID status change */
+#define USB_OTG_GINTSTS_DISCINT                 (0x20000000UL)            /*!< Disconnect detected interrupt */
+#define USB_OTG_GINTSTS_SRQINT                  (0x40000000UL)            /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT                  (0x80000000UL)            /*!< Resume/remote wakeup detected interrupt */
 
 /********************  Bit definition forUSB_OTG_GINTMSK register  ********************/
-#define USB_OTG_GINTMSK_MMISM                   ((uint32_t)0x00000002)            /*!< Mode mismatch interrupt mask */
-#define USB_OTG_GINTMSK_OTGINT                  ((uint32_t)0x00000004)            /*!< OTG interrupt mask */
-#define USB_OTG_GINTMSK_SOFM                    ((uint32_t)0x00000008)            /*!< Start of frame mask */
-#define USB_OTG_GINTMSK_RXFLVLM                 ((uint32_t)0x00000010)            /*!< Receive FIFO nonempty mask */
-#define USB_OTG_GINTMSK_NPTXFEM                 ((uint32_t)0x00000020)            /*!< Nonperiodic TxFIFO empty mask */
-#define USB_OTG_GINTMSK_GINAKEFFM               ((uint32_t)0x00000040)            /*!< Global nonperiodic IN NAK effective mask */
-#define USB_OTG_GINTMSK_GONAKEFFM               ((uint32_t)0x00000080)            /*!< Global OUT NAK effective mask */
-#define USB_OTG_GINTMSK_ESUSPM                  ((uint32_t)0x00000400)            /*!< Early suspend mask */
-#define USB_OTG_GINTMSK_USBSUSPM                ((uint32_t)0x00000800)            /*!< USB suspend mask */
-#define USB_OTG_GINTMSK_USBRST                  ((uint32_t)0x00001000)            /*!< USB reset mask */
-#define USB_OTG_GINTMSK_ENUMDNEM                ((uint32_t)0x00002000)            /*!< Enumeration done mask */
-#define USB_OTG_GINTMSK_ISOODRPM                ((uint32_t)0x00004000)            /*!< Isochronous OUT packet dropped interrupt mask */
-#define USB_OTG_GINTMSK_EOPFM                   ((uint32_t)0x00008000)            /*!< End of periodic frame interrupt mask */
-#define USB_OTG_GINTMSK_EPMISM                  ((uint32_t)0x00020000)            /*!< Endpoint mismatch interrupt mask */
-#define USB_OTG_GINTMSK_IEPINT                  ((uint32_t)0x00040000)            /*!< IN endpoints interrupt mask */
-#define USB_OTG_GINTMSK_OEPINT                  ((uint32_t)0x00080000)            /*!< OUT endpoints interrupt mask */
-#define USB_OTG_GINTMSK_IISOIXFRM               ((uint32_t)0x00100000)            /*!< Incomplete isochronous IN transfer mask */
-#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM         ((uint32_t)0x00200000)            /*!< Incomplete periodic transfer mask */
-#define USB_OTG_GINTMSK_FSUSPM                  ((uint32_t)0x00400000)            /*!< Data fetch suspended mask */
-#define USB_OTG_GINTMSK_PRTIM                   ((uint32_t)0x01000000)            /*!< Host port interrupt mask */
-#define USB_OTG_GINTMSK_HCIM                    ((uint32_t)0x02000000)            /*!< Host channels interrupt mask */
-#define USB_OTG_GINTMSK_PTXFEM                  ((uint32_t)0x04000000)            /*!< Periodic TxFIFO empty mask */
-#define USB_OTG_GINTMSK_CIDSCHGM                ((uint32_t)0x10000000)            /*!< Connector ID status change mask */
-#define USB_OTG_GINTMSK_DISCINT                 ((uint32_t)0x20000000)            /*!< Disconnect detected interrupt mask */
-#define USB_OTG_GINTMSK_SRQIM                   ((uint32_t)0x40000000)            /*!< Session request/new session detected interrupt mask */
-#define USB_OTG_GINTMSK_WUIM                    ((uint32_t)0x80000000)            /*!< Resume/remote wakeup detected interrupt mask */
+#define USB_OTG_GINTMSK_MMISM                   (0x00000002UL)            /*!< Mode mismatch interrupt mask */
+#define USB_OTG_GINTMSK_OTGINT                  (0x00000004UL)            /*!< OTG interrupt mask */
+#define USB_OTG_GINTMSK_SOFM                    (0x00000008UL)            /*!< Start of frame mask */
+#define USB_OTG_GINTMSK_RXFLVLM                 (0x00000010UL)            /*!< Receive FIFO nonempty mask */
+#define USB_OTG_GINTMSK_NPTXFEM                 (0x00000020UL)            /*!< Nonperiodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_GINAKEFFM               (0x00000040UL)            /*!< Global nonperiodic IN NAK effective mask */
+#define USB_OTG_GINTMSK_GONAKEFFM               (0x00000080UL)            /*!< Global OUT NAK effective mask */
+#define USB_OTG_GINTMSK_ESUSPM                  (0x00000400UL)            /*!< Early suspend mask */
+#define USB_OTG_GINTMSK_USBSUSPM                (0x00000800UL)            /*!< USB suspend mask */
+#define USB_OTG_GINTMSK_USBRST                  (0x00001000UL)            /*!< USB reset mask */
+#define USB_OTG_GINTMSK_ENUMDNEM                (0x00002000UL)            /*!< Enumeration done mask */
+#define USB_OTG_GINTMSK_ISOODRPM                (0x00004000UL)            /*!< Isochronous OUT packet dropped interrupt mask */
+#define USB_OTG_GINTMSK_EOPFM                   (0x00008000UL)            /*!< End of periodic frame interrupt mask */
+#define USB_OTG_GINTMSK_EPMISM                  (0x00020000UL)            /*!< Endpoint mismatch interrupt mask */
+#define USB_OTG_GINTMSK_IEPINT                  (0x00040000UL)            /*!< IN endpoints interrupt mask */
+#define USB_OTG_GINTMSK_OEPINT                  (0x00080000UL)            /*!< OUT endpoints interrupt mask */
+#define USB_OTG_GINTMSK_IISOIXFRM               (0x00100000UL)            /*!< Incomplete isochronous IN transfer mask */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM         (0x00200000UL)            /*!< Incomplete periodic transfer mask */
+#define USB_OTG_GINTMSK_FSUSPM                  (0x00400000UL)            /*!< Data fetch suspended mask */
+#define USB_OTG_GINTMSK_PRTIM                   (0x01000000UL)            /*!< Host port interrupt mask */
+#define USB_OTG_GINTMSK_HCIM                    (0x02000000UL)            /*!< Host channels interrupt mask */
+#define USB_OTG_GINTMSK_PTXFEM                  (0x04000000UL)            /*!< Periodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_CIDSCHGM                (0x10000000UL)            /*!< Connector ID status change mask */
+#define USB_OTG_GINTMSK_DISCINT                 (0x20000000UL)            /*!< Disconnect detected interrupt mask */
+#define USB_OTG_GINTMSK_SRQIM                   (0x40000000UL)            /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM                    (0x80000000UL)            /*!< Resume/remote wakeup detected interrupt mask */
 
 /********************  Bit definition forUSB_OTG_DAINT register  ********************/
-#define USB_OTG_DAINT_IEPINT                  ((uint32_t)0x0000FFFF)            /*!< IN endpoint interrupt bits */
-#define USB_OTG_DAINT_OEPINT                  ((uint32_t)0xFFFF0000)            /*!< OUT endpoint interrupt bits */
+#define USB_OTG_DAINT_IEPINT                  (0x0000FFFFUL)            /*!< IN endpoint interrupt bits */
+#define USB_OTG_DAINT_OEPINT                  (0xFFFF0000UL)            /*!< OUT endpoint interrupt bits */
 
 /********************  Bit definition forUSB_OTG_HAINTMSK register  ********************/
-#define USB_OTG_HAINTMSK_HAINTM                  ((uint32_t)0x0000FFFF)            /*!< Channel interrupt mask */
+#define USB_OTG_HAINTMSK_HAINTM                  (0x0000FFFFUL)            /*!< Channel interrupt mask */
 
 /********************  Bit definition for USB_OTG_GRXSTSP register  ********************/
-#define USB_OTG_GRXSTSP_EPNUM                    ((uint32_t)0x0000000F)            /*!< IN EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_BCNT                     ((uint32_t)0x00007FF0)            /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_DPID                     ((uint32_t)0x00018000)            /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_PKTSTS                   ((uint32_t)0x001E0000)            /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_EPNUM                    (0x0000000FUL)            /*!< IN EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_BCNT                     (0x00007FF0UL)            /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID                     (0x00018000UL)            /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS                   (0x001E0000UL)            /*!< OUT EP interrupt mask bits */
 
 /********************  Bit definition forUSB_OTG_DAINTMSK register  ********************/
-#define USB_OTG_DAINTMSK_IEPM                    ((uint32_t)0x0000FFFF)            /*!< IN EP interrupt mask bits */
-#define USB_OTG_DAINTMSK_OEPM                    ((uint32_t)0xFFFF0000)            /*!< OUT EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_IEPM                    (0x0000FFFFUL)            /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM                    (0xFFFF0000UL)            /*!< OUT EP interrupt mask bits */
 
 /********************  Bit definition for OTG register  ********************/
 
-#define USB_OTG_CHNUM                   ((uint32_t)0x0000000F)            /*!< Channel number */
-#define USB_OTG_CHNUM_0                 ((uint32_t)0x00000001)            /*!<Bit 0 */
-#define USB_OTG_CHNUM_1                 ((uint32_t)0x00000002)            /*!<Bit 1 */
-#define USB_OTG_CHNUM_2                 ((uint32_t)0x00000004)            /*!<Bit 2 */
-#define USB_OTG_CHNUM_3                 ((uint32_t)0x00000008)            /*!<Bit 3 */
-#define USB_OTG_BCNT                    ((uint32_t)0x00007FF0)            /*!< Byte count */
+#define USB_OTG_CHNUM                   (0x0000000FUL)            /*!< Channel number */
+#define USB_OTG_CHNUM_0                 (0x00000001UL)            /*!<Bit 0 */
+#define USB_OTG_CHNUM_1                 (0x00000002UL)            /*!<Bit 1 */
+#define USB_OTG_CHNUM_2                 (0x00000004UL)            /*!<Bit 2 */
+#define USB_OTG_CHNUM_3                 (0x00000008UL)            /*!<Bit 3 */
+#define USB_OTG_BCNT                    (0x00007FF0UL)            /*!< Byte count */
 
-#define USB_OTG_DPID                    ((uint32_t)0x00018000)            /*!< Data PID */
-#define USB_OTG_DPID_0                  ((uint32_t)0x00008000)            /*!<Bit 0 */
-#define USB_OTG_DPID_1                  ((uint32_t)0x00010000)            /*!<Bit 1 */
+#define USB_OTG_DPID                    (0x00018000UL)            /*!< Data PID */
+#define USB_OTG_DPID_0                  (0x00008000UL)            /*!<Bit 0 */
+#define USB_OTG_DPID_1                  (0x00010000UL)            /*!<Bit 1 */
 
-#define USB_OTG_PKTSTS                  ((uint32_t)0x001E0000)            /*!< Packet status */
-#define USB_OTG_PKTSTS_0                ((uint32_t)0x00020000)            /*!<Bit 0 */
-#define USB_OTG_PKTSTS_1                ((uint32_t)0x00040000)            /*!<Bit 1 */
-#define USB_OTG_PKTSTS_2                ((uint32_t)0x00080000)            /*!<Bit 2 */
-#define USB_OTG_PKTSTS_3                ((uint32_t)0x00100000)            /*!<Bit 3 */
+#define USB_OTG_PKTSTS                  (0x001E0000UL)            /*!< Packet status */
+#define USB_OTG_PKTSTS_0                (0x00020000UL)            /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1                (0x00040000UL)            /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2                (0x00080000UL)            /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3                (0x00100000UL)            /*!<Bit 3 */
 
-#define USB_OTG_EPNUM                   ((uint32_t)0x0000000F)            /*!< Endpoint number */
-#define USB_OTG_EPNUM_0                 ((uint32_t)0x00000001)            /*!<Bit 0 */
-#define USB_OTG_EPNUM_1                 ((uint32_t)0x00000002)            /*!<Bit 1 */
-#define USB_OTG_EPNUM_2                 ((uint32_t)0x00000004)            /*!<Bit 2 */
-#define USB_OTG_EPNUM_3                 ((uint32_t)0x00000008)            /*!<Bit 3 */
+#define USB_OTG_EPNUM                   (0x0000000FUL)            /*!< Endpoint number */
+#define USB_OTG_EPNUM_0                 (0x00000001UL)            /*!<Bit 0 */
+#define USB_OTG_EPNUM_1                 (0x00000002UL)            /*!<Bit 1 */
+#define USB_OTG_EPNUM_2                 (0x00000004UL)            /*!<Bit 2 */
+#define USB_OTG_EPNUM_3                 (0x00000008UL)            /*!<Bit 3 */
 
-#define USB_OTG_FRMNUM                  ((uint32_t)0x01E00000)            /*!< Frame number */
-#define USB_OTG_FRMNUM_0                ((uint32_t)0x00200000)            /*!<Bit 0 */
-#define USB_OTG_FRMNUM_1                ((uint32_t)0x00400000)            /*!<Bit 1 */
-#define USB_OTG_FRMNUM_2                ((uint32_t)0x00800000)            /*!<Bit 2 */
-#define USB_OTG_FRMNUM_3                ((uint32_t)0x01000000)            /*!<Bit 3 */
+#define USB_OTG_FRMNUM                  (0x01E00000UL)            /*!< Frame number */
+#define USB_OTG_FRMNUM_0                (0x00200000UL)            /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1                (0x00400000UL)            /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2                (0x00800000UL)            /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3                (0x01000000UL)            /*!<Bit 3 */
 
 /********************  Bit definition for OTG register  ********************/
 
-#define USB_OTG_CHNUM                   ((uint32_t)0x0000000F)            /*!< Channel number */
-#define USB_OTG_CHNUM_0                 ((uint32_t)0x00000001)            /*!<Bit 0 */
-#define USB_OTG_CHNUM_1                 ((uint32_t)0x00000002)            /*!<Bit 1 */
-#define USB_OTG_CHNUM_2                 ((uint32_t)0x00000004)            /*!<Bit 2 */
-#define USB_OTG_CHNUM_3                 ((uint32_t)0x00000008)            /*!<Bit 3 */
-#define USB_OTG_BCNT                    ((uint32_t)0x00007FF0)            /*!< Byte count */
+#define USB_OTG_CHNUM                   (0x0000000FUL)            /*!< Channel number */
+#define USB_OTG_CHNUM_0                 (0x00000001UL)            /*!<Bit 0 */
+#define USB_OTG_CHNUM_1                 (0x00000002UL)            /*!<Bit 1 */
+#define USB_OTG_CHNUM_2                 (0x00000004UL)            /*!<Bit 2 */
+#define USB_OTG_CHNUM_3                 (0x00000008UL)            /*!<Bit 3 */
+#define USB_OTG_BCNT                    (0x00007FF0UL)            /*!< Byte count */
 
-#define USB_OTG_DPID                    ((uint32_t)0x00018000)            /*!< Data PID */
-#define USB_OTG_DPID_0                  ((uint32_t)0x00008000)            /*!<Bit 0 */
-#define USB_OTG_DPID_1                  ((uint32_t)0x00010000)            /*!<Bit 1 */
+#define USB_OTG_DPID                    (0x00018000UL)            /*!< Data PID */
+#define USB_OTG_DPID_0                  (0x00008000UL)            /*!<Bit 0 */
+#define USB_OTG_DPID_1                  (0x00010000UL)            /*!<Bit 1 */
 
-#define USB_OTG_PKTSTS                  ((uint32_t)0x001E0000)            /*!< Packet status */
-#define USB_OTG_PKTSTS_0                ((uint32_t)0x00020000)            /*!<Bit 0 */
-#define USB_OTG_PKTSTS_1                ((uint32_t)0x00040000)            /*!<Bit 1 */
-#define USB_OTG_PKTSTS_2                ((uint32_t)0x00080000)            /*!<Bit 2 */
-#define USB_OTG_PKTSTS_3                ((uint32_t)0x00100000)            /*!<Bit 3 */
+#define USB_OTG_PKTSTS                  (0x001E0000UL)            /*!< Packet status */
+#define USB_OTG_PKTSTS_0                (0x00020000UL)            /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1                (0x00040000UL)            /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2                (0x00080000UL)            /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3                (0x00100000UL)            /*!<Bit 3 */
 
-#define USB_OTG_EPNUM                   ((uint32_t)0x0000000F)            /*!< Endpoint number */
-#define USB_OTG_EPNUM_0                 ((uint32_t)0x00000001)            /*!<Bit 0 */
-#define USB_OTG_EPNUM_1                 ((uint32_t)0x00000002)            /*!<Bit 1 */
-#define USB_OTG_EPNUM_2                 ((uint32_t)0x00000004)            /*!<Bit 2 */
-#define USB_OTG_EPNUM_3                 ((uint32_t)0x00000008)            /*!<Bit 3 */
+#define USB_OTG_EPNUM                   (0x0000000FUL)            /*!< Endpoint number */
+#define USB_OTG_EPNUM_0                 (0x00000001UL)            /*!<Bit 0 */
+#define USB_OTG_EPNUM_1                 (0x00000002UL)            /*!<Bit 1 */
+#define USB_OTG_EPNUM_2                 (0x00000004UL)            /*!<Bit 2 */
+#define USB_OTG_EPNUM_3                 (0x00000008UL)            /*!<Bit 3 */
 
-#define USB_OTG_FRMNUM                  ((uint32_t)0x01E00000)            /*!< Frame number */
-#define USB_OTG_FRMNUM_0                ((uint32_t)0x00200000)            /*!<Bit 0 */
-#define USB_OTG_FRMNUM_1                ((uint32_t)0x00400000)            /*!<Bit 1 */
-#define USB_OTG_FRMNUM_2                ((uint32_t)0x00800000)            /*!<Bit 2 */
-#define USB_OTG_FRMNUM_3                ((uint32_t)0x01000000)            /*!<Bit 3 */
+#define USB_OTG_FRMNUM                  (0x01E00000UL)            /*!< Frame number */
+#define USB_OTG_FRMNUM_0                (0x00200000UL)            /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1                (0x00400000UL)            /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2                (0x00800000UL)            /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3                (0x01000000UL)            /*!<Bit 3 */
 
 /********************  Bit definition forUSB_OTG_GRXFSIZ register  ********************/
-#define USB_OTG_GRXFSIZ_RXFD                    ((uint32_t)0x0000FFFF)            /*!< RxFIFO depth */
+#define USB_OTG_GRXFSIZ_RXFD                    (0x0000FFFFUL)            /*!< RxFIFO depth */
 
 /********************  Bit definition forUSB_OTG_DVBUSDIS register  ********************/
-#define USB_OTG_DVBUSDIS_VBUSDT                  ((uint32_t)0x0000FFFF)            /*!< Device VBUS discharge time */
+#define USB_OTG_DVBUSDIS_VBUSDT                  (0x0000FFFFUL)            /*!< Device VBUS discharge time */
 
 /********************  Bit definition for OTG register  ********************/
-#define USB_OTG_NPTXFSA                 ((uint32_t)0x0000FFFF)            /*!< Nonperiodic transmit RAM start address */
-#define USB_OTG_NPTXFD                  ((uint32_t)0xFFFF0000)            /*!< Nonperiodic TxFIFO depth */
-#define USB_OTG_TX0FSA                  ((uint32_t)0x0000FFFF)            /*!< Endpoint 0 transmit RAM start address */
-#define USB_OTG_TX0FD                   ((uint32_t)0xFFFF0000)            /*!< Endpoint 0 TxFIFO depth */
+#define USB_OTG_NPTXFSA                 (0x0000FFFFUL)            /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD                  (0xFFFF0000UL)            /*!< Nonperiodic TxFIFO depth */
+#define USB_OTG_TX0FSA                  (0x0000FFFFUL)            /*!< Endpoint 0 transmit RAM start address */
+#define USB_OTG_TX0FD                   (0xFFFF0000UL)            /*!< Endpoint 0 TxFIFO depth */
 
 /********************  Bit definition forUSB_OTG_DVBUSPULSE register  ********************/
-#define USB_OTG_DVBUSPULSE_DVBUSP                  ((uint32_t)0x00000FFF)            /*!< Device VBUS pulsing time */
+#define USB_OTG_DVBUSPULSE_DVBUSP                  (0x00000FFFUL)            /*!< Device VBUS pulsing time */
 
 /********************  Bit definition forUSB_OTG_GNPTXSTS register  ********************/
-#define USB_OTG_GNPTXSTS_NPTXFSAV                ((uint32_t)0x0000FFFF)            /*!< Nonperiodic TxFIFO space available */
+#define USB_OTG_GNPTXSTS_NPTXFSAV                (0x0000FFFFUL)            /*!< Nonperiodic TxFIFO space available */
 
-#define USB_OTG_GNPTXSTS_NPTQXSAV                ((uint32_t)0x00FF0000)            /*!< Nonperiodic transmit request queue space available */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_0              ((uint32_t)0x00010000)            /*!<Bit 0 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_1              ((uint32_t)0x00020000)            /*!<Bit 1 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_2              ((uint32_t)0x00040000)            /*!<Bit 2 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_3              ((uint32_t)0x00080000)            /*!<Bit 3 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_4              ((uint32_t)0x00100000)            /*!<Bit 4 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_5              ((uint32_t)0x00200000)            /*!<Bit 5 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_6              ((uint32_t)0x00400000)            /*!<Bit 6 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_7              ((uint32_t)0x00800000)            /*!<Bit 7 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV                (0x00FF0000UL)            /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0              (0x00010000UL)            /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1              (0x00020000UL)            /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2              (0x00040000UL)            /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3              (0x00080000UL)            /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4              (0x00100000UL)            /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5              (0x00200000UL)            /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6              (0x00400000UL)            /*!<Bit 6 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7              (0x00800000UL)            /*!<Bit 7 */
 
-#define USB_OTG_GNPTXSTS_NPTXQTOP                ((uint32_t)0x7F000000)            /*!< Top of the nonperiodic transmit request queue */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_0              ((uint32_t)0x01000000)            /*!<Bit 0 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_1              ((uint32_t)0x02000000)            /*!<Bit 1 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_2              ((uint32_t)0x04000000)            /*!<Bit 2 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_3              ((uint32_t)0x08000000)            /*!<Bit 3 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_4              ((uint32_t)0x10000000)            /*!<Bit 4 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_5              ((uint32_t)0x20000000)            /*!<Bit 5 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_6              ((uint32_t)0x40000000)            /*!<Bit 6 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP                (0x7F000000UL)            /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0              (0x01000000UL)            /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1              (0x02000000UL)            /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2              (0x04000000UL)            /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3              (0x08000000UL)            /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4              (0x10000000UL)            /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5              (0x20000000UL)            /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6              (0x40000000UL)            /*!<Bit 6 */
 
 /********************  Bit definition forUSB_OTG_DTHRCTL register  ********************/
-#define USB_OTG_DTHRCTL_NONISOTHREN             ((uint32_t)0x00000001)            /*!< Nonisochronous IN endpoints threshold enable */
-#define USB_OTG_DTHRCTL_ISOTHREN                ((uint32_t)0x00000002)            /*!< ISO IN endpoint threshold enable */
+#define USB_OTG_DTHRCTL_NONISOTHREN             (0x00000001UL)            /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN                (0x00000002UL)            /*!< ISO IN endpoint threshold enable */
 
-#define USB_OTG_DTHRCTL_TXTHRLEN                ((uint32_t)0x000007FC)            /*!< Transmit threshold length */
-#define USB_OTG_DTHRCTL_TXTHRLEN_0              ((uint32_t)0x00000004)            /*!<Bit 0 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_1              ((uint32_t)0x00000008)            /*!<Bit 1 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_2              ((uint32_t)0x00000010)            /*!<Bit 2 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_3              ((uint32_t)0x00000020)            /*!<Bit 3 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_4              ((uint32_t)0x00000040)            /*!<Bit 4 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_5              ((uint32_t)0x00000080)            /*!<Bit 5 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_6              ((uint32_t)0x00000100)            /*!<Bit 6 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_7              ((uint32_t)0x00000200)            /*!<Bit 7 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_8              ((uint32_t)0x00000400)            /*!<Bit 8 */
-#define USB_OTG_DTHRCTL_RXTHREN                 ((uint32_t)0x00010000)            /*!< Receive threshold enable */
+#define USB_OTG_DTHRCTL_TXTHRLEN                (0x000007FCUL)            /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0              (0x00000004UL)            /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1              (0x00000008UL)            /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2              (0x00000010UL)            /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3              (0x00000020UL)            /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4              (0x00000040UL)            /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5              (0x00000080UL)            /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6              (0x00000100UL)            /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7              (0x00000200UL)            /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8              (0x00000400UL)            /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_RXTHREN                 (0x00010000UL)            /*!< Receive threshold enable */
 
-#define USB_OTG_DTHRCTL_RXTHRLEN                ((uint32_t)0x03FE0000)            /*!< Receive threshold length */
-#define USB_OTG_DTHRCTL_RXTHRLEN_0              ((uint32_t)0x00020000)            /*!<Bit 0 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_1              ((uint32_t)0x00040000)            /*!<Bit 1 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_2              ((uint32_t)0x00080000)            /*!<Bit 2 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_3              ((uint32_t)0x00100000)            /*!<Bit 3 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_4              ((uint32_t)0x00200000)            /*!<Bit 4 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_5              ((uint32_t)0x00400000)            /*!<Bit 5 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_6              ((uint32_t)0x00800000)            /*!<Bit 6 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_7              ((uint32_t)0x01000000)            /*!<Bit 7 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_8              ((uint32_t)0x02000000)            /*!<Bit 8 */
-#define USB_OTG_DTHRCTL_ARPEN                   ((uint32_t)0x08000000)            /*!< Arbiter parking enable */
+#define USB_OTG_DTHRCTL_RXTHRLEN                (0x03FE0000UL)            /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0              (0x00020000UL)            /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1              (0x00040000UL)            /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2              (0x00080000UL)            /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3              (0x00100000UL)            /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4              (0x00200000UL)            /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5              (0x00400000UL)            /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6              (0x00800000UL)            /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7              (0x01000000UL)            /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8              (0x02000000UL)            /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_ARPEN                   (0x08000000UL)            /*!< Arbiter parking enable */
 
 /********************  Bit definition forUSB_OTG_DIEPEMPMSK register  ********************/
-#define USB_OTG_DIEPEMPMSK_INEPTXFEM               ((uint32_t)0x0000FFFF)            /*!< IN EP Tx FIFO empty interrupt mask bits */
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM               (0x0000FFFFUL)            /*!< IN EP Tx FIFO empty interrupt mask bits */
 
 /********************  Bit definition forUSB_OTG_DEACHINT register  ********************/
-#define USB_OTG_DEACHINT_IEP1INT                 ((uint32_t)0x00000002)            /*!< IN endpoint 1interrupt bit */
-#define USB_OTG_DEACHINT_OEP1INT                 ((uint32_t)0x00020000)            /*!< OUT endpoint 1 interrupt bit */
+#define USB_OTG_DEACHINT_IEP1INT                 (0x00000002UL)            /*!< IN endpoint 1interrupt bit */
+#define USB_OTG_DEACHINT_OEP1INT                 (0x00020000UL)            /*!< OUT endpoint 1 interrupt bit */
 
 /********************  Bit definition forUSB_OTG_GCCFG register  ********************/
-#define USB_OTG_GCCFG_PWRDWN                  ((uint32_t)0x00010000)            /*!< Power down */
-#define USB_OTG_GCCFG_I2CPADEN                ((uint32_t)0x00020000)            /*!< Enable I2C bus connection for the external I2C PHY interface */
-#define USB_OTG_GCCFG_VBUSASEN                ((uint32_t)0x00040000)            /*!< Enable the VBUS sensing device */
-#define USB_OTG_GCCFG_VBUSBSEN                ((uint32_t)0x00080000)            /*!< Enable the VBUS sensing device */
-#define USB_OTG_GCCFG_SOFOUTEN                ((uint32_t)0x00100000)            /*!< SOF output enable */
-#define USB_OTG_GCCFG_NOVBUSSENS              ((uint32_t)0x00200000)            /*!< VBUS sensing disable option */
+#define USB_OTG_GCCFG_PWRDWN                  (0x00010000UL)            /*!< Power down */
+#define USB_OTG_GCCFG_I2CPADEN                (0x00020000UL)            /*!< Enable I2C bus connection for the external I2C PHY interface */
+#define USB_OTG_GCCFG_VBUSASEN                (0x00040000UL)            /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_VBUSBSEN                (0x00080000UL)            /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_SOFOUTEN                (0x00100000UL)            /*!< SOF output enable */
+#define USB_OTG_GCCFG_NOVBUSSENS              (0x00200000UL)            /*!< VBUS sensing disable option */
 
 /********************  Bit definition forUSB_OTG_DEACHINTMSK register  ********************/
-#define USB_OTG_DEACHINTMSK_IEP1INTM                ((uint32_t)0x00000002)            /*!< IN Endpoint 1 interrupt mask bit */
-#define USB_OTG_DEACHINTMSK_OEP1INTM                ((uint32_t)0x00020000)            /*!< OUT Endpoint 1 interrupt mask bit */
+#define USB_OTG_DEACHINTMSK_IEP1INTM                (0x00000002UL)            /*!< IN Endpoint 1 interrupt mask bit */
+#define USB_OTG_DEACHINTMSK_OEP1INTM                (0x00020000UL)            /*!< OUT Endpoint 1 interrupt mask bit */
 
 /********************  Bit definition forUSB_OTG_CID register  ********************/
-#define USB_OTG_CID_PRODUCT_ID              ((uint32_t)0xFFFFFFFF)            /*!< Product ID field */
+#define USB_OTG_CID_PRODUCT_ID              (0xFFFFFFFFUL)            /*!< Product ID field */
 
 /********************  Bit definition forUSB_OTG_DIEPEACHMSK1 register  ********************/
-#define USB_OTG_DIEPEACHMSK1_XFRCM                   ((uint32_t)0x00000001)            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_EPDM                    ((uint32_t)0x00000002)            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_TOM                     ((uint32_t)0x00000008)            /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK               ((uint32_t)0x00000010)            /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DIEPEACHMSK1_INEPNMM                 ((uint32_t)0x00000020)            /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DIEPEACHMSK1_INEPNEM                 ((uint32_t)0x00000040)            /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DIEPEACHMSK1_TXFURM                  ((uint32_t)0x00000100)            /*!< FIFO underrun mask */
-#define USB_OTG_DIEPEACHMSK1_BIM                     ((uint32_t)0x00000200)            /*!< BNA interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_NAKM                    ((uint32_t)0x00002000)            /*!< NAK interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_XFRCM                   (0x00000001UL)            /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_EPDM                    (0x00000002UL)            /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_TOM                     (0x00000008UL)            /*!< Timeout condition mask (nonisochronous endpointsUL) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK               (0x00000010UL)            /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM                 (0x00000020UL)            /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM                 (0x00000040UL)            /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPEACHMSK1_TXFURM                  (0x00000100UL)            /*!< FIFO underrun mask */
+#define USB_OTG_DIEPEACHMSK1_BIM                     (0x00000200UL)            /*!< BNA interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_NAKM                    (0x00002000UL)            /*!< NAK interrupt mask */
 
 /********************  Bit definition forUSB_OTG_HPRT register  ********************/
-#define USB_OTG_HPRT_PCSTS                   ((uint32_t)0x00000001)            /*!< Port connect status */
-#define USB_OTG_HPRT_PCDET                   ((uint32_t)0x00000002)            /*!< Port connect detected */
-#define USB_OTG_HPRT_PENA                    ((uint32_t)0x00000004)            /*!< Port enable */
-#define USB_OTG_HPRT_PENCHNG                 ((uint32_t)0x00000008)            /*!< Port enable/disable change */
-#define USB_OTG_HPRT_POCA                    ((uint32_t)0x00000010)            /*!< Port overcurrent active */
-#define USB_OTG_HPRT_POCCHNG                 ((uint32_t)0x00000020)            /*!< Port overcurrent change */
-#define USB_OTG_HPRT_PRES                    ((uint32_t)0x00000040)            /*!< Port resume */
-#define USB_OTG_HPRT_PSUSP                   ((uint32_t)0x00000080)            /*!< Port suspend */
-#define USB_OTG_HPRT_PRST                    ((uint32_t)0x00000100)            /*!< Port reset */
+#define USB_OTG_HPRT_PCSTS                   (0x00000001UL)            /*!< Port connect status */
+#define USB_OTG_HPRT_PCDET                   (0x00000002UL)            /*!< Port connect detected */
+#define USB_OTG_HPRT_PENA                    (0x00000004UL)            /*!< Port enable */
+#define USB_OTG_HPRT_PENCHNG                 (0x00000008UL)            /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA                    (0x00000010UL)            /*!< Port overcurrent active */
+#define USB_OTG_HPRT_POCCHNG                 (0x00000020UL)            /*!< Port overcurrent change */
+#define USB_OTG_HPRT_PRES                    (0x00000040UL)            /*!< Port resume */
+#define USB_OTG_HPRT_PSUSP                   (0x00000080UL)            /*!< Port suspend */
+#define USB_OTG_HPRT_PRST                    (0x00000100UL)            /*!< Port reset */
 
-#define USB_OTG_HPRT_PLSTS                   ((uint32_t)0x00000C00)            /*!< Port line status */
-#define USB_OTG_HPRT_PLSTS_0                 ((uint32_t)0x00000400)            /*!<Bit 0 */
-#define USB_OTG_HPRT_PLSTS_1                 ((uint32_t)0x00000800)            /*!<Bit 1 */
-#define USB_OTG_HPRT_PPWR                    ((uint32_t)0x00001000)            /*!< Port power */
+#define USB_OTG_HPRT_PLSTS                   (0x00000C00UL)            /*!< Port line status */
+#define USB_OTG_HPRT_PLSTS_0                 (0x00000400UL)            /*!<Bit 0 */
+#define USB_OTG_HPRT_PLSTS_1                 (0x00000800UL)            /*!<Bit 1 */
+#define USB_OTG_HPRT_PPWR                    (0x00001000UL)            /*!< Port power */
 
-#define USB_OTG_HPRT_PTCTL                   ((uint32_t)0x0001E000)            /*!< Port test control */
-#define USB_OTG_HPRT_PTCTL_0                 ((uint32_t)0x00002000)            /*!<Bit 0 */
-#define USB_OTG_HPRT_PTCTL_1                 ((uint32_t)0x00004000)            /*!<Bit 1 */
-#define USB_OTG_HPRT_PTCTL_2                 ((uint32_t)0x00008000)            /*!<Bit 2 */
-#define USB_OTG_HPRT_PTCTL_3                 ((uint32_t)0x00010000)            /*!<Bit 3 */
+#define USB_OTG_HPRT_PTCTL                   (0x0001E000UL)            /*!< Port test control */
+#define USB_OTG_HPRT_PTCTL_0                 (0x00002000UL)            /*!<Bit 0 */
+#define USB_OTG_HPRT_PTCTL_1                 (0x00004000UL)            /*!<Bit 1 */
+#define USB_OTG_HPRT_PTCTL_2                 (0x00008000UL)            /*!<Bit 2 */
+#define USB_OTG_HPRT_PTCTL_3                 (0x00010000UL)            /*!<Bit 3 */
 
-#define USB_OTG_HPRT_PSPD                    ((uint32_t)0x00060000)            /*!< Port speed */
-#define USB_OTG_HPRT_PSPD_0                  ((uint32_t)0x00020000)            /*!<Bit 0 */
-#define USB_OTG_HPRT_PSPD_1                  ((uint32_t)0x00040000)            /*!<Bit 1 */
+#define USB_OTG_HPRT_PSPD                    (0x00060000UL)            /*!< Port speed */
+#define USB_OTG_HPRT_PSPD_0                  (0x00020000UL)            /*!<Bit 0 */
+#define USB_OTG_HPRT_PSPD_1                  (0x00040000UL)            /*!<Bit 1 */
 
 /********************  Bit definition forUSB_OTG_DOEPEACHMSK1 register  ********************/
-#define USB_OTG_DOEPEACHMSK1_XFRCM                   ((uint32_t)0x00000001)            /*!< Transfer completed interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_EPDM                    ((uint32_t)0x00000002)            /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_TOM                     ((uint32_t)0x00000008)            /*!< Timeout condition mask */
-#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK               ((uint32_t)0x00000010)            /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DOEPEACHMSK1_INEPNMM                 ((uint32_t)0x00000020)            /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DOEPEACHMSK1_INEPNEM                 ((uint32_t)0x00000040)            /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DOEPEACHMSK1_TXFURM                  ((uint32_t)0x00000100)            /*!< OUT packet error mask */
-#define USB_OTG_DOEPEACHMSK1_BIM                     ((uint32_t)0x00000200)            /*!< BNA interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_BERRM                   ((uint32_t)0x00001000)            /*!< Bubble error interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_NAKM                    ((uint32_t)0x00002000)            /*!< NAK interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_NYETM                   ((uint32_t)0x00004000)            /*!< NYET interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_XFRCM                   (0x00000001UL)            /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_EPDM                    (0x00000002UL)            /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_TOM                     (0x00000008UL)            /*!< Timeout condition mask */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK               (0x00000010UL)            /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM                 (0x00000020UL)            /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM                 (0x00000040UL)            /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DOEPEACHMSK1_TXFURM                  (0x00000100UL)            /*!< OUT packet error mask */
+#define USB_OTG_DOEPEACHMSK1_BIM                     (0x00000200UL)            /*!< BNA interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_BERRM                   (0x00001000UL)            /*!< Bubble error interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NAKM                    (0x00002000UL)            /*!< NAK interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NYETM                   (0x00004000UL)            /*!< NYET interrupt mask */
 
 /********************  Bit definition forUSB_OTG_HPTXFSIZ register  ********************/
-#define USB_OTG_HPTXFSIZ_PTXSA                   ((uint32_t)0x0000FFFF)            /*!< Host periodic TxFIFO start address */
-#define USB_OTG_HPTXFSIZ_PTXFD                   ((uint32_t)0xFFFF0000)            /*!< Host periodic TxFIFO depth */
+#define USB_OTG_HPTXFSIZ_PTXSA                   (0x0000FFFFUL)            /*!< Host periodic TxFIFO start address */
+#define USB_OTG_HPTXFSIZ_PTXFD                   (0xFFFF0000UL)            /*!< Host periodic TxFIFO depth */
 
 /********************  Bit definition forUSB_OTG_DIEPCTL register  ********************/
-#define USB_OTG_DIEPCTL_MPSIZ                   ((uint32_t)0x000007FF)            /*!< Maximum packet size */
-#define USB_OTG_DIEPCTL_USBAEP                  ((uint32_t)0x00008000)            /*!< USB active endpoint */
-#define USB_OTG_DIEPCTL_EONUM_DPID              ((uint32_t)0x00010000)            /*!< Even/odd frame */
-#define USB_OTG_DIEPCTL_NAKSTS                  ((uint32_t)0x00020000)            /*!< NAK status */
+#define USB_OTG_DIEPCTL_MPSIZ                   (0x000007FFUL)            /*!< Maximum packet size */
+#define USB_OTG_DIEPCTL_USBAEP                  (0x00008000UL)            /*!< USB active endpoint */
+#define USB_OTG_DIEPCTL_EONUM_DPID              (0x00010000UL)            /*!< Even/odd frame */
+#define USB_OTG_DIEPCTL_NAKSTS                  (0x00020000UL)            /*!< NAK status */
 
-#define USB_OTG_DIEPCTL_EPTYP                   ((uint32_t)0x000C0000)            /*!< Endpoint type */
-#define USB_OTG_DIEPCTL_EPTYP_0                 ((uint32_t)0x00040000)            /*!<Bit 0 */
-#define USB_OTG_DIEPCTL_EPTYP_1                 ((uint32_t)0x00080000)            /*!<Bit 1 */
-#define USB_OTG_DIEPCTL_STALL                   ((uint32_t)0x00200000)            /*!< STALL handshake */
+#define USB_OTG_DIEPCTL_EPTYP                   (0x000C0000UL)            /*!< Endpoint type */
+#define USB_OTG_DIEPCTL_EPTYP_0                 (0x00040000UL)            /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_EPTYP_1                 (0x00080000UL)            /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_STALL                   (0x00200000UL)            /*!< STALL handshake */
 
-#define USB_OTG_DIEPCTL_TXFNUM                  ((uint32_t)0x03C00000)            /*!< TxFIFO number */
-#define USB_OTG_DIEPCTL_TXFNUM_0                ((uint32_t)0x00400000)            /*!<Bit 0 */
-#define USB_OTG_DIEPCTL_TXFNUM_1                ((uint32_t)0x00800000)            /*!<Bit 1 */
-#define USB_OTG_DIEPCTL_TXFNUM_2                ((uint32_t)0x01000000)            /*!<Bit 2 */
-#define USB_OTG_DIEPCTL_TXFNUM_3                ((uint32_t)0x02000000)            /*!<Bit 3 */
-#define USB_OTG_DIEPCTL_CNAK                    ((uint32_t)0x04000000)            /*!< Clear NAK */
-#define USB_OTG_DIEPCTL_SNAK                    ((uint32_t)0x08000000)            /*!< Set NAK */
-#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM          ((uint32_t)0x10000000)            /*!< Set DATA0 PID */
-#define USB_OTG_DIEPCTL_SODDFRM                 ((uint32_t)0x20000000)            /*!< Set odd frame */
-#define USB_OTG_DIEPCTL_EPDIS                   ((uint32_t)0x40000000)            /*!< Endpoint disable */
-#define USB_OTG_DIEPCTL_EPENA                   ((uint32_t)0x80000000)            /*!< Endpoint enable */
+#define USB_OTG_DIEPCTL_TXFNUM                  (0x03C00000UL)            /*!< TxFIFO number */
+#define USB_OTG_DIEPCTL_TXFNUM_0                (0x00400000UL)            /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_TXFNUM_1                (0x00800000UL)            /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_TXFNUM_2                (0x01000000UL)            /*!<Bit 2 */
+#define USB_OTG_DIEPCTL_TXFNUM_3                (0x02000000UL)            /*!<Bit 3 */
+#define USB_OTG_DIEPCTL_CNAK                    (0x04000000UL)            /*!< Clear NAK */
+#define USB_OTG_DIEPCTL_SNAK                    (0x08000000UL)            /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM          (0x10000000UL)            /*!< Set DATA0 PID */
+#define USB_OTG_DIEPCTL_SODDFRM                 (0x20000000UL)            /*!< Set odd frame */
+#define USB_OTG_DIEPCTL_EPDIS                   (0x40000000UL)            /*!< Endpoint disable */
+#define USB_OTG_DIEPCTL_EPENA                   (0x80000000UL)            /*!< Endpoint enable */
 
 /********************  Bit definition forUSB_OTG_HCCHAR register  ********************/
-#define USB_OTG_HCCHAR_MPSIZ                   ((uint32_t)0x000007FF)            /*!< Maximum packet size */
+#define USB_OTG_HCCHAR_MPSIZ                   (0x000007FFUL)            /*!< Maximum packet size */
 
-#define USB_OTG_HCCHAR_EPNUM                   ((uint32_t)0x00007800)            /*!< Endpoint number */
-#define USB_OTG_HCCHAR_EPNUM_0                 ((uint32_t)0x00000800)            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_EPNUM_1                 ((uint32_t)0x00001000)            /*!<Bit 1 */
-#define USB_OTG_HCCHAR_EPNUM_2                 ((uint32_t)0x00002000)            /*!<Bit 2 */
-#define USB_OTG_HCCHAR_EPNUM_3                 ((uint32_t)0x00004000)            /*!<Bit 3 */
-#define USB_OTG_HCCHAR_EPDIR                   ((uint32_t)0x00008000)            /*!< Endpoint direction */
-#define USB_OTG_HCCHAR_LSDEV                   ((uint32_t)0x00020000)            /*!< Low-speed device */
+#define USB_OTG_HCCHAR_EPNUM                   (0x00007800UL)            /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0                 (0x00000800UL)            /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPNUM_1                 (0x00001000UL)            /*!<Bit 1 */
+#define USB_OTG_HCCHAR_EPNUM_2                 (0x00002000UL)            /*!<Bit 2 */
+#define USB_OTG_HCCHAR_EPNUM_3                 (0x00004000UL)            /*!<Bit 3 */
+#define USB_OTG_HCCHAR_EPDIR                   (0x00008000UL)            /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV                   (0x00020000UL)            /*!< Low-speed device */
 
-#define USB_OTG_HCCHAR_EPTYP                   ((uint32_t)0x000C0000)            /*!< Endpoint type */
-#define USB_OTG_HCCHAR_EPTYP_0                 ((uint32_t)0x00040000)            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_EPTYP_1                 ((uint32_t)0x00080000)            /*!<Bit 1 */
+#define USB_OTG_HCCHAR_EPTYP                   (0x000C0000UL)            /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0                 (0x00040000UL)            /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPTYP_1                 (0x00080000UL)            /*!<Bit 1 */
 
-#define USB_OTG_HCCHAR_MC                      ((uint32_t)0x00300000)            /*!< Multi Count (MC) / Error Count (EC) */
-#define USB_OTG_HCCHAR_MC_0                    ((uint32_t)0x00100000)            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_MC_1                    ((uint32_t)0x00200000)            /*!<Bit 1 */
+#define USB_OTG_HCCHAR_MC                      (0x00300000UL)            /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0                    (0x00100000UL)            /*!<Bit 0 */
+#define USB_OTG_HCCHAR_MC_1                    (0x00200000UL)            /*!<Bit 1 */
 
-#define USB_OTG_HCCHAR_DAD                     ((uint32_t)0x1FC00000)            /*!< Device address */
-#define USB_OTG_HCCHAR_DAD_0                   ((uint32_t)0x00400000)            /*!<Bit 0 */
-#define USB_OTG_HCCHAR_DAD_1                   ((uint32_t)0x00800000)            /*!<Bit 1 */
-#define USB_OTG_HCCHAR_DAD_2                   ((uint32_t)0x01000000)            /*!<Bit 2 */
-#define USB_OTG_HCCHAR_DAD_3                   ((uint32_t)0x02000000)            /*!<Bit 3 */
-#define USB_OTG_HCCHAR_DAD_4                   ((uint32_t)0x04000000)            /*!<Bit 4 */
-#define USB_OTG_HCCHAR_DAD_5                   ((uint32_t)0x08000000)            /*!<Bit 5 */
-#define USB_OTG_HCCHAR_DAD_6                   ((uint32_t)0x10000000)            /*!<Bit 6 */
-#define USB_OTG_HCCHAR_ODDFRM                  ((uint32_t)0x20000000)            /*!< Odd frame */
-#define USB_OTG_HCCHAR_CHDIS                   ((uint32_t)0x40000000)            /*!< Channel disable */
-#define USB_OTG_HCCHAR_CHENA                   ((uint32_t)0x80000000)            /*!< Channel enable */
+#define USB_OTG_HCCHAR_DAD                     (0x1FC00000UL)            /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0                   (0x00400000UL)            /*!<Bit 0 */
+#define USB_OTG_HCCHAR_DAD_1                   (0x00800000UL)            /*!<Bit 1 */
+#define USB_OTG_HCCHAR_DAD_2                   (0x01000000UL)            /*!<Bit 2 */
+#define USB_OTG_HCCHAR_DAD_3                   (0x02000000UL)            /*!<Bit 3 */
+#define USB_OTG_HCCHAR_DAD_4                   (0x04000000UL)            /*!<Bit 4 */
+#define USB_OTG_HCCHAR_DAD_5                   (0x08000000UL)            /*!<Bit 5 */
+#define USB_OTG_HCCHAR_DAD_6                   (0x10000000UL)            /*!<Bit 6 */
+#define USB_OTG_HCCHAR_ODDFRM                  (0x20000000UL)            /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS                   (0x40000000UL)            /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA                   (0x80000000UL)            /*!< Channel enable */
 
 /********************  Bit definition forUSB_OTG_HCSPLT register  ********************/
 
-#define USB_OTG_HCSPLT_PRTADDR                 ((uint32_t)0x0000007F)            /*!< Port address */
-#define USB_OTG_HCSPLT_PRTADDR_0               ((uint32_t)0x00000001)            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_PRTADDR_1               ((uint32_t)0x00000002)            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_PRTADDR_2               ((uint32_t)0x00000004)            /*!<Bit 2 */
-#define USB_OTG_HCSPLT_PRTADDR_3               ((uint32_t)0x00000008)            /*!<Bit 3 */
-#define USB_OTG_HCSPLT_PRTADDR_4               ((uint32_t)0x00000010)            /*!<Bit 4 */
-#define USB_OTG_HCSPLT_PRTADDR_5               ((uint32_t)0x00000020)            /*!<Bit 5 */
-#define USB_OTG_HCSPLT_PRTADDR_6               ((uint32_t)0x00000040)            /*!<Bit 6 */
+#define USB_OTG_HCSPLT_PRTADDR                 (0x0000007FUL)            /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0               (0x00000001UL)            /*!<Bit 0 */
+#define USB_OTG_HCSPLT_PRTADDR_1               (0x00000002UL)            /*!<Bit 1 */
+#define USB_OTG_HCSPLT_PRTADDR_2               (0x00000004UL)            /*!<Bit 2 */
+#define USB_OTG_HCSPLT_PRTADDR_3               (0x00000008UL)            /*!<Bit 3 */
+#define USB_OTG_HCSPLT_PRTADDR_4               (0x00000010UL)            /*!<Bit 4 */
+#define USB_OTG_HCSPLT_PRTADDR_5               (0x00000020UL)            /*!<Bit 5 */
+#define USB_OTG_HCSPLT_PRTADDR_6               (0x00000040UL)            /*!<Bit 6 */
 
-#define USB_OTG_HCSPLT_HUBADDR                 ((uint32_t)0x00003F80)            /*!< Hub address */
-#define USB_OTG_HCSPLT_HUBADDR_0               ((uint32_t)0x00000080)            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_HUBADDR_1               ((uint32_t)0x00000100)            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_HUBADDR_2               ((uint32_t)0x00000200)            /*!<Bit 2 */
-#define USB_OTG_HCSPLT_HUBADDR_3               ((uint32_t)0x00000400)            /*!<Bit 3 */
-#define USB_OTG_HCSPLT_HUBADDR_4               ((uint32_t)0x00000800)            /*!<Bit 4 */
-#define USB_OTG_HCSPLT_HUBADDR_5               ((uint32_t)0x00001000)            /*!<Bit 5 */
-#define USB_OTG_HCSPLT_HUBADDR_6               ((uint32_t)0x00002000)            /*!<Bit 6 */
+#define USB_OTG_HCSPLT_HUBADDR                 (0x00003F80UL)            /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0               (0x00000080UL)            /*!<Bit 0 */
+#define USB_OTG_HCSPLT_HUBADDR_1               (0x00000100UL)            /*!<Bit 1 */
+#define USB_OTG_HCSPLT_HUBADDR_2               (0x00000200UL)            /*!<Bit 2 */
+#define USB_OTG_HCSPLT_HUBADDR_3               (0x00000400UL)            /*!<Bit 3 */
+#define USB_OTG_HCSPLT_HUBADDR_4               (0x00000800UL)            /*!<Bit 4 */
+#define USB_OTG_HCSPLT_HUBADDR_5               (0x00001000UL)            /*!<Bit 5 */
+#define USB_OTG_HCSPLT_HUBADDR_6               (0x00002000UL)            /*!<Bit 6 */
 
-#define USB_OTG_HCSPLT_XACTPOS                 ((uint32_t)0x0000C000)            /*!< XACTPOS */
-#define USB_OTG_HCSPLT_XACTPOS_0               ((uint32_t)0x00004000)            /*!<Bit 0 */
-#define USB_OTG_HCSPLT_XACTPOS_1               ((uint32_t)0x00008000)            /*!<Bit 1 */
-#define USB_OTG_HCSPLT_COMPLSPLT               ((uint32_t)0x00010000)            /*!< Do complete split */
-#define USB_OTG_HCSPLT_SPLITEN                 ((uint32_t)0x80000000)            /*!< Split enable */
+#define USB_OTG_HCSPLT_XACTPOS                 (0x0000C000UL)            /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0               (0x00004000UL)            /*!<Bit 0 */
+#define USB_OTG_HCSPLT_XACTPOS_1               (0x00008000UL)            /*!<Bit 1 */
+#define USB_OTG_HCSPLT_COMPLSPLT               (0x00010000UL)            /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN                 (0x80000000UL)            /*!< Split enable */
 
 /********************  Bit definition forUSB_OTG_HCINT register  ********************/
-#define USB_OTG_HCINT_XFRC                    ((uint32_t)0x00000001)            /*!< Transfer completed */
-#define USB_OTG_HCINT_CHH                     ((uint32_t)0x00000002)            /*!< Channel halted */
-#define USB_OTG_HCINT_AHBERR                  ((uint32_t)0x00000004)            /*!< AHB error */
-#define USB_OTG_HCINT_STALL                   ((uint32_t)0x00000008)            /*!< STALL response received interrupt */
-#define USB_OTG_HCINT_NAK                     ((uint32_t)0x00000010)            /*!< NAK response received interrupt */
-#define USB_OTG_HCINT_ACK                     ((uint32_t)0x00000020)            /*!< ACK response received/transmitted interrupt */
-#define USB_OTG_HCINT_NYET                    ((uint32_t)0x00000040)            /*!< Response received interrupt */
-#define USB_OTG_HCINT_TXERR                   ((uint32_t)0x00000080)            /*!< Transaction error */
-#define USB_OTG_HCINT_BBERR                   ((uint32_t)0x00000100)            /*!< Babble error */
-#define USB_OTG_HCINT_FRMOR                   ((uint32_t)0x00000200)            /*!< Frame overrun */
-#define USB_OTG_HCINT_DTERR                   ((uint32_t)0x00000400)            /*!< Data toggle error */
+#define USB_OTG_HCINT_XFRC                    (0x00000001UL)            /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH                     (0x00000002UL)            /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR                  (0x00000004UL)            /*!< AHB error */
+#define USB_OTG_HCINT_STALL                   (0x00000008UL)            /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK                     (0x00000010UL)            /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK                     (0x00000020UL)            /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET                    (0x00000040UL)            /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR                   (0x00000080UL)            /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR                   (0x00000100UL)            /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR                   (0x00000200UL)            /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR                   (0x00000400UL)            /*!< Data toggle error */
 
 /********************  Bit definition forUSB_OTG_DIEPINT register  ********************/
-#define USB_OTG_DIEPINT_XFRC                    ((uint32_t)0x00000001)            /*!< Transfer completed interrupt */
-#define USB_OTG_DIEPINT_EPDISD                  ((uint32_t)0x00000002)            /*!< Endpoint disabled interrupt */
-#define USB_OTG_DIEPINT_TOC                     ((uint32_t)0x00000008)            /*!< Timeout condition */
-#define USB_OTG_DIEPINT_ITTXFE                  ((uint32_t)0x00000010)            /*!< IN token received when TxFIFO is empty */
-#define USB_OTG_DIEPINT_INEPNE                  ((uint32_t)0x00000040)            /*!< IN endpoint NAK effective */
-#define USB_OTG_DIEPINT_TXFE                    ((uint32_t)0x00000080)            /*!< Transmit FIFO empty */
-#define USB_OTG_DIEPINT_TXFIFOUDRN              ((uint32_t)0x00000100)            /*!< Transmit Fifo Underrun */
-#define USB_OTG_DIEPINT_BNA                     ((uint32_t)0x00000200)            /*!< Buffer not available interrupt */
-#define USB_OTG_DIEPINT_PKTDRPSTS               ((uint32_t)0x00000800)            /*!< Packet dropped status */
-#define USB_OTG_DIEPINT_BERR                    ((uint32_t)0x00001000)            /*!< Babble error interrupt */
-#define USB_OTG_DIEPINT_NAK                     ((uint32_t)0x00002000)            /*!< NAK interrupt */
+#define USB_OTG_DIEPINT_XFRC                    (0x00000001UL)            /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD                  (0x00000002UL)            /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_TOC                     (0x00000008UL)            /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE                  (0x00000010UL)            /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNE                  (0x00000040UL)            /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE                    (0x00000080UL)            /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN              (0x00000100UL)            /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA                     (0x00000200UL)            /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS               (0x00000800UL)            /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR                    (0x00001000UL)            /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK                     (0x00002000UL)            /*!< NAK interrupt */
 
 /********************  Bit definition forUSB_OTG_HCINTMSK register  ********************/
-#define USB_OTG_HCINTMSK_XFRCM                   ((uint32_t)0x00000001)            /*!< Transfer completed mask */
-#define USB_OTG_HCINTMSK_CHHM                    ((uint32_t)0x00000002)            /*!< Channel halted mask */
-#define USB_OTG_HCINTMSK_AHBERR                  ((uint32_t)0x00000004)            /*!< AHB error */
-#define USB_OTG_HCINTMSK_STALLM                  ((uint32_t)0x00000008)            /*!< STALL response received interrupt mask */
-#define USB_OTG_HCINTMSK_NAKM                    ((uint32_t)0x00000010)            /*!< NAK response received interrupt mask */
-#define USB_OTG_HCINTMSK_ACKM                    ((uint32_t)0x00000020)            /*!< ACK response received/transmitted interrupt mask */
-#define USB_OTG_HCINTMSK_NYET                    ((uint32_t)0x00000040)            /*!< response received interrupt mask */
-#define USB_OTG_HCINTMSK_TXERRM                  ((uint32_t)0x00000080)            /*!< Transaction error mask */
-#define USB_OTG_HCINTMSK_BBERRM                  ((uint32_t)0x00000100)            /*!< Babble error mask */
-#define USB_OTG_HCINTMSK_FRMORM                  ((uint32_t)0x00000200)            /*!< Frame overrun mask */
-#define USB_OTG_HCINTMSK_DTERRM                  ((uint32_t)0x00000400)            /*!< Data toggle error mask */
+#define USB_OTG_HCINTMSK_XFRCM                   (0x00000001UL)            /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM                    (0x00000002UL)            /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR                  (0x00000004UL)            /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM                  (0x00000008UL)            /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM                    (0x00000010UL)            /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM                    (0x00000020UL)            /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET                    (0x00000040UL)            /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM                  (0x00000080UL)            /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM                  (0x00000100UL)            /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM                  (0x00000200UL)            /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM                  (0x00000400UL)            /*!< Data toggle error mask */
 
 /********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/
 
-#define USB_OTG_DIEPTSIZ_XFRSIZ                  ((uint32_t)0x0007FFFF)            /*!< Transfer size */
-#define USB_OTG_DIEPTSIZ_PKTCNT                  ((uint32_t)0x1FF80000)            /*!< Packet count */
-#define USB_OTG_DIEPTSIZ_MULCNT                  ((uint32_t)0x60000000)            /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_XFRSIZ                  (0x0007FFFFUL)            /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT                  (0x1FF80000UL)            /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT                  (0x60000000UL)            /*!< Packet count */
 /********************  Bit definition forUSB_OTG_HCTSIZ register  ********************/
-#define USB_OTG_HCTSIZ_XFRSIZ                    ((uint32_t)0x0007FFFF)            /*!< Transfer size */
-#define USB_OTG_HCTSIZ_PKTCNT                    ((uint32_t)0x1FF80000)            /*!< Packet count */
-#define USB_OTG_HCTSIZ_DOPING                    ((uint32_t)0x80000000)            /*!< Do PING */
-#define USB_OTG_HCTSIZ_DPID                      ((uint32_t)0x60000000)            /*!< Data PID */
-#define USB_OTG_HCTSIZ_DPID_0                    ((uint32_t)0x20000000)            /*!<Bit 0 */
-#define USB_OTG_HCTSIZ_DPID_1                    ((uint32_t)0x40000000)            /*!<Bit 1 */
+#define USB_OTG_HCTSIZ_XFRSIZ                    (0x0007FFFFUL)            /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT                    (0x1FF80000UL)            /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING                    (0x80000000UL)            /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID                      (0x60000000UL)            /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0                    (0x20000000UL)            /*!<Bit 0 */
+#define USB_OTG_HCTSIZ_DPID_1                    (0x40000000UL)            /*!<Bit 1 */
 
 /********************  Bit definition forUSB_OTG_DIEPDMA register  ********************/
-#define USB_OTG_DIEPDMA_DMAADDR                  ((uint32_t)0xFFFFFFFF)            /*!< DMA address */
+#define USB_OTG_DIEPDMA_DMAADDR                  (0xFFFFFFFFUL)            /*!< DMA address */
 
 /********************  Bit definition forUSB_OTG_HCDMA register  ********************/
-#define USB_OTG_HCDMA_DMAADDR                    ((uint32_t)0xFFFFFFFF)            /*!< DMA address */
+#define USB_OTG_HCDMA_DMAADDR                    (0xFFFFFFFFUL)            /*!< DMA address */
 
 /********************  Bit definition forUSB_OTG_DTXFSTS register  ********************/
-#define USB_OTG_DTXFSTS_INEPTFSAV                ((uint32_t)0x0000FFFF)            /*!< IN endpoint TxFIFO space avail */
+#define USB_OTG_DTXFSTS_INEPTFSAV                (0x0000FFFFUL)            /*!< IN endpoint TxFIFO space avail */
 
 /********************  Bit definition forUSB_OTG_DIEPTXF register  ********************/
-#define USB_OTG_DIEPTXF_INEPTXSA                 ((uint32_t)0x0000FFFF)            /*!< IN endpoint FIFOx transmit RAM start address */
-#define USB_OTG_DIEPTXF_INEPTXFD                 ((uint32_t)0xFFFF0000)            /*!< IN endpoint TxFIFO depth */
+#define USB_OTG_DIEPTXF_INEPTXSA                 (0x0000FFFFUL)            /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD                 (0xFFFF0000UL)            /*!< IN endpoint TxFIFO depth */
 
 /********************  Bit definition forUSB_OTG_DOEPCTL register  ********************/
 
-#define USB_OTG_DOEPCTL_MPSIZ                     ((uint32_t)0x000007FF)            /*!< Maximum packet size */          /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_USBAEP                    ((uint32_t)0x00008000)            /*!< USB active endpoint */
-#define USB_OTG_DOEPCTL_NAKSTS                    ((uint32_t)0x00020000)            /*!< NAK status */
-#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM            ((uint32_t)0x10000000)            /*!< Set DATA0 PID */
-#define USB_OTG_DOEPCTL_SODDFRM                   ((uint32_t)0x20000000)            /*!< Set odd frame */
-#define USB_OTG_DOEPCTL_EPTYP                     ((uint32_t)0x000C0000)            /*!< Endpoint type */
-#define USB_OTG_DOEPCTL_EPTYP_0                   ((uint32_t)0x00040000)            /*!<Bit 0 */
-#define USB_OTG_DOEPCTL_EPTYP_1                   ((uint32_t)0x00080000)            /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_SNPM                      ((uint32_t)0x00100000)            /*!< Snoop mode */
-#define USB_OTG_DOEPCTL_STALL                     ((uint32_t)0x00200000)            /*!< STALL handshake */
-#define USB_OTG_DOEPCTL_CNAK                      ((uint32_t)0x04000000)            /*!< Clear NAK */
-#define USB_OTG_DOEPCTL_SNAK                      ((uint32_t)0x08000000)            /*!< Set NAK */
-#define USB_OTG_DOEPCTL_EPDIS                     ((uint32_t)0x40000000)            /*!< Endpoint disable */
-#define USB_OTG_DOEPCTL_EPENA                     ((uint32_t)0x80000000)            /*!< Endpoint enable */
+#define USB_OTG_DOEPCTL_MPSIZ                     (0x000007FFUL)            /*!< Maximum packet size */          /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP                    (0x00008000UL)            /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS                    (0x00020000UL)            /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM            (0x10000000UL)            /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM                   (0x20000000UL)            /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP                     (0x000C0000UL)            /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0                   (0x00040000UL)            /*!<Bit 0 */
+#define USB_OTG_DOEPCTL_EPTYP_1                   (0x00080000UL)            /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_SNPM                      (0x00100000UL)            /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL                     (0x00200000UL)            /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK                      (0x04000000UL)            /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK                      (0x08000000UL)            /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS                     (0x40000000UL)            /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA                     (0x80000000UL)            /*!< Endpoint enable */
 
 /********************  Bit definition forUSB_OTG_DOEPINT register  ********************/
-#define USB_OTG_DOEPINT_XFRC                    ((uint32_t)0x00000001)            /*!< Transfer completed interrupt */
-#define USB_OTG_DOEPINT_EPDISD                  ((uint32_t)0x00000002)            /*!< Endpoint disabled interrupt */
-#define USB_OTG_DOEPINT_STUP                    ((uint32_t)0x00000008)            /*!< SETUP phase done */
-#define USB_OTG_DOEPINT_OTEPDIS                 ((uint32_t)0x00000010)            /*!< OUT token received when endpoint disabled */
-#define USB_OTG_DOEPINT_B2BSTUP                 ((uint32_t)0x00000040)            /*!< Back-to-back SETUP packets received */
-#define USB_OTG_DOEPINT_NYET                    ((uint32_t)0x00004000)            /*!< NYET interrupt */
+#define USB_OTG_DOEPINT_XFRC                    (0x00000001UL)            /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD                  (0x00000002UL)            /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_STUP                    (0x00000008UL)            /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS                 (0x00000010UL)            /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_B2BSTUP                 (0x00000040UL)            /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_NYET                    (0x00004000UL)            /*!< NYET interrupt */
 
 /********************  Bit definition forUSB_OTG_DOEPTSIZ register  ********************/
 
-#define USB_OTG_DOEPTSIZ_XFRSIZ                  ((uint32_t)0x0007FFFF)            /*!< Transfer size */
-#define USB_OTG_DOEPTSIZ_PKTCNT                  ((uint32_t)0x1FF80000)            /*!< Packet count */
+#define USB_OTG_DOEPTSIZ_XFRSIZ                  (0x0007FFFFUL)            /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT                  (0x1FF80000UL)            /*!< Packet count */
 
-#define USB_OTG_DOEPTSIZ_STUPCNT                 ((uint32_t)0x60000000)            /*!< SETUP packet count */
-#define USB_OTG_DOEPTSIZ_STUPCNT_0               ((uint32_t)0x20000000)            /*!<Bit 0 */
-#define USB_OTG_DOEPTSIZ_STUPCNT_1               ((uint32_t)0x40000000)            /*!<Bit 1 */
+#define USB_OTG_DOEPTSIZ_STUPCNT                 (0x60000000UL)            /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0               (0x20000000UL)            /*!<Bit 0 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1               (0x40000000UL)            /*!<Bit 1 */
 
 /********************  Bit definition for PCGCCTL register  ********************/
-#define USB_OTG_PCGCCTL_STOPCLK                 ((uint32_t)0x00000001)            /*!< SETUP packet count */
-#define USB_OTG_PCGCCTL_GATECLK                 ((uint32_t)0x00000002)            /*!<Bit 0 */
-#define USB_OTG_PCGCCTL_PHYSUSP                 ((uint32_t)0x00000010)            /*!<Bit 1 */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_macros
-  * @{
-  */
-
-/******************************* ADC Instances ********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
-
-/******************************* CRC Instances ********************************/
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
-
-/******************************** DMA Instances *******************************/
-#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
-                                              ((INSTANCE) == DMA1_Stream1) || \
-                                              ((INSTANCE) == DMA1_Stream2) || \
-                                              ((INSTANCE) == DMA1_Stream3) || \
-                                              ((INSTANCE) == DMA1_Stream4) || \
-                                              ((INSTANCE) == DMA1_Stream5) || \
-                                              ((INSTANCE) == DMA1_Stream6) || \
-                                              ((INSTANCE) == DMA1_Stream7) || \
-                                              ((INSTANCE) == DMA2_Stream0) || \
-                                              ((INSTANCE) == DMA2_Stream1) || \
-                                              ((INSTANCE) == DMA2_Stream2) || \
-                                              ((INSTANCE) == DMA2_Stream3) || \
-                                              ((INSTANCE) == DMA2_Stream4) || \
-                                              ((INSTANCE) == DMA2_Stream5) || \
-                                              ((INSTANCE) == DMA2_Stream6) || \
-                                              ((INSTANCE) == DMA2_Stream7))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOD) || \
-                                        ((INSTANCE) == GPIOE) || \
-                                        ((INSTANCE) == GPIOH))
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                       ((INSTANCE) == I2C2) || \
-                                       ((INSTANCE) == I2C3))
-
-/******************************** I2S Instances *******************************/
-#define IS_I2S_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == SPI1) || \
-                                    ((INSTANCE) == SPI2) || \
-                                    ((INSTANCE) == SPI3) || \
-                                    ((INSTANCE) == SPI4) || \
-                                    ((INSTANCE) == SPI5))
-
-/*************************** I2S Extended Instances ***************************/
-#define IS_I2S_ALL_INSTANCE_EXT(PERIPH)  (((INSTANCE) == SPI2)    || \
-                                          ((INSTANCE) == SPI3)    || \
-                                          ((INSTANCE) == I2S2ext) || \
-                                          ((INSTANCE) == I2S3ext))
-
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
-                                       ((INSTANCE) == SPI2) || \
-                                       ((INSTANCE) == SPI3) || \
-                                       ((INSTANCE) == SPI4) || \
-                                       ((INSTANCE) == SPI5))
-/*************************** SPI Extended Instances ***************************/
-#define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1)    || \
-                                           ((INSTANCE) == SPI2)    || \
-                                           ((INSTANCE) == SPI3)    || \
-                                           ((INSTANCE) == SPI4)    || \
-                                           ((INSTANCE) == SPI5)    || \
-                                           ((INSTANCE) == I2S2ext) || \
-                                           ((INSTANCE) == I2S3ext))
-
-/****************** TIM Instances : All supported instances *******************/
-#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
-                                   ((INSTANCE) == TIM2)   || \
-                                   ((INSTANCE) == TIM3)   || \
-                                   ((INSTANCE) == TIM4)   || \
-                                   ((INSTANCE) == TIM5)   || \
-                                   ((INSTANCE) == TIM9)   || \
-                                   ((INSTANCE) == TIM10)  || \
-                                   ((INSTANCE) == TIM11))
-
-/************* TIM Instances : at least 1 capture/compare channel *************/
-#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \
-                                         ((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM3)  || \
-                                         ((INSTANCE) == TIM4)  || \
-                                         ((INSTANCE) == TIM5)  || \
-                                         ((INSTANCE) == TIM9)  || \
-                                         ((INSTANCE) == TIM10) || \
-                                         ((INSTANCE) == TIM11))
-
-/************ TIM Instances : at least 2 capture/compare channels *************/
-#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                       ((INSTANCE) == TIM2) || \
-                                       ((INSTANCE) == TIM3) || \
-                                       ((INSTANCE) == TIM4) || \
-                                       ((INSTANCE) == TIM5) || \
-                                       ((INSTANCE) == TIM9))
-
-/************ TIM Instances : at least 3 capture/compare channels *************/
-#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \
-                                         ((INSTANCE) == TIM2) || \
-                                         ((INSTANCE) == TIM3) || \
-                                         ((INSTANCE) == TIM4) || \
-                                         ((INSTANCE) == TIM5))
-
-/************ TIM Instances : at least 4 capture/compare channels *************/
-#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                       ((INSTANCE) == TIM2) || \
-                                       ((INSTANCE) == TIM3) || \
-                                       ((INSTANCE) == TIM4) || \
-                                       ((INSTANCE) == TIM5))
-
-/******************** TIM Instances : Advanced-control timers *****************/
-#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
-
-/******************* TIM Instances : Timer input XOR function *****************/
-#define IS_TIM_XOR_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \
-                                         ((INSTANCE) == TIM2) || \
-                                         ((INSTANCE) == TIM3) || \
-                                         ((INSTANCE) == TIM4) || \
-                                         ((INSTANCE) == TIM5))
-
-/****************** TIM Instances : DMA requests generation (UDE) *************/
-#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                       ((INSTANCE) == TIM2) || \
-                                       ((INSTANCE) == TIM3) || \
-                                       ((INSTANCE) == TIM4) || \
-                                       ((INSTANCE) == TIM5))
-
-/************ TIM Instances : DMA requests generation (CCxDE) *****************/
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                          ((INSTANCE) == TIM2) || \
-                                          ((INSTANCE) == TIM3) || \
-                                          ((INSTANCE) == TIM4) || \
-                                          ((INSTANCE) == TIM5))
-
-/************ TIM Instances : DMA requests generation (COMDE) *****************/
-#define IS_TIM_CCDMA_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
-                                          ((INSTANCE) == TIM2) || \
-                                          ((INSTANCE) == TIM3) || \
-                                          ((INSTANCE) == TIM4) || \
-                                          ((INSTANCE) == TIM5))
-
-/******************** TIM Instances : DMA burst feature ***********************/
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
-                                             ((INSTANCE) == TIM2) || \
-                                             ((INSTANCE) == TIM3) || \
-                                             ((INSTANCE) == TIM4) || \
-                                             ((INSTANCE) == TIM5))
-
-/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
-#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                          ((INSTANCE) == TIM2) || \
-                                          ((INSTANCE) == TIM3) || \
-                                          ((INSTANCE) == TIM4) || \
-                                          ((INSTANCE) == TIM5) || \
-                                          ((INSTANCE) == TIM9))
-
-/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                         ((INSTANCE) == TIM2) || \
-                                         ((INSTANCE) == TIM3) || \
-                                         ((INSTANCE) == TIM4) || \
-                                         ((INSTANCE) == TIM5) || \
-                                         ((INSTANCE) == TIM9))
-
-/********************** TIM Instances : 32 bit Counter ************************/
-#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
-                                              ((INSTANCE) == TIM5))
-
-/***************** TIM Instances : external trigger input availabe ************/
-#define IS_TIM_ETR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
-                                        ((INSTANCE) == TIM2) || \
-                                        ((INSTANCE) == TIM3) || \
-                                        ((INSTANCE) == TIM4) || \
-                                        ((INSTANCE) == TIM5))
-
-/****************** TIM Instances : remapping capability **********************/
-#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM5)  || \
-                                         ((INSTANCE) == TIM11))
-
-/******************* TIM Instances : output(s) available **********************/
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
-    ((((INSTANCE) == TIM1) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM2) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM3) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM4) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM5) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM9) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2)))           \
-    ||                                         \
-    (((INSTANCE) == TIM10) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((INSTANCE) == TIM11) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1))))
-
-/************ TIM Instances : complementary output(s) available ***************/
-#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
-   ((((INSTANCE) == TIM1) &&                    \
-     (((CHANNEL) == TIM_CHANNEL_1) ||           \
-      ((CHANNEL) == TIM_CHANNEL_2) ||           \
-      ((CHANNEL) == TIM_CHANNEL_3))))
-
-/******************** USART Instances : Synchronous mode **********************/
-#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                     ((INSTANCE) == USART2) || \
-                                     ((INSTANCE) == USART6))
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART6))
-
-/****************** UART Instances : Hardware Flow control ********************/
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2) || \
-                                           ((INSTANCE) == USART6))
-
-/********************* UART Instances : Smard card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                         ((INSTANCE) == USART2) || \
-                                         ((INSTANCE) == USART6))
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART6))
-
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
-
-/****************************** SDIO Instances ********************************/
-#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
+#define USB_OTG_PCGCCTL_STOPCLK                 (0x00000001UL)            /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK                 (0x00000002UL)            /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP                 (0x00000010UL)            /*!<Bit 1 */
 
 /****************************** USB Exported Constants ************************/
 #define USB_OTG_FS_HOST_MAX_CHANNEL_NBR                8
@@ -4840,83 +4560,6 @@ USB_OTG_HostChannelTypeDef;
 #define USB_OTG_FS_MAX_OUT_ENDPOINTS                   4    /* Including EP0 */
 #define USB_OTG_FS_TOTAL_FIFO_SIZE                     1280 /* in Bytes */
 
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_types
-  * @{
-  */
-typedef enum
-{
-  RESET = 0,
-  SET = !RESET
-} FlagStatus, ITStatus;
-
-typedef enum
-{
-  DISABLE = 0,
-  ENABLE = !DISABLE
-} FunctionalState;
-#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
-
-typedef enum
-{
-  ERROR = 0,
-  SUCCESS = !ERROR
-} ErrorStatus;
-
-/**
-  * @}
-  */
-
-
-/** @addtogroup Exported_macro
-  * @{
-  */
-#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
-
-#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
-
-#define READ_BIT(REG, BIT)    ((REG) & (BIT))
-
-#define CLEAR_REG(REG)        ((REG) = (0x0))
-
-#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
-
-#define READ_REG(REG)         ((REG))
-
-#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
-
-#define POSITION_VAL(VAL)     (__CLZ(__RBIT(VAL)))
-
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
 #endif /* __STM32F4xx_H */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-
-
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/cmsis-system_stm32f4xx.c b/cmsis-system_stm32f4xx.c
index aa7f978..15951e4 100644
--- a/cmsis-system_stm32f4xx.c
+++ b/cmsis-system_stm32f4xx.c
@@ -76,22 +76,13 @@
   - Wrapped the whole file in #ifdef __ARM_STM32F411__ to not cause conflicts with
     AVR builds.
   - Rebuild SystemInit() and SetSysClock() to get rid of most mbed-files. Please take a look into history.
+  - Rework SetSysClock completely
 */
 
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f4xx_system
-  * @{
-  */
-  
-/** @addtogroup STM32F4xx_System_Private_Includes
-  * @{
-  */
 #ifdef __ARM_STM32F411__
 
 #include "cmsis-stm32f4xx.h"
+#include "arduino_stm32f411.h"
 
 #if !defined  (HSE_VALUE)
   #define HSE_VALUE    ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz */
@@ -101,22 +92,6 @@
   #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
 #endif /* HSI_VALUE */
 
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F4xx_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F4xx_System_Private_Defines
-  * @{
-  */
-
 /*!< Uncomment the following line if you need to relocate your vector Table in
      Internal SRAM. */
 /* #define VECT_TAB_SRAM */
@@ -124,22 +99,10 @@
                                    This value must be a multiple of 0x200. */
 /******************************************************************************/
 
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F4xx_System_Private_Macros
-  * @{
-  */
-
 /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
 #define USE_PLL_HSE_EXTC (1) /* Use external clock */
 #define USE_PLL_HSE_XTAL (1) /* Use external xtal */
 
-/**
-  * @}
-  */
-
 /** @addtogroup STM32F4xx_System_Private_Variables
   * @{
   */
@@ -154,24 +117,6 @@
 uint32_t SystemCoreClock = 16000000;
 const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
 
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
-  * @{
-  */
-
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F4xx_System_Private_Functions
-  * @{
-  */
-
 /**
   * @brief  Setup the microcontroller system
   *         Initialize the FPU setting, vector table location and External memory
@@ -187,19 +132,21 @@ void SystemInit(void)
   #endif
   /* Reset the RCC clock configuration to the default reset state ------------*/
   /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
+  RCC->CR |= RCC_CR_HSION;
 
   /* Reset CFGR register */
   RCC->CFGR = 0x00000000;
 
   /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
+  RCC->CR &= ~(RCC_CR_HSEON |
+               RCC_CR_CSSON |
+               RCC_CR_PLLON);
 
   /* Reset PLLCFGR register */
   RCC->PLLCFGR = 0x24003010;
 
   /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
+  RCC->CR &= ~(RCC_CR_HSEBYP);
 
   /* Disable all interrupts */
   RCC->CIR = 0x00000000;
@@ -209,7 +156,6 @@ void SystemInit(void)
   /* Configure the System clock source, PLL Multiplier and Divider factors,
      AHB/APBx prescalers and Flash settings */
   SetSysClock();
- 
 }
 
 /**
@@ -257,13 +203,13 @@ void SystemCoreClockUpdate(void)
 
   switch (tmp)
   {
-    case 0x00:  /* HSI used as system clock source */
+    case RCC_CFGR_SWS_HSI:  /* HSI used as system clock source */
       SystemCoreClock = HSI_VALUE;
       break;
-    case 0x04:  /* HSE used as system clock source */
+    case RCC_CFGR_SWS_HSE:  /* HSE used as system clock source */
       SystemCoreClock = HSE_VALUE;
       break;
-    case 0x08:  /* PLL used as system clock source */
+    case RCC_CFGR_SWS_PLL:  /* PLL used as system clock source */
 
       /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
          SYSCLK = PLL_VCO / PLL_P
@@ -312,57 +258,61 @@ void SetSysClock(void)
      regarding system frequency refer to product datasheet. */
   RCC->APB1ENR |= RCC_APB1ENR_PWREN;
 
-  MODIFY_REG(PWR->CR, PWR_CR_VOS, PWR_CR_VOS_1);
+  PWR->CR |= PWR_CR_VOS;
   
   /* Enable HSE oscillator and activate PLL with HSE as source */
   /*------------------------------- HSE Configuration ------------------------*/
 
   /* Reset HSEON and HSEBYP bits before configuring the HSE --------------*/
   RCC->CR &= ~(RCC_CR_HSEON);
-  //__HAL_RCC_HSE_CONFIG(RCC_HSE_OFF);
-
-  /* Wait till HSE is disabled */
   while(RCC->CR & RCC_CR_HSERDY);
   
   /* Set the new HSE configuration ---------------------------------------*/
   RCC->CR |= RCC_CR_HSEON;
-  
-  /* Wait till HSE is ready */
   while(!(RCC->CR & RCC_CR_HSERDY));
 
   /*-------------------------------- PLL Configuration -----------------------*/
   /* Disable the main PLL. */
   RCC->CR &= ~(RCC_CR_PLLON);
-  
-  /* Wait till PLL is ready */
   while(RCC->CR & RCC_CR_PLLRDY);
 
   /* Configure the main PLL clock source, multiplication and division factors. */
-  // PLLM_2:      VCO input clock = 2 MHz (8 MHz / 4)
-  // PLLN_6/7:    VCO output clock = 384 MHz (2 MHz * 192)
-  // PLLP_0:      PLLCLK = 96 MHz (384 MHz / 4)
-  // PLLQ_3:      USB clock = 48 MHz (384 MHz / 8) --> 48MHz is best choice for USB
+  // PLLM:      VCO input clock = 2 MHz (8 MHz / 4)
+  // PLLN:      VCO output clock = 384 MHz (2 MHz * 192)
+  // PLLP:      PLLCLK = 96 MHz (384 MHz / 4)
+  // PLLQ:      USB clock = 48 MHz (384 MHz / 8) --> 48MHz is best choice for USB
   #if __SYSTEM_CLOCK == 96000000
-  RCC->PLLCFGR =  RCC_PLLCFGR_PLLSRC_HSE | RCC_PLLCFGR_PLLM_2 | \
-                  RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | \
-                  RCC_PLLCFGR_PLLP_0 | \
-                  RCC_PLLCFGR_PLLQ_3;
+    #define PLLM 4
+    #define PLLN 192
+    #define PLLP 4
+    #define PLLQ 8
   #elif __SYSTEM_CLOCK == 100000000
-  RCC->PLLCFGR =  RCC_PLLCFGR_PLLSRC_HSE | RCC_PLLCFGR_PLLM_2 | \
-                  RCC_PLLCFGR_PLLN_3 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | \
-                  RCC_PLLCFGR_PLLP_0 | \
-                  RCC_PLLCFGR_PLLQ_3;
+    #define PLLM 4
+    #define PLLN 200
+    #define PLLP 4
+    #define PLLQ 8
   #elif __SYSTEM_CLOCK == 108000000
-  RCC->PLLCFGR =  RCC_PLLCFGR_PLLSRC_HSE | RCC_PLLCFGR_PLLM_2 | \
-                  RCC_PLLCFGR_PLLN_3 | RCC_PLLCFGR_PLLN_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | \
-                  RCC_PLLCFGR_PLLP_0 | \
-                  RCC_PLLCFGR_PLLQ_0 | RCC_PLLCFGR_PLLQ_3;
+    #warning You are running the controller out of specification!
+    #define PLLM 4
+    #define PLLN 216
+    #define PLLP 4
+    #define PLLQ 9
+  #elif __SYSTEM_CLOCK == 125000000
+    #warning You are running the controller out of specification!
+    #define PLLM 4
+    #define PLLN 250
+    #define PLLP 4
+    #define PLLQ 10
   #endif
 
+  RCC->PLLCFGR =  RCC_PLLCFGR_PLLSRC_HSE |
+                  ((PLLM << 0) & RCC_PLLCFGR_PLLM) |
+                  ((PLLN << 6) & RCC_PLLCFGR_PLLN) |
+                  (((PLLP/2 - 1) << 16) & RCC_PLLCFGR_PLLP) |
+                  ((PLLQ << 24) & RCC_PLLCFGR_PLLQ);
+
   /* Enable the main PLL. */
   RCC->CR |= RCC_CR_PLLON;
-  
-  /* Wait till PLL is ready */
   while(!(RCC->CR & RCC_CR_PLLRDY));
 
   /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
@@ -373,39 +323,26 @@ void SetSysClock(void)
   if(FLASH_ACR_LATENCY_3WS > (FLASH->ACR & FLASH_ACR_LATENCY))
   {
     /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
-    MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, FLASH_ACR_LATENCY_3WS);
-    /*-------------------------- HCLK Configuration --------------------------*/
-    MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_CFGR_HPRE_DIV1);
-    /*------------------------- SYSCLK Configuration ---------------------------*/
-    MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_CFGR_SW_PLL);
+    FLASH->ACR &= ~(FLASH_ACR_LATENCY);
+    FLASH->ACR |= FLASH_ACR_LATENCY_3WS;
+
+    RCC->CFGR &= ~(RCC_CFGR_HPRE | RCC_CFGR_SW);
+    RCC->CFGR |= RCC_CFGR_HPRE_DIV1 | RCC_CFGR_SW_PLL;
   }
   /* Decreasing the CPU frequency */
   else
   {
-    /*-------------------------- HCLK Configuration --------------------------*/
-    MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_CFGR_HPRE_DIV1);
-    /*------------------------- SYSCLK Configuration -------------------------*/
-    MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_CFGR_SW_PLL);
+    RCC->CFGR &= ~(RCC_CFGR_HPRE | RCC_CFGR_SW);
+    RCC->CFGR |= RCC_CFGR_HPRE_DIV1 | RCC_CFGR_SW_PLL;
+
     /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
-    MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, FLASH_ACR_LATENCY_3WS);
+    FLASH->ACR &= ~(FLASH_ACR_LATENCY);
+    FLASH->ACR |= FLASH_ACR_LATENCY_3WS;
   }
 
-  /*-------------------------- PCLK1 Configuration ---------------------------*/
-  MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_CFGR_PPRE1_DIV2);
-  /*-------------------------- PCLK2 Configuration ---------------------------*/
-  MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, RCC_CFGR_PPRE2_DIV1);
+  RCC->CFGR &= ~(RCC_CFGR_PPRE1 | RCC_CFGR_PPRE2);
+  RCC->CFGR |= PPRE1_DIV | PPRE2_DIV;
 }
 
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
 #endif
diff --git a/cmsis-system_stm32f4xx.h b/cmsis-system_stm32f4xx.h
index 6b7ad9e..c57ef09 100644
--- a/cmsis-system_stm32f4xx.h
+++ b/cmsis-system_stm32f4xx.h
@@ -41,16 +41,9 @@
 
   - Prefixed names of #include files with cmsis- to match the names of the
     copies in the Teacup repo.
-
+  - Cleanup file
+  - Add different clock frequencies
 */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f4xx_system
-  * @{
-  */
   
 /**
   * @brief Define to prevent recursive inclusion
@@ -65,59 +58,15 @@
 // #define __SYSTEM_CLOCK 96000000
 #define __SYSTEM_CLOCK 100000000
 // #define __SYSTEM_CLOCK 108000000 // Overclocking is not recommended!
-/** @addtogroup STM32F4xx_System_Includes
-  * @{
-  */
 
-/**
-  * @}
-  */
-
-
-/** @addtogroup STM32F4xx_System_Exported_types
-  * @{
-  */
-  /* This variable is updated in three ways:
-      1) by calling CMSIS function SystemCoreClockUpdate()
-      2) by calling HAL API function HAL_RCC_GetSysClockFreq()
-      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
-         Note: If you use this function to configure the system clock; then there
-               is no need to call the 2 first functions listed above, since SystemCoreClock
-               variable is updated automatically.
-  */
+/* 
+  This variable is updated in by calling CMSIS function SystemCoreClockUpdate()
+*/
 extern uint32_t SystemCoreClock;          /*!< System Clock Frequency (Core Clock) */
 
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F4xx_System_Exported_Constants
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F4xx_System_Exported_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F4xx_System_Exported_Functions
-  * @{
-  */
-  
 extern void SystemInit(void);
 extern void SystemCoreClockUpdate(void);
 extern void SetSysClock(void);
-/**
-  * @}
-  */
 
 #ifdef __cplusplus
 }
@@ -125,11 +74,4 @@ extern void SetSysClock(void);
 
 #endif /*__SYSTEM_STM32F4XX_H */
 
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/