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stm32: enable the ART accelerator 

See also RM0383 Embedded Flash memory interface
3.4.2 Adaptive real-time memory accelerator
- instruction prefetch
- instruction cache memory
- data management
This commit is contained in:
Nico Tonnhofer 2017-07-27 13:12:00 +02:00
parent 7581c0038d
commit 2af85e348f
1 changed files with 13 additions and 0 deletions
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13
cmsis-system_stm32f4xx.c
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@ -332,6 +332,17 @@ void SetSysClock(void)
#define PLLP 2 #define PLLP 2
#define PLLQ 8 #define PLLQ 8
#define LATENCY FLASH_ACR_LATENCY_5WS #define LATENCY FLASH_ACR_LATENCY_5WS
#elif __SYSTEM_CLOCK == 250000000
#if !defined(STM32F446xx)
#error You are running the controller out of specification! 250 MHz!
#else
#warning You are running the controller out of specification! 250 MHz!
#endif
#define PLLM 4
#define PLLN 250
#define PLLP 2
#define PLLQ 9
#define LATENCY FLASH_ACR_LATENCY_5WS
#endif #endif
RCC->PLLCFGR = RCC_PLLCFGR_PLLSRC_HSE | RCC->PLLCFGR = RCC_PLLCFGR_PLLSRC_HSE |
@ -369,6 +380,8 @@ void SetSysClock(void)
FLASH->ACR |= LATENCY; FLASH->ACR |= LATENCY;
} }
FLASH->ACR |= FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN;
RCC->CFGR &= ~(RCC_CFGR_PPRE1 | RCC_CFGR_PPRE2); RCC->CFGR &= ~(RCC_CFGR_PPRE1 | RCC_CFGR_PPRE2);
RCC->CFGR |= PPRE1_DIV | PPRE2_DIV; RCC->CFGR |= PPRE1_DIV | PPRE2_DIV;