STM32F411: get rid of mbed-core_cmFunc.h and mbed-core_cmInstr.h.

move some functions of them to mbed-core_cm4.h

Makefile-ARM

@@ -121,13 +121,13 @@ SOURCES = $(wildcard *.c)
 ifeq ($(MCU), stm32f411)
   SOURCES += mbed-pinmap_stm32.c
   SOURCES += mbed-system_stm32f4xx.c
+  SOURCES += mbed-cmsis_nvic_stm32.c
   SOURCES += mbed-stm32f4xx_hal.c
   SOURCES += mbed-stm32f4xx_hal_cortex.c
   SOURCES += mbed-stm32f4xx_hal_gpio.c
   SOURCES += mbed-stm32f4xx_hal_rcc.c
   SOURCES += mbed-stm32f4xx_hal_tim.c
   SOURCES += mbed-ticker_api.c
-  SOURCES += mbed-cmsis_nvic_stm32.c
   SOURCES += mbed-hal_tick_stm32.c
 endif
 

mbed-core_cm4.h

@@ -42,8 +42,9 @@
   impossible to see wether code changes work. Should go away soon, because
   all this MBED stuff is too bloated for Teacup's purposes.
 
-  - Prefixed names of #include files with mbed- to match the names of the
+  - Replaced __DSB(); with __ASM volatile ("dsb").
-    copies in the Teacup repo.
+  - Added from mbed-core_cmFunc.h: __enable_irq() and __disable_irq()\
+  - Added from mbed-core_cmInstr: __CLZ and __RBIT
 */
 
 #if defined ( __ICCARM__ )
@@ -177,10 +178,60 @@
 #endif
 
 #include <stdint.h>                      /* standard types definitions                      */
-#include "mbed-core_cmInstr.h"                /* Core Instruction Access                         */
+//#include "mbed-core_cmInstr.h"                /* Core Instruction Access                         */
-#include "mbed-core_cmFunc.h"                 /* Core Function Access                            */
+//#include "mbed-core_cmFunc.h"                 /* Core Function Access                            */
 #include "mbed-core_cm4_simd.h"               /* Compiler specific SIMD Intrinsics               */
 
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
+{
+   uint32_t result;
+
+  __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+   return(result);
+}
+
+/** \brief  Enable IRQ Interrupts
+
+  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i" : : : "memory");
+}
+
+/** \brief  Disable IRQ Interrupts
+
+  This function disables IRQ interrupts by setting the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i" : : : "memory");
+}
+
 #endif /* __CORE_CM4_H_GENERIC */
 
 #ifndef __CMSIS_GENERIC
@@ -1648,12 +1699,12 @@ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr
  */
 __STATIC_INLINE void NVIC_SystemReset(void)
 {
-  __DSB();                                                     /* Ensure all outstanding memory accesses included
+  __ASM volatile ("dsb");                                                     /* Ensure all outstanding memory accesses included
                                                                   buffered write are completed before reset */
   SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
                  (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
                  SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
-  __DSB();                                                     /* Ensure completion of memory access */
+  __ASM volatile ("dsb");                                                     /* Ensure completion of memory access */
   while(1);                                                    /* wait until reset */
 }
 

mbed-hal_tick_stm32.c

@@ -44,7 +44,7 @@ void us_ticker_irq_handler(void);
 void timer_irq_handler(void) {
     // Channel 1 for mbed timeout
     if (__HAL_TIM_GET_ITSTATUS(&TimMasterHandle, TIM_IT_CC1) == SET) {
-        us_ticker_irq_handler();
+        //us_ticker_irq_handler();
     }
 
     // Channel 2 for HAL tick
@@ -79,7 +79,7 @@ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) {
     // Configure time base
     TimMasterHandle.Instance = TIM_MST;
     TimMasterHandle.Init.Period            = 0xFFFFFFFF;
-    TimMasterHandle.Init.Prescaler         = (uint32_t)(SystemCoreClock / 1000000) - 1; // 1 µs tick
+    TimMasterHandle.Init.Prescaler         = (uint32_t)(SystemCoreClock / 1000000) - 1; // 1 <EFBFBD>s tick
     TimMasterHandle.Init.ClockDivision     = 0;
     TimMasterHandle.Init.CounterMode       = TIM_COUNTERMODE_UP;
     TimMasterHandle.Init.RepetitionCounter = 0;

mbed-stm32f4xx.h

@@ -371,7 +371,7 @@ typedef struct
   __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
   __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */
   __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */
-  __IO uint32_t BSRR;     /*!< GPIO port bit set/reset register,      Address offset: 0x18      */
+  __IO uint32_t BSRR;     /*!< GPIO port bit set/reset register       Address offset: 0x18      */
   __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */
   __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
 } GPIO_TypeDef;