stm32: correct some clock settings
This commit is contained in:
parent
b62bad1b0a
commit
7581c0038d
|
|
@ -24,8 +24,8 @@
|
||||||
*/
|
*/
|
||||||
#define RX_UART1 PA_10
|
#define RX_UART1 PA_10
|
||||||
#define TX_UART1 PA_9
|
#define TX_UART1 PA_9
|
||||||
#define RX_UART2 PA_3
|
#define RX_UART2 PA_3
|
||||||
#define TX_UART2 PA_2
|
#define TX_UART2 PA_2
|
||||||
#define RX_UART6 PA_12
|
#define RX_UART6 PA_12
|
||||||
#define TX_UART6 PA_11
|
#define TX_UART6 PA_11
|
||||||
|
|
||||||
|
|
@ -33,8 +33,13 @@
|
||||||
*/
|
*/
|
||||||
#define F_CPU __SYSTEM_CLOCK
|
#define F_CPU __SYSTEM_CLOCK
|
||||||
|
|
||||||
#define PPRE1_DIV (RCC_CFGR_PPRE1_DIV2) // 0x1000
|
#if defined STM32F411xE
|
||||||
#define PPRE2_DIV (RCC_CFGR_PPRE2_DIV1) // 0x0000
|
#define PPRE1_DIV (RCC_CFGR_PPRE1_DIV2)
|
||||||
|
#define PPRE2_DIV (RCC_CFGR_PPRE2_DIV1)
|
||||||
|
#elif defined STM32F446xx
|
||||||
|
#define PPRE1_DIV (RCC_CFGR_PPRE1_DIV4)
|
||||||
|
#define PPRE2_DIV (RCC_CFGR_PPRE2_DIV2)
|
||||||
|
#endif
|
||||||
|
|
||||||
#if PPRE1_DIV > 0
|
#if PPRE1_DIV > 0
|
||||||
#define APB1_DIV (1 << ((PPRE1_DIV >> 10) - 3))
|
#define APB1_DIV (1 << ((PPRE1_DIV >> 10) - 3))
|
||||||
|
|
|
||||||
|
|
@ -325,7 +325,7 @@ void SetSysClock(void)
|
||||||
#define LATENCY FLASH_ACR_LATENCY_2WS
|
#define LATENCY FLASH_ACR_LATENCY_2WS
|
||||||
#elif __SYSTEM_CLOCK == 180000000
|
#elif __SYSTEM_CLOCK == 180000000
|
||||||
#if !defined(STM32F446xx)
|
#if !defined(STM32F446xx)
|
||||||
#warning You are running the controller out of specification! 180 MHz!
|
#error You are running the controller out of specification! 180 MHz!
|
||||||
#endif
|
#endif
|
||||||
#define PLLM 4
|
#define PLLM 4
|
||||||
#define PLLN 180
|
#define PLLN 180
|
||||||
|
|
@ -371,6 +371,8 @@ void SetSysClock(void)
|
||||||
|
|
||||||
RCC->CFGR &= ~(RCC_CFGR_PPRE1 | RCC_CFGR_PPRE2);
|
RCC->CFGR &= ~(RCC_CFGR_PPRE1 | RCC_CFGR_PPRE2);
|
||||||
RCC->CFGR |= PPRE1_DIV | PPRE2_DIV;
|
RCC->CFGR |= PPRE1_DIV | PPRE2_DIV;
|
||||||
|
|
||||||
|
RCC->DCKCFGR |= RCC_DCKCFGR_TIMPRE;
|
||||||
}
|
}
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
|
|
|
||||||
|
|
@ -55,10 +55,6 @@
|
||||||
extern "C" {
|
extern "C" {
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
// #define __SYSTEM_CLOCK 96000000
|
|
||||||
// #define __SYSTEM_CLOCK 100000000
|
|
||||||
// #define __SYSTEM_CLOCK 108000000 // Overclocking is not recommended!
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
This variable is updated in by calling CMSIS function SystemCoreClockUpdate()
|
This variable is updated in by calling CMSIS function SystemCoreClockUpdate()
|
||||||
*/
|
*/
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue