ARM: prettify cmsis-lpc11xx.h.
This is, remove trailing whitespace and such stuff. Log of all changes near the top of the file.
This commit is contained in:
Markus Hitter
parent
a7240523e1
commit
d1c624f0c5
137
cmsis-lpc11xx.h
137
cmsis-lpc11xx.h
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@ -1,11 +1,11 @@
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/****************************************************************************
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* $Id:: LPC11xx.h 9198 2012-05-29 usb00175 $
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* Project: NXP LPC11xx software example
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* Project: NXP LPC11xx software example
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*
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* Description:
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* CMSIS Cortex-M0 Core Peripheral Access Layer Header File for
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* NXP LPC11xx Device Series
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* CMSIS Cortex-M0 Core Peripheral Access Layer Header File for
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* NXP LPC11xx Device Series
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****************************************************************************
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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@ -18,32 +18,31 @@
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* warranty that such application will be suitable for the specified
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* use without further testing or modification.
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors'
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* relevant copyright in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors'
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* relevant copyright in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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****************************************************************************/
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/*
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Notes for Teacup:
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Copied in spring 2015 from https://github.com/mbedmicro/mbed, file
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mbed/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/LPC11xx.h
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Copied from $(MBED)/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/LPC11xx.h.
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Changes for Teacup:
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Used only to get things running quickly. Without serial it's almost
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impossible to see wether code changes work. Should go away soon, because
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all this MBED stuff is too bloated for Teacup's purposes.
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- Prefixed names of #include files with mbed- to match the names of the
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- Prefixed names of #include files with cmsis- to match the names of the
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copies in the Teacup repo.
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- Removed long === runs to not disturb grep'ing for them on Git conflicts.
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- Replaced tabs by spaces and removed trailing whitespace.
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*/
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#ifndef __LPC11xx_H__
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#define __LPC11xx_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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#endif
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/** @addtogroup LPC11xx_Definitions LPC11xx Definitions
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This file defines all structures and symbols for LPC11xx:
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@ -64,9 +63,7 @@
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*/
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/*
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* ==========================================================================
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* ---------- Interrupt Number Definition -----------------------------------
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* ==========================================================================
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*/
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typedef enum IRQn
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{
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@ -82,15 +79,15 @@ typedef enum IRQn
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WAKEUP1_IRQn = 1, /*!< There are 13 pins in total for LPC11xx */
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WAKEUP2_IRQn = 2,
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WAKEUP3_IRQn = 3,
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WAKEUP4_IRQn = 4,
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WAKEUP5_IRQn = 5,
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WAKEUP6_IRQn = 6,
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WAKEUP7_IRQn = 7,
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WAKEUP8_IRQn = 8,
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WAKEUP9_IRQn = 9,
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WAKEUP10_IRQn = 10,
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WAKEUP11_IRQn = 11,
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WAKEUP12_IRQn = 12,
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WAKEUP4_IRQn = 4,
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WAKEUP5_IRQn = 5,
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WAKEUP6_IRQn = 6,
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WAKEUP7_IRQn = 7,
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WAKEUP8_IRQn = 8,
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WAKEUP9_IRQn = 9,
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WAKEUP10_IRQn = 10,
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WAKEUP11_IRQn = 11,
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WAKEUP12_IRQn = 12,
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CAN_IRQn = 13, /*!< CAN Interrupt */
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SSP1_IRQn = 14, /*!< SSP1 Interrupt */
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I2C_IRQn = 15, /*!< I2C Interrupt */
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@ -101,9 +98,9 @@ typedef enum IRQn
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SSP0_IRQn = 20, /*!< SSP0 Interrupt */
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UART_IRQn = 21, /*!< UART Interrupt */
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Reserved0_IRQn = 22, /*!< Reserved Interrupt */
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Reserved1_IRQn = 23,
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Reserved1_IRQn = 23,
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ADC_IRQn = 24, /*!< A/D Converter Interrupt */
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WDT_IRQn = 25, /*!< Watchdog timer Interrupt */
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WDT_IRQn = 25, /*!< Watchdog timer Interrupt */
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BOD_IRQn = 26, /*!< Brown Out Detect(BOD) Interrupt */
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FMC_IRQn = 27, /*!< Flash Memory Controller Interrupt */
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EINT3_IRQn = 28, /*!< External Interrupt 3 Interrupt */
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@ -113,9 +110,7 @@ typedef enum IRQn
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} IRQn_Type;
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/*
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* ==========================================================================
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* ----------- Processor and Core Peripheral Section ------------------------
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* ==========================================================================
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*/
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/* Configuration of the Cortex-M0 Processor and Core Peripherals */
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@ -126,8 +121,8 @@ typedef enum IRQn
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/*@}*/ /* end of group LPC11xx_CMSIS */
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#include "mbed-core_cm0.h" /* Cortex-M0 processor and core peripherals */
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#include "mbed-system_LPC11xx.h" /* System Header */
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#include "mbed-core_cm0.h" /* Cortex-M0 processor and core peripherals */
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#include "mbed-system_LPC11xx.h" /* System Header */
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/******************************************************************************/
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@ -139,7 +134,7 @@ typedef enum IRQn
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#endif
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/*------------- System Control (SYSCON) --------------------------------------*/
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/** @addtogroup LPC11xx_SYSCON LPC11xx System Control Block
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/** @addtogroup LPC11xx_SYSCON LPC11xx System Control Block
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@{
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*/
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typedef struct
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@ -156,7 +151,7 @@ typedef struct
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uint32_t RESERVED1[1];
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__IO uint32_t SYSRSTSTAT; /*!< Offset: 0x030 System reset status Register (R/ ) */
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uint32_t RESERVED2[3];
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__IO uint32_t SYSPLLCLKSEL; /*!< Offset: 0x040 System PLL clock source select (R/W) */
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__IO uint32_t SYSPLLCLKSEL; /*!< Offset: 0x040 System PLL clock source select (R/W) */
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__IO uint32_t SYSPLLCLKUEN; /*!< Offset: 0x044 System PLL clock source update enable (R/W) */
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uint32_t RESERVED3[10];
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@ -167,42 +162,42 @@ typedef struct
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__IO uint32_t SYSAHBCLKCTRL; /*!< Offset: 0x080 System AHB clock control (R/W) */
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uint32_t RESERVED5[4];
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__IO uint32_t SSP0CLKDIV; /*!< Offset: 0x094 SSP0 clock divider (R/W) */
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__IO uint32_t SSP0CLKDIV; /*!< Offset: 0x094 SSP0 clock divider (R/W) */
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__IO uint32_t UARTCLKDIV; /*!< Offset: 0x098 UART clock divider (R/W) */
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__IO uint32_t SSP1CLKDIV; /*!< Offset: 0x09C SSP1 clock divider (R/W) */
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__IO uint32_t SSP1CLKDIV; /*!< Offset: 0x09C SSP1 clock divider (R/W) */
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uint32_t RESERVED6[12];
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__IO uint32_t WDTCLKSEL; /*!< Offset: 0x0D0 WDT clock source select (R/W) */
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__IO uint32_t WDTCLKUEN; /*!< Offset: 0x0D4 WDT clock source update enable (R/W) */
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__IO uint32_t WDTCLKDIV; /*!< Offset: 0x0D8 WDT clock divider (R/W) */
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uint32_t RESERVED8[1];
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uint32_t RESERVED8[1];
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__IO uint32_t CLKOUTCLKSEL; /*!< Offset: 0x0E0 CLKOUT clock source select (R/W) */
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__IO uint32_t CLKOUTUEN; /*!< Offset: 0x0E4 CLKOUT clock source update enable (R/W) */
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__IO uint32_t CLKOUTDIV; /*!< Offset: 0x0E8 CLKOUT clock divider (R/W) */
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__IO uint32_t CLKOUTDIV; /*!< Offset: 0x0E8 CLKOUT clock divider (R/W) */
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uint32_t RESERVED9[5];
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__IO uint32_t PIOPORCAP0; /*!< Offset: 0x100 POR captured PIO status 0 (R/ ) */
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__IO uint32_t PIOPORCAP1; /*!< Offset: 0x104 POR captured PIO status 1 (R/ ) */
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__IO uint32_t PIOPORCAP0; /*!< Offset: 0x100 POR captured PIO status 0 (R/ ) */
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__IO uint32_t PIOPORCAP1; /*!< Offset: 0x104 POR captured PIO status 1 (R/ ) */
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uint32_t RESERVED10[18];
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__IO uint32_t BODCTRL; /*!< Offset: 0x150 BOD control (R/W) */
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__IO uint32_t SYSTCKCAL; /*!< Offset: 0x154 System tick counter calibration (R/W) */
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uint32_t RESERVED13[7];
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__IO uint32_t NMISRC; /*!< Offset: 0x174 NMI source selection register (R/W) */
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uint32_t RESERVED14[34];
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__IO uint32_t STARTAPRP0; /*!< Offset: 0x200 Start logic edge control Register 0 (R/W) */
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__IO uint32_t STARTERP0; /*!< Offset: 0x204 Start logic signal enable Register 0 (R/W) */
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__IO uint32_t STARTAPRP0; /*!< Offset: 0x200 Start logic edge control Register 0 (R/W) */
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__IO uint32_t STARTERP0; /*!< Offset: 0x204 Start logic signal enable Register 0 (R/W) */
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__O uint32_t STARTRSRP0CLR; /*!< Offset: 0x208 Start logic reset Register 0 ( /W) */
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__I uint32_t STARTSRP0; /*!< Offset: 0x20C Start logic status Register 0 (R/) */
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__IO uint32_t STARTAPRP1; /*!< Offset: 0x210 Start logic edge control Register 0 (R/W). (LPC11UXX only) */
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__IO uint32_t STARTERP1; /*!< Offset: 0x214 Start logic signal enable Register 0 (R/W). (LPC11UXX only) */
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__IO uint32_t STARTAPRP1; /*!< Offset: 0x210 Start logic edge control Register 0 (R/W). (LPC11UXX only) */
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__IO uint32_t STARTERP1; /*!< Offset: 0x214 Start logic signal enable Register 0 (R/W). (LPC11UXX only) */
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__O uint32_t STARTRSRP1CLR; /*!< Offset: 0x218 Start logic reset Register 0 ( /W). (LPC11UXX only) */
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__IO uint32_t STARTSRP1; /*!< Offset: 0x21C Start logic status Register 0 (R/W). (LPC11UXX only) */
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uint32_t RESERVED17[4];
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__IO uint32_t PDSLEEPCFG; /*!< Offset: 0x230 Power-down states in Deep-sleep mode (R/W) */
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__IO uint32_t PDAWAKECFG; /*!< Offset: 0x234 Power-down states after wake-up (R/W) */
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__IO uint32_t PDAWAKECFG; /*!< Offset: 0x234 Power-down states after wake-up (R/W) */
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__IO uint32_t PDRUNCFG; /*!< Offset: 0x238 Power-down configuration Register (R/W) */
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uint32_t RESERVED15[110];
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__I uint32_t DEVICE_ID; /*!< Offset: 0x3F4 Device ID (R/ ) */
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@ -211,7 +206,7 @@ typedef struct
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/*------------- Pin Connect Block (IOCON) --------------------------------*/
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/** @addtogroup LPC11xx_IOCON LPC11xx I/O Configuration Block
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/** @addtogroup LPC11xx_IOCON LPC11xx I/O Configuration Block
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@{
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*/
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typedef struct
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@ -281,7 +276,7 @@ typedef struct
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/*------------- Power Management Unit (PMU) --------------------------*/
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/** @addtogroup LPC11xx_PMU LPC11xx Power Management Unit
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/** @addtogroup LPC11xx_PMU LPC11xx Power Management Unit
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@{
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*/
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typedef struct
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@ -320,7 +315,7 @@ typedef struct { /*!< (@ 0x4003C000) FLASHCTRL Struct
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/*------------- General Purpose Input/Output (GPIO) --------------------------*/
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/** @addtogroup LPC11xx_GPIO LPC11xx General Purpose Input/Output
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/** @addtogroup LPC11xx_GPIO LPC11xx General Purpose Input/Output
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@{
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*/
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typedef struct
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@ -345,7 +340,7 @@ typedef struct
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/*@}*/ /* end of group LPC11xx_GPIO */
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/*------------- Timer (TMR) --------------------------------------------------*/
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/** @addtogroup LPC11xx_TMR LPC11xx 16/32-bit Counter/Timer
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/** @addtogroup LPC11xx_TMR LPC11xx 16/32-bit Counter/Timer
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@{
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*/
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typedef struct
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@ -378,7 +373,7 @@ typedef struct
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/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
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/** @addtogroup LPC11xx_UART LPC11xx Universal Asynchronous Receiver/Transmitter
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/** @addtogroup LPC11xx_UART LPC11xx Universal Asynchronous Receiver/Transmitter
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@{
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*/
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typedef struct
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@ -416,7 +411,7 @@ typedef struct
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/*------------- Synchronous Serial Communication (SSP) -----------------------*/
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/** @addtogroup LPC11xx_SSP LPC11xx Synchronous Serial Port
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/** @addtogroup LPC11xx_SSP LPC11xx Synchronous Serial Port
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@{
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*/
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typedef struct
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@ -435,7 +430,7 @@ typedef struct
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/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
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/** @addtogroup LPC11xx_I2C LPC11xx I2C-Bus Interface
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/** @addtogroup LPC11xx_I2C LPC11xx I2C-Bus Interface
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@{
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*/
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typedef struct
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@ -461,7 +456,7 @@ typedef struct
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/*------------- Watchdog Timer (WDT) -----------------------------------------*/
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/** @addtogroup LPC11xx_WDT LPC11xx WatchDog Timer
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/** @addtogroup LPC11xx_WDT LPC11xx WatchDog Timer
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@{
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*/
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typedef struct
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@ -471,14 +466,14 @@ typedef struct
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__O uint32_t FEED; /*!< Offset: 0x008 Watchdog feed sequence register (W) */
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__I uint32_t TV; /*!< Offset: 0x00C Watchdog timer value register (R) */
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uint32_t RESERVED0;
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__IO uint32_t WARNINT; /*!< Offset: 0x014 Watchdog timer warning int. register (R/W) */
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__IO uint32_t WINDOW; /*!< Offset: 0x018 Watchdog timer window value register (R/W) */
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__IO uint32_t WARNINT; /*!< Offset: 0x014 Watchdog timer warning int. register (R/W) */
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__IO uint32_t WINDOW; /*!< Offset: 0x018 Watchdog timer window value register (R/W) */
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} LPC_WDT_TypeDef;
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/*@}*/ /* end of group LPC11xx_WDT */
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/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
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/** @addtogroup LPC11xx_ADC LPC11xx Analog-to-Digital Converter
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/** @addtogroup LPC11xx_ADC LPC11xx Analog-to-Digital Converter
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@{
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*/
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typedef struct
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@ -494,12 +489,12 @@ typedef struct
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/*------------- CAN Controller (CAN) ----------------------------*/
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/** @addtogroup LPC11xx_CAN LPC11xx Controller Area Network(CAN)
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/** @addtogroup LPC11xx_CAN LPC11xx Controller Area Network(CAN)
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@{
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*/
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typedef struct
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{
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__IO uint32_t CNTL; /* 0x000 */
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__IO uint32_t CNTL; /* 0x000 */
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__IO uint32_t STAT;
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__IO uint32_t EC;
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__IO uint32_t BT;
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@ -507,7 +502,7 @@ typedef struct
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__IO uint32_t TEST;
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__IO uint32_t BRPE;
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uint32_t RESERVED0;
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__IO uint32_t IF1_CMDREQ; /* 0x020 */
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__IO uint32_t IF1_CMDREQ; /* 0x020 */
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__IO uint32_t IF1_CMDMSK;
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__IO uint32_t IF1_MSK1;
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__IO uint32_t IF1_MSK2;
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@ -518,8 +513,8 @@ typedef struct
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__IO uint32_t IF1_DA2;
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__IO uint32_t IF1_DB1;
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__IO uint32_t IF1_DB2;
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uint32_t RESERVED1[13];
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__IO uint32_t IF2_CMDREQ; /* 0x080 */
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uint32_t RESERVED1[13];
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__IO uint32_t IF2_CMDREQ; /* 0x080 */
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__IO uint32_t IF2_CMDMSK;
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__IO uint32_t IF2_MSK1;
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__IO uint32_t IF2_MSK2;
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@ -531,19 +526,19 @@ typedef struct
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__IO uint32_t IF2_DB1;
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__IO uint32_t IF2_DB2;
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uint32_t RESERVED2[21];
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__I uint32_t TXREQ1; /* 0x100 */
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__I uint32_t TXREQ1; /* 0x100 */
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__I uint32_t TXREQ2;
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uint32_t RESERVED3[6];
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__I uint32_t ND1; /* 0x120 */
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__I uint32_t ND1; /* 0x120 */
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__I uint32_t ND2;
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uint32_t RESERVED4[6];
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__I uint32_t IR1; /* 0x140 */
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__I uint32_t IR1; /* 0x140 */
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__I uint32_t IR2;
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uint32_t RESERVED5[6];
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__I uint32_t MSGV1; /* 0x160 */
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__I uint32_t MSGV1; /* 0x160 */
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__I uint32_t MSGV2;
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uint32_t RESERVED6[6];
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__IO uint32_t CLKDIV; /* 0x180 */
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__IO uint32_t CLKDIV; /* 0x180 */
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} LPC_CAN_TypeDef;
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/*@}*/ /* end of group LPC11xx_CAN */
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