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STM32F411: save cpu cycles are 160 

Also, first interrupt should not occur at 0.
This commit is contained in:
Nico Tonnhofer 2016-08-08 19:25:26 +02:00
parent ab03852750
commit d9a350749d
1 changed files with 4 additions and 3 deletions
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7
timer-stm32.c
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@ -74,6 +74,7 @@ void timer_init() {
*/ */
RCC->APB1ENR |= RCC_APB1ENR_TIM5EN; // Turn on TIM5 power. RCC->APB1ENR |= RCC_APB1ENR_TIM5EN; // Turn on TIM5 power.
TIM5->CCR1 = 0xFFFFFFFF; // First timer should not occur at 0
TIM5->CR1 &= ~(0x03FF); // clear register TIM5->CR1 &= ~(0x03FF); // clear register
TIM5->CR1 |= TIM_CR1_CEN; // Enable counter. TIM5->CR1 |= TIM_CR1_CEN; // Enable counter.
@ -176,14 +177,14 @@ uint8_t timer_set(int32_t delay, uint8_t check_short) {
#ifdef ACCELERATION_TEMPORAL #ifdef ACCELERATION_TEMPORAL
if (check_short) { if (check_short) {
/** /**
100 = safe number of cpu cycles after current_time to allow a new 160 = safe number of cpu cycles after current_time to allow a new
interrupt happening. This is mostly the time needed to complete the interrupt happening. This is mostly the time needed to complete the
current interrupt. current interrupt. The interrupt needs up to 152 cycles.
TIM5->CNT = timer counter = current time. TIM5->CNT = timer counter = current time.
TIM5->CCR1 = last capture compare = time of the last step. TIM5->CCR1 = last capture compare = time of the last step.
*/ */
if ((TIM5->CNT - TIM5->CCR1) + 100 > delay) if ((TIM5->CNT - TIM5->CCR1) + 160 > delay)
return 1; return 1;
} }
#endif /* ACCELERATION_TEMPORAL */ #endif /* ACCELERATION_TEMPORAL */