diff --git a/mbed-system_LPC11xx.c b/mbed-system_LPC11xx.c index ccf6e16..856f403 100644 --- a/mbed-system_LPC11xx.c +++ b/mbed-system_LPC11xx.c @@ -37,219 +37,18 @@ - Silenced this warning: system_LPC11xx.c:344:21: warning: unused variable 'i' by declaring i directly where it's used and renaming the other to 'j'. + - Moved definitions to system_LPC11xx.h to have them available elsewhere. + Replaced by this marker: + // Moved definitions from here to system_LPC11xx.h. + and replaced #include with #include "mbed-system_LPC11xx.h" */ #ifdef __ARMEL__ -#include +#include "mbed-system_LPC11xx.h" #include "mbed-LPC11xx.h" -/* -//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -*/ - -/*--------------------- Clock Configuration ---------------------------------- -// -// Clock Configuration -// System Oscillator Control Register (SYSOSCCTRL) -// BYPASS: System Oscillator Bypass Enable -// If enabled then PLL input (sys_osc_clk) is fed -// directly from XTALIN and XTALOUT pins. -// FREQRANGE: System Oscillator Frequency Range -// Determines frequency range for Low-power oscillator. -// <0=> 1 - 20 MHz -// <1=> 15 - 25 MHz -// -// -// Watchdog Oscillator Control Register (WDTOSCCTRL) -// DIVSEL: Select Divider for Fclkana -// wdt_osc_clk = Fclkana/ (2 * (1 + DIVSEL)) -// <0-31> -// FREQSEL: Select Watchdog Oscillator Analog Output Frequency (Fclkana) -// <0=> Undefined -// <1=> 0.5 MHz -// <2=> 0.8 MHz -// <3=> 1.1 MHz -// <4=> 1.4 MHz -// <5=> 1.6 MHz -// <6=> 1.8 MHz -// <7=> 2.0 MHz -// <8=> 2.2 MHz -// <9=> 2.4 MHz -// <10=> 2.6 MHz -// <11=> 2.7 MHz -// <12=> 2.9 MHz -// <13=> 3.1 MHz -// <14=> 3.2 MHz -// <15=> 3.4 MHz -// -// -// System PLL Control Register (SYSPLLCTRL) -// F_clkout = M * F_clkin = F_CCO / (2 * P) -// F_clkin must be in the range of 10 MHz to 25 MHz -// F_CCO must be in the range of 156 MHz to 320 MHz -// MSEL: Feedback Divider Selection -// M = MSEL + 1 -// <0-31> -// PSEL: Post Divider Selection -// <0=> P = 1 -// <1=> P = 2 -// <2=> P = 4 -// <3=> P = 8 -// -// -// System PLL Clock Source Select Register (SYSPLLCLKSEL) -// SEL: System PLL Clock Source -// <0=> IRC Oscillator -// <1=> System Oscillator -// <2=> Reserved -// <3=> Reserved -// -// -// Main Clock Source Select Register (MAINCLKSEL) -// SEL: Clock Source for Main Clock -// <0=> IRC Oscillator -// <1=> Input Clock to System PLL -// <2=> WDT Oscillator -// <3=> System PLL Clock Out -// -// -// System AHB Clock Divider Register (SYSAHBCLKDIV) -// DIV: System AHB Clock Divider -// Divides main clock to provide system clock to core, memories, and peripherals. -// 0 = is disabled -// <0-255> -// -// -*/ -#define CLOCK_SETUP 1 -#define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000 -#define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000 -#define SYSPLLCTRL_Val 0x00000023 // Reset: 0x000 -#define SYSPLLCLKSEL_Val 0x00000000 // Reset: 0x000 // Define as using IRC -#define MAINCLKSEL_Val 0x00000003 // Reset: 0x000 // Define as using System PLL clock out -#define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001 - -/* -//-------- <<< end of configuration section >>> ------------------------------ -*/ - -/*---------------------------------------------------------------------------- - Check the register settings - *----------------------------------------------------------------------------*/ -#define CHECK_RANGE(val, min, max) ((val < min) || (val > max)) -#define CHECK_RSVD(val, mask) (val & mask) - -/* Clock Configuration -------------------------------------------------------*/ -#if (CHECK_RSVD((SYSOSCCTRL_Val), ~0x00000003)) - #error "SYSOSCCTRL: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((WDTOSCCTRL_Val), ~0x000001FF)) - #error "WDTOSCCTRL: Invalid values of reserved bits!" -#endif - -#if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 2)) - #error "SYSPLLCLKSEL: Value out of range!" -#endif - -#if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x000001FF)) - #error "SYSPLLCTRL: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((MAINCLKSEL_Val), ~0x00000003)) - #error "MAINCLKSEL: Invalid values of reserved bits!" -#endif - -#if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255)) - #error "SYSAHBCLKDIV: Value out of range!" -#endif - - -/*---------------------------------------------------------------------------- - DEFINES - *----------------------------------------------------------------------------*/ - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define __XTAL (12000000UL) /* Oscillator frequency */ -#define __SYS_OSC_CLK ( __XTAL) /* Main oscillator frequency */ -#define __IRC_OSC_CLK (12000000UL) /* Internal RC oscillator frequency */ - - -#define __FREQSEL ((WDTOSCCTRL_Val >> 5) & 0x0F) -#define __DIVSEL (((WDTOSCCTRL_Val & 0x1F) << 1) + 2) - -#if (CLOCK_SETUP) /* Clock Setup */ - #if (__FREQSEL == 0) - #define __WDT_OSC_CLK ( 0) /* undefined */ - #elif (__FREQSEL == 1) - #define __WDT_OSC_CLK ( 500000 / __DIVSEL) - #elif (__FREQSEL == 2) - #define __WDT_OSC_CLK ( 800000 / __DIVSEL) - #elif (__FREQSEL == 3) - #define __WDT_OSC_CLK (1100000 / __DIVSEL) - #elif (__FREQSEL == 4) - #define __WDT_OSC_CLK (1400000 / __DIVSEL) - #elif (__FREQSEL == 5) - #define __WDT_OSC_CLK (1600000 / __DIVSEL) - #elif (__FREQSEL == 6) - #define __WDT_OSC_CLK (1800000 / __DIVSEL) - #elif (__FREQSEL == 7) - #define __WDT_OSC_CLK (2000000 / __DIVSEL) - #elif (__FREQSEL == 8) - #define __WDT_OSC_CLK (2200000 / __DIVSEL) - #elif (__FREQSEL == 9) - #define __WDT_OSC_CLK (2400000 / __DIVSEL) - #elif (__FREQSEL == 10) - #define __WDT_OSC_CLK (2600000 / __DIVSEL) - #elif (__FREQSEL == 11) - #define __WDT_OSC_CLK (2700000 / __DIVSEL) - #elif (__FREQSEL == 12) - #define __WDT_OSC_CLK (2900000 / __DIVSEL) - #elif (__FREQSEL == 13) - #define __WDT_OSC_CLK (3100000 / __DIVSEL) - #elif (__FREQSEL == 14) - #define __WDT_OSC_CLK (3200000 / __DIVSEL) - #else - #define __WDT_OSC_CLK (3400000 / __DIVSEL) - #endif - - /* sys_pllclkin calculation */ - #if ((SYSPLLCLKSEL_Val & 0x03) == 0) - #define __SYS_PLLCLKIN (__IRC_OSC_CLK) - #elif ((SYSPLLCLKSEL_Val & 0x03) == 1) - #define __SYS_PLLCLKIN (__SYS_OSC_CLK) - #else - #define __SYS_PLLCLKIN (0) - #endif - - #define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1)) - - /* main clock calculation */ - #if ((MAINCLKSEL_Val & 0x03) == 0) - #define __MAIN_CLOCK (__IRC_OSC_CLK) - #elif ((MAINCLKSEL_Val & 0x03) == 1) - #define __MAIN_CLOCK (__SYS_PLLCLKIN) - #elif ((MAINCLKSEL_Val & 0x03) == 2) - #if (__FREQSEL == 0) - #error "MAINCLKSEL: WDT Oscillator selected but FREQSEL is undefined!" - #else - #define __MAIN_CLOCK (__WDT_OSC_CLK) - #endif - #elif ((MAINCLKSEL_Val & 0x03) == 3) - #define __MAIN_CLOCK (__SYS_PLLCLKOUT) - #else - #define __MAIN_CLOCK (0) - #endif - - #define __SYSTEM_CLOCK (__MAIN_CLOCK / SYSAHBCLKDIV_Val) - -#else - #define __SYSTEM_CLOCK (__IRC_OSC_CLK) -#endif // CLOCK_SETUP - +// Moved definitions from here to system_LPC11xx.h. /*---------------------------------------------------------------------------- Clock Variable definitions diff --git a/mbed-system_LPC11xx.h b/mbed-system_LPC11xx.h index 9326539..04fa272 100644 --- a/mbed-system_LPC11xx.h +++ b/mbed-system_LPC11xx.h @@ -9,9 +9,9 @@ * Copyright (C) 2009-2010 ARM Limited. All rights reserved. * * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. * * @par * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED @@ -32,6 +32,11 @@ - Prefixed names of #include files with mbed- to match the names of the copies in the Teacup repo. + - Moved all the definitions from system_LPC11xx.h to here to have them + available elsewhere. It's the section between + // From system_LPC11xx.c start. + and + // From system_LPC11xx.c start. */ @@ -44,6 +49,215 @@ extern "C" { #include +// From system_LPC11xx.c start. +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + +/*--------------------- Clock Configuration ---------------------------------- +// +// Clock Configuration +// System Oscillator Control Register (SYSOSCCTRL) +// BYPASS: System Oscillator Bypass Enable +// If enabled then PLL input (sys_osc_clk) is fed +// directly from XTALIN and XTALOUT pins. +// FREQRANGE: System Oscillator Frequency Range +// Determines frequency range for Low-power oscillator. +// <0=> 1 - 20 MHz +// <1=> 15 - 25 MHz +// +// +// Watchdog Oscillator Control Register (WDTOSCCTRL) +// DIVSEL: Select Divider for Fclkana +// wdt_osc_clk = Fclkana/ (2 * (1 + DIVSEL)) +// <0-31> +// FREQSEL: Select Watchdog Oscillator Analog Output Frequency (Fclkana) +// <0=> Undefined +// <1=> 0.5 MHz +// <2=> 0.8 MHz +// <3=> 1.1 MHz +// <4=> 1.4 MHz +// <5=> 1.6 MHz +// <6=> 1.8 MHz +// <7=> 2.0 MHz +// <8=> 2.2 MHz +// <9=> 2.4 MHz +// <10=> 2.6 MHz +// <11=> 2.7 MHz +// <12=> 2.9 MHz +// <13=> 3.1 MHz +// <14=> 3.2 MHz +// <15=> 3.4 MHz +// +// +// System PLL Control Register (SYSPLLCTRL) +// F_clkout = M * F_clkin = F_CCO / (2 * P) +// F_clkin must be in the range of 10 MHz to 25 MHz +// F_CCO must be in the range of 156 MHz to 320 MHz +// MSEL: Feedback Divider Selection +// M = MSEL + 1 +// <0-31> +// PSEL: Post Divider Selection +// <0=> P = 1 +// <1=> P = 2 +// <2=> P = 4 +// <3=> P = 8 +// +// +// System PLL Clock Source Select Register (SYSPLLCLKSEL) +// SEL: System PLL Clock Source +// <0=> IRC Oscillator +// <1=> System Oscillator +// <2=> Reserved +// <3=> Reserved +// +// +// Main Clock Source Select Register (MAINCLKSEL) +// SEL: Clock Source for Main Clock +// <0=> IRC Oscillator +// <1=> Input Clock to System PLL +// <2=> WDT Oscillator +// <3=> System PLL Clock Out +// +// +// System AHB Clock Divider Register (SYSAHBCLKDIV) +// DIV: System AHB Clock Divider +// Divides main clock to provide system clock to core, memories, and peripherals. +// 0 = is disabled +// <0-255> +// +// +*/ +#define CLOCK_SETUP 1 +#define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000 +#define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000 +#define SYSPLLCTRL_Val 0x00000023 // Reset: 0x000 +#define SYSPLLCLKSEL_Val 0x00000000 // Reset: 0x000 // Define as using IRC +#define MAINCLKSEL_Val 0x00000003 // Reset: 0x000 // Define as using System PLL clock out +#define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001 + +/* +//-------- <<< end of configuration section >>> ------------------------------ +*/ + +/*---------------------------------------------------------------------------- + Check the register settings + *----------------------------------------------------------------------------*/ +#define CHECK_RANGE(val, min, max) ((val < min) || (val > max)) +#define CHECK_RSVD(val, mask) (val & mask) + +/* Clock Configuration -------------------------------------------------------*/ +#if (CHECK_RSVD((SYSOSCCTRL_Val), ~0x00000003)) + #error "SYSOSCCTRL: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((WDTOSCCTRL_Val), ~0x000001FF)) + #error "WDTOSCCTRL: Invalid values of reserved bits!" +#endif + +#if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 2)) + #error "SYSPLLCLKSEL: Value out of range!" +#endif + +#if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x000001FF)) + #error "SYSPLLCTRL: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((MAINCLKSEL_Val), ~0x00000003)) + #error "MAINCLKSEL: Invalid values of reserved bits!" +#endif + +#if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255)) + #error "SYSAHBCLKDIV: Value out of range!" +#endif + + +/*---------------------------------------------------------------------------- + DEFINES + *----------------------------------------------------------------------------*/ + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define __XTAL (12000000UL) /* Oscillator frequency */ +#define __SYS_OSC_CLK ( __XTAL) /* Main oscillator frequency */ +#define __IRC_OSC_CLK (12000000UL) /* Internal RC oscillator frequency */ + + +#define __FREQSEL ((WDTOSCCTRL_Val >> 5) & 0x0F) +#define __DIVSEL (((WDTOSCCTRL_Val & 0x1F) << 1) + 2) + +#if (CLOCK_SETUP) /* Clock Setup */ + #if (__FREQSEL == 0) + #define __WDT_OSC_CLK ( 0) /* undefined */ + #elif (__FREQSEL == 1) + #define __WDT_OSC_CLK ( 500000 / __DIVSEL) + #elif (__FREQSEL == 2) + #define __WDT_OSC_CLK ( 800000 / __DIVSEL) + #elif (__FREQSEL == 3) + #define __WDT_OSC_CLK (1100000 / __DIVSEL) + #elif (__FREQSEL == 4) + #define __WDT_OSC_CLK (1400000 / __DIVSEL) + #elif (__FREQSEL == 5) + #define __WDT_OSC_CLK (1600000 / __DIVSEL) + #elif (__FREQSEL == 6) + #define __WDT_OSC_CLK (1800000 / __DIVSEL) + #elif (__FREQSEL == 7) + #define __WDT_OSC_CLK (2000000 / __DIVSEL) + #elif (__FREQSEL == 8) + #define __WDT_OSC_CLK (2200000 / __DIVSEL) + #elif (__FREQSEL == 9) + #define __WDT_OSC_CLK (2400000 / __DIVSEL) + #elif (__FREQSEL == 10) + #define __WDT_OSC_CLK (2600000 / __DIVSEL) + #elif (__FREQSEL == 11) + #define __WDT_OSC_CLK (2700000 / __DIVSEL) + #elif (__FREQSEL == 12) + #define __WDT_OSC_CLK (2900000 / __DIVSEL) + #elif (__FREQSEL == 13) + #define __WDT_OSC_CLK (3100000 / __DIVSEL) + #elif (__FREQSEL == 14) + #define __WDT_OSC_CLK (3200000 / __DIVSEL) + #else + #define __WDT_OSC_CLK (3400000 / __DIVSEL) + #endif + + /* sys_pllclkin calculation */ + #if ((SYSPLLCLKSEL_Val & 0x03) == 0) + #define __SYS_PLLCLKIN (__IRC_OSC_CLK) + #elif ((SYSPLLCLKSEL_Val & 0x03) == 1) + #define __SYS_PLLCLKIN (__SYS_OSC_CLK) + #else + #define __SYS_PLLCLKIN (0) + #endif + + #define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1)) + + /* main clock calculation */ + #if ((MAINCLKSEL_Val & 0x03) == 0) + #define __MAIN_CLOCK (__IRC_OSC_CLK) + #elif ((MAINCLKSEL_Val & 0x03) == 1) + #define __MAIN_CLOCK (__SYS_PLLCLKIN) + #elif ((MAINCLKSEL_Val & 0x03) == 2) + #if (__FREQSEL == 0) + #error "MAINCLKSEL: WDT Oscillator selected but FREQSEL is undefined!" + #else + #define __MAIN_CLOCK (__WDT_OSC_CLK) + #endif + #elif ((MAINCLKSEL_Val & 0x03) == 3) + #define __MAIN_CLOCK (__SYS_PLLCLKOUT) + #else + #define __MAIN_CLOCK (0) + #endif + + #define __SYSTEM_CLOCK (__MAIN_CLOCK / SYSAHBCLKDIV_Val) + +#else + #define __SYSTEM_CLOCK (__IRC_OSC_CLK) +#endif // CLOCK_SETUP +// From system_LPC11xx.c end. + + extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ @@ -64,7 +278,7 @@ extern void SystemInit (void); * @param none * @return none * - * @brief Updates the SystemCoreClock with current core Clock + * @brief Updates the SystemCoreClock with current core Clock * retrieved from cpu registers. */ extern void SystemCoreClockUpdate (void); diff --git a/serial-arm.c b/serial-arm.c index ac52cb6..c85fc87 100644 --- a/serial-arm.c +++ b/serial-arm.c @@ -14,6 +14,7 @@ #if defined TEACUP_C_INCLUDE && defined __ARMEL__ #include "arduino.h" +#include "mbed-LPC11xx.h" #ifdef XONXOFF #error XON/XOFF protocol not yet implemented for ARM. \