126 lines
2.6 KiB
C
126 lines
2.6 KiB
C
#include "timer.h"
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#include <avr/interrupt.h>
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#include "dda_queue.h"
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volatile uint32_t next_step_time;
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uint8_t clock_counter_10ms = 0;
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uint8_t clock_counter_250ms = 0;
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uint8_t clock_counter_1s = 0;
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volatile uint8_t clock_flag = 0;
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// timer overflow, happens every TICK_TIME
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ISR(TIMER1_CAPT_vect) {
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/*
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check if next step time will occur before next overflow
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*/
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if (next_step_time > TICK_TIME)
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next_step_time -= TICK_TIME;
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else if (next_step_time > 0) {
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OCR1A = next_step_time & 0xFFFF;
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TIMSK1 |= MASK(OCIE1A);
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}
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/*
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clock stuff
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*/
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clock_counter_10ms += TICK_TIME_MS;
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if (clock_counter_10ms >= 10) {
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clock_counter_10ms -= 10;
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clock_flag |= CLOCK_FLAG_10MS;
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clock_counter_250ms += 1;
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if (clock_counter_250ms >= 25) {
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clock_counter_250ms -= 25;
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clock_flag |= CLOCK_FLAG_250MS;
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clock_counter_1s += 1;
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if (clock_counter_1s >= 4) {
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clock_counter_1s -= 4;
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clock_flag |= CLOCK_FLAG_1S;
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}
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}
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}
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}
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void timer1_compa_isr(void) __attribute__ ((hot));
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void timer1_compa_isr() {
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// led on
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WRITE(SCK, 1);
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// disable this interrupt. if we set a new timeout, it will be re-enabled when appropriate
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TIMSK1 &= ~MASK(OCIE1A);
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// ensure we don't interrupt again unless timer is reset
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next_step_time = 0;
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// stepper tick
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queue_step();
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// led off
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WRITE(SCK, 0);
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}
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ISR(TIMER1_COMPA_vect) {
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timer1_compa_isr();
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}
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void timer_init()
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{
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// no outputs
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TCCR1A = 0;
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// CTC mode- use ICR for top
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TCCR1B = MASK(WGM13) | MASK(WGM12) | MASK(CS10);
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// set timeout- first timeout is indeterminate, probably doesn't matter
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ICR1 = TICK_TIME;
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// overflow interrupt (uses input capture interrupt in CTC:ICR mode)
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TIMSK1 = MASK(ICIE1);
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}
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void setTimer(uint32_t delay)
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{
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// save interrupt flag
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uint8_t sreg = SREG;
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// disable interrupts
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cli();
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// re-enable clock interrupt in case we're recovering from emergency stop
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TIMSK1 |= MASK(ICIE1);
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if (delay > 0) {
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// mangle timer variables
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next_step_time = delay + TCNT1;
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if (delay <= 16) {
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// unfortunately, force registers don't trigger an interrupt, so we do the following
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// don't step from timer interrupt
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next_step_time = 0;
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// "fire" ISR- maybe it sets a new timeout
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timer1_compa_isr();
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}
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else if (next_step_time <= TICK_TIME) {
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// next step occurs before overflow, set comparator here
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OCR1A = next_step_time & 0xFFFF;
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TIMSK1 |= MASK(OCIE1A);
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}
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else {
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// adjust next_step_time so overflow interrupt sets the correct timeout
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next_step_time -= TICK_TIME;
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}
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}
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else {
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next_step_time = 0;
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}
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// restore interrupt flag
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SREG = sreg;
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}
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void timer_stop() {
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// disable all interrupts
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TIMSK1 = 0;
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// reset timeout
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next_step_time = 0;
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}
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