189 lines
5.9 KiB
C
189 lines
5.9 KiB
C
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/** \file
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\brief MCU pin mappings.
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Here we map the pins required by Teacup to the names known by CMSIS.
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*/
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/** I/O pins.
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In MBED, I/O pin handling is rather complicated. Lots of enums, lots of
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functions, spread over various files, slow execution (pin toggling about
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15 times slower than what we have here).
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Accordingly, the strategy for FastIO is derived directly from the data sheet.
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There one can see that hardware is very similar to that of AVRs: pins grouped
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in ports (here: 12 pins per port) and a number of additional registers with
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bits for additional proterties: wether input or output, wether a pullup is
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attached, and so on. See chapter 12 of the LPC111x User Manual. Other than
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AVRs, many ARMs (including the LPC1114) support bit-banding, which is
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interrupt safe and also a few clock cycles faster. See macros in pinio.h.
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*/
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#include "mbed-LPC11xx.h"
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/**
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Offsets to the various GPIO registers. See chapter 12.3 in LPC111x User
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Manual.
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*/
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#define IO_MASK_OFFSET 0x0000 // Bit-masked data registers.
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#define IO_DATA_OFFSET 0x3FFC // Data register.
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#define IO_DIR_OFFSET 0x8000 // Data direction register.
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#define IO_IS_OFFSET 0x8004 // Interrupt sense register.
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#define IO_IBE_OFFSET 0x8008 // Interrupt both edges register.
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#define IO_IEV_OFFSET 0x800C // Interrupt event register.
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#define IO_IE_OFFSET 0x8010 // Interrupt mask register.
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#define IO_RIS_OFFSET 0x8014 // Raw interrupt status register.
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#define IO_MIS_OFFSET 0x8018 // Masked interrupt status register.
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#define IO_IC_OFFSET 0x801C // Interrupt clear register.
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/**
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Masks to handle the pulling function. All IOCON registers for pins do this on
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bits [4:3]. 'Or' them with xxx_OUTPUT (see below) to get the requested
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functionality.
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Note that PIO0_4 and PIO0_5 are always open drain, no pullup possible. Mask
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bits are "reserved" on these two.
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*/
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#define IO_MODEMASK_INACTIVE (0x00 << 3)
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#define IO_MODEMASK_PULLDOWN (0x01 << 3)
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#define IO_MODEMASK_PULLUP (0x02 << 3)
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#define IO_MODEMASK_REPEATER (0x03 << 3)
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/**
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We define only pins available on the DIP28/TSSOP28 package here, because
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the LPC1114FN28/102 is currently the only LPC1114 known to be used in a
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RepRap controller. We also use pin names as defined in the User Manual, for
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(hopefully) least disambiguation.
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Description:
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xxx_CMSIS Stupid MBED uses an inconsistent naming scheme in
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LPC_IOCON_TypeDef, so we have to map these names to the
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standard naming pattern.
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xxx_PIN Pin number. Can be used to calculate the port mask and also
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the bitbanding address.
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xxx_PORT Base address of the corresponding GPIO register. For offsets
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see above.
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xxx_OUTPUT Bits to set/clear to set this pin as GPIO output in the IOCON
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register. See chapter 7.4 of the User Manual. FUNC as I/O pin,
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MODE inactive (no pullup or pulldown), no hysteresis, no
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analog function, no open drain.
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To achieve appropriate pulling behaviour for inputs, 'or'
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this value with one of the IO_MODEMASKs.
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*/
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// Reset pin. Don't use.
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//#define PIO0_0_CMSIS RESET_PIO0_0
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//#define PIO0_0_PIN 0
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//#define PIO0_0_PORT LPC_GPIO0
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//#define PIO0_0_OUTPUT (0x01 << 0)
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#define PIO0_1_CMSIS PIO0_1
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#define PIO0_1_PIN 1
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#define PIO0_1_PORT LPC_GPIO0
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#define PIO0_1_OUTPUT 0x00
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#define PIO0_2_CMSIS PIO0_2
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#define PIO0_2_PIN 2
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#define PIO0_2_PORT LPC_GPIO0
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#define PIO0_2_OUTPUT 0x00
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#define PIO0_3_CMSIS PIO0_3
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#define PIO0_3_PIN 3
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#define PIO0_3_PORT LPC_GPIO0
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#define PIO0_3_OUTPUT 0x00
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#define PIO0_4_CMSIS PIO0_4
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#define PIO0_4_PIN 4
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#define PIO0_4_PORT LPC_GPIO0
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#define PIO0_4_OUTPUT (0x01 << 8)
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#define PIO0_5_CMSIS PIO0_5
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#define PIO0_5_PIN 5
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#define PIO0_5_PORT LPC_GPIO0
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#define PIO0_5_OUTPUT (0x01 << 8)
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#define PIO0_6_CMSIS PIO0_6
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#define PIO0_6_PIN 6
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#define PIO0_6_PORT LPC_GPIO0
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#define PIO0_6_OUTPUT 0x00
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#define PIO0_7_CMSIS PIO0_7
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#define PIO0_7_PIN 7
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#define PIO0_7_PORT LPC_GPIO0
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#define PIO0_7_OUTPUT 0x00
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#define PIO0_8_CMSIS PIO0_8
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#define PIO0_8_PIN 8
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#define PIO0_8_PORT LPC_GPIO0
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#define PIO0_8_OUTPUT 0x00
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#define PIO0_9_CMSIS PIO0_9
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#define PIO0_9_PIN 9
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#define PIO0_9_PORT LPC_GPIO0
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#define PIO0_9_OUTPUT 0x00
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#define PIO0_10_CMSIS SWCLK_PIO0_10
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#define PIO0_10_PIN 10
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#define PIO0_10_PORT LPC_GPIO0
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#define PIO0_10_OUTPUT (0x01 << 0)
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#define PIO0_11_CMSIS R_PIO0_11
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#define PIO0_11_PIN 11
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#define PIO0_11_PORT LPC_GPIO0
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#define PIO0_11_OUTPUT ((0x01 << 0) | (0x01 << 7))
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#define PIO1_0_CMSIS R_PIO1_0
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#define PIO1_0_PIN 0
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#define PIO1_0_PORT LPC_GPIO1
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#define PIO1_0_OUTPUT ((0x01 << 0) | (0x01 << 7))
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#define PIO1_1_CMSIS R_PIO1_1
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#define PIO1_1_PIN 1
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#define PIO1_1_PORT LPC_GPIO1
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#define PIO1_1_OUTPUT ((0x01 << 0) | (0x01 << 7))
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#define PIO1_2_CMSIS R_PIO1_2
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#define PIO1_2_PIN 2
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#define PIO1_2_PORT LPC_GPIO1
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#define PIO1_2_OUTPUT ((0x01 << 0) | (0x01 << 7))
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#define PIO1_3_CMSIS SWDIO_PIO1_3
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#define PIO1_3_PIN 3
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#define PIO1_3_PORT LPC_GPIO1
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#define PIO1_3_OUTPUT ((0x01 << 0) | (0x01 << 7))
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#define PIO1_4_CMSIS PIO1_4
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#define PIO1_4_PIN 4
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#define PIO1_4_PORT LPC_GPIO1
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#define PIO1_4_OUTPUT (0x01 << 7)
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#define PIO1_5_CMSIS PIO1_5
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#define PIO1_5_PIN 5
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#define PIO1_5_PORT LPC_GPIO1
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#define PIO1_5_OUTPUT 0x00
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#define PIO1_6_CMSIS PIO1_6
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#define PIO1_6_PIN 6
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#define PIO1_6_PORT LPC_GPIO1
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#define PIO1_6_OUTPUT 0x00
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#define PIO1_7_CMSIS PIO1_7
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#define PIO1_7_PIN 7
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#define PIO1_7_PORT LPC_GPIO1
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#define PIO1_7_OUTPUT 0x00
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#define PIO1_8_CMSIS PIO1_8
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#define PIO1_8_PIN 8
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#define PIO1_8_PORT LPC_GPIO1
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#define PIO1_8_OUTPUT 0x00
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#define PIO1_9_CMSIS PIO1_9
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#define PIO1_9_PIN 9
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#define PIO1_9_PORT LPC_GPIO1
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#define PIO1_9_OUTPUT 0x00
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