230 lines
7.5 KiB
C
230 lines
7.5 KiB
C
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/** \file
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\brief Timer management, ARM specific part.
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To be included from timer.c.
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*/
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#if defined TEACUP_C_INCLUDE && defined __ARM_STM32__
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#include "cmsis-core_cm4.h"
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#include "clock.h"
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#include "pinio.h"
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#include "dda_queue.h"
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/** Timer initialisation.
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Initialise timer and enable system clock interrupt. Step interrupt is
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enabled later, when we start using it.
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For the system clock, we use SysTickTimer. This timer is made for exactly
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such purposes.
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Other than AVRs, Cortex-M doesn't allow reentry of interupts. To deal with
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this we use another interrupt, PendSV, with slightly lower priority and
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without an interrupt source. The possibly lengthy operation in dda_clock()
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goes into there and at the end of the SysTick interrupt we simply set PendSV
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pending. This way PendSV is executed right after SysTick or, if PendSV is
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already running, ignored.
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*/
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void timer_init() {
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/**
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Initialise the system tick timer
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We enable the system tick timer with interrupts. A similar function is
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SysTick_Config(uint32_t ticks) in cmsis-core_cm4.h
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Register name mapping from STM32F4xx
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SYST_CSR SysTick->CTRL System Timer Control and status register.
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SYST_RVR SysTick->LOAD System Timer Reload value register.
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SYST_CVR SysTick->VAL System Timer Current value register.
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SYST_CALIB SysTick->CALIB System Timer Calibration value register.
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*/
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NVIC_SetPriorityGrouping(1);
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NVIC_SetPriority(SysTick_IRQn,
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NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 1, 0));
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//NVIC_SetPriority(SysTick_IRQn, 2); // Highest priority.
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// SysTick defined in cmsis-core_cm4.h.
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SysTick->LOAD = TICK_TIME - 1; // set reload register
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SysTick->VAL = 0; // Load the SysTick Counter Value
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SysTick->CTRL = SysTick_CTRL_ENABLE_Msk // Enable the ticker.
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| SysTick_CTRL_TICKINT_Msk // Enable interrupt.
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| SysTick_CTRL_CLKSOURCE_Msk; // Run at full CPU clock.
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/**
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Initialise PendSV for dda_clock().
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*/
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NVIC_SetPriority(PendSV_IRQn,
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NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 2, 0)); // Almost highest priority.
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/**
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Initialise the stepper timer. On ARM we have the comfort of hardware
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32-bit timers, so we don't have to artifically extend the timer to this
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size. We use match register 1 of the first 32-bit timer, TIM5.
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We run the timer all the time, just turn the interrupt on and off, to
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allow interrupts equally spaced, independent from processing time. See
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also description of timer_set().
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*/
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RCC->APB1ENR |= RCC_APB1ENR_TIM5EN; // Turn on TIM5 power.
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TIM5->CCR1 = 0xFFFFFFFF; // First timer should not occur at 0
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TIM5->CR1 &= ~(0x03FF); // clear register
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TIM5->CR1 |= TIM_CR1_CEN; // Enable counter.
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NVIC_SetPriority(TIM5_IRQn,
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NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 0, 0)); // Also highest priority.
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NVIC_EnableIRQ(TIM5_IRQn); // Enable interrupt generally.
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}
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/** System clock interrupt.
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Happens every TICK_TIME. Must have the same name as in
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cmsis-startup_stm32f411xe.s
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*/
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void SysTick_Handler(void) {
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clock_tick();
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SCB->ICSR = SCB_ICSR_PENDSVSET_Msk; // Trigger PendSV_Handler().
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}
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/** System clock interrupt, slow part.
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Here we do potentially lengthy calculations. Must have the same name as in
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cmsis-startup_stm32f411xe.s
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*/
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void PendSV_Handler(void) {
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dda_clock();
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}
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/** Step interrupt.
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Happens for every stepper motor step. Must have the same name as in
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cmsis-startup_stm32f411xe.s
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TIM2 and TIM5 are 32bit timers. We use TIM5, because depending pins have
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an alternative timer for pwm.
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*/
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void TIM5_IRQHandler(void) {
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#ifdef DEBUG_LED_PIN
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WRITE(DEBUG_LED_PIN, 1);
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#endif
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/**
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Turn off interrupt generation, timer counter continues. As this interrupt
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is the only use of this timer, there's no need for a read-modify-write.
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*/
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TIM5->DIER = 0;
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/**
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We have to "reset" this interrupt, else it'll be triggered over and over
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again.
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*/
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TIM5->SR = 0;
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queue_step();
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#ifdef DEBUG_LED_PIN
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WRITE(DEBUG_LED_PIN, 0);
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#endif
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}
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/** Specify how long until the step timer should fire.
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\param delay Delay for the next step interrupt, in CPU ticks.
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\param check_short Tell whether to check for impossibly short requests. This
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should be set to 1 for calls from the step interrupt. Short requests
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then return 1 and do not schedule a timer interrupt. The calling code
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usually wants to handle this case.
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Calls from elsewhere should set it to 0. In this case a timer
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interrupt is always scheduled.
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\return A flag whether the requested time was too short to allow scheduling
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an interrupt. This is meaningful for ACCELERATION_TEMPORAL, where
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requested delays can be zero or even negative. In this case, the
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calling code should repeat the stepping code immediately and also
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assume the timer to not change his idea of when the last step
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happened.
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Strategy of this timer is to schedule timer interrupts not starting at the
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time of the call, but starting at the time of the previous timer interrupt
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fired. This ignores the processing time taken in the step interrupt so far,
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offering smooth and even step distribution. Flipside of this coin is,
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schedules issued at an arbitrary time can result in drastically wrong delays.
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See also discussion of parameter check_short and the return value.
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This enables the step interrupt, but also disables interrupts globally.
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So, if you use it from inside the step interrupt, make sure to do so
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as late as possible. If you use it from outside the step interrupt,
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do a sei() after it to make the interrupt actually fire.
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On ARM we have the comfort of hardware 32-bit timers, so we don't have to
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artifically extend the timer to this size. We use match register 1 of the
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first 32-bit timer, TIM5.
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*/
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uint8_t timer_set(int32_t delay, uint8_t check_short) {
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#ifdef ACCELERATION_TEMPORAL
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if (check_short) {
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/**
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160 = safe number of cpu cycles after current_time to allow a new
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interrupt happening. This is mostly the time needed to complete the
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current interrupt. The interrupt needs up to 152 cycles.
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TIM5->CNT = timer counter = current time.
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TIM5->CCR1 = last capture compare = time of the last step.
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*/
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if ((TIM5->CNT - TIM5->CCR1) + 160 > delay)
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return 1;
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}
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#endif /* ACCELERATION_TEMPORAL */
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/**
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Still here? Then we can schedule the next step. Off of the previous step.
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If there is no previous step, CNT and CCR1 should have been reset to zero
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by calling timer_reset() shortly before we arrive here.
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*/
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TIM5->CCR1 += delay;
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/**
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Turn on the stepper interrupt. As this interrupt is the only use of this
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timer, there's no need for a read-modify-write.
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*/
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TIM5->DIER = TIM_DIER_CC1IE; // Interrupt on MR0 match.
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return 0;
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}
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/** Timer reset.
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Reset the timer, so step interrupts scheduled at an arbitrary point in time
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don't lead to a full round through the timer counter.
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On ARM we actually do something, such a full round through the timer is
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2^32 / F_CPU = 22 to 44 seconds.
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*/
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void timer_reset() {
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TIM5->CNT = 0;
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TIM5->CCR1 = 0;
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}
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/** Stop timers.
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This means to be an emergency stop.
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*/
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void timer_stop() {
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SysTick->CTRL = 0;
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}
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#endif /* defined TEACUP_C_INCLUDE && defined __ARM_STM32__ */
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