527 lines
17 KiB
C
527 lines
17 KiB
C
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/** \file
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\brief I2C / TWI subsystem
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"TWI", "Two Wire Interface", is Atmel's name for the (patented) I2C bus
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system. I2C is technically pretty sophisticated, it also takes the current
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state of these two wires as part of the protocol into account. Like SPI it's
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a master/slave system with a clock signal on the wire. Unlike SPI,
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communication partners aren't choosen by setting a pin, but by by
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transferring an address byte before the actual data.
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Accordingly, code has to deal with states, transmissions have a start and
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an end, and actions on the bus can result in different states, like success
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or failure.
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avr-libc comes with good sample code:
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http://www.nongnu.org/avr-libc/examples/twitest/twitest.c
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For technical details see section 22 of atmega328 datasheet.
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*/
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#include "i2c.h"
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#ifdef I2C
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#include <avr/io.h>
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#include <avr/interrupt.h>
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#include <util/twi.h>
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#include "delay.h"
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#include "pinio.h"
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#include "memory_barrier.h"
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#if defined I2C_MASTER_MODE && defined I2C_SLAVE_MODE
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#error Cant be I2C master and slave at the same time.
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#endif
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#if defined I2C_SLAVE_MODE || defined I2C_READ_SUPPORT || \
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defined I2C_EEPROM_SUPPORT
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#warning These portions of the code are untested and need work.
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#endif
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#ifdef I2C_SLAVE_MODE
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#define I2C_MODE 1
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#else
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#define I2C_MODE 0
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#endif
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#define I2C_MODE_MASK 0b00001100
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// Start-Addr_R-Read-Stop: just read mode.
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#define I2C_MODE_SARP 0b00000000
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// Start-Addr_W-Write-Stop: just write mode.
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#define I2C_MODE_SAWP 0b00000100
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// Start-Addr_W-WrPageAdr-rStart-Addr_R-Read-Stop.
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#define I2C_MODE_ENHA 0b00001000
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// Transponder is busy.
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#define I2C_MODE_BUSY 0b01000000
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// Transmission interrupted.
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#define I2C_INTERRUPTED 0b10000000
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#define I2C_ERROR 0b00000001
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#define I2C_ERROR_LOW_PRIO 0b00100000
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// Address of the device that is communicated with.
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uint8_t i2c_address;
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// State of TWI component of MCU.
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volatile uint8_t i2c_state = 0;
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/**
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Wether transmission should be terminated on buffer drain. This also means
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no new bytes get stuffed into the buffer until this drain happened. It's
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used to allow distinct transmissions.
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*/
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volatile uint8_t i2c_should_end = 0;
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#ifdef I2C_EEPROM_SUPPORT
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// For SAWSARP mode (see ENHA in i2c.h).
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uint8_t i2c_page_address[I2C_PAGE_ADDRESS_SIZE];
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// Index into the page address buffer.
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uint8_t i2c_page_index;
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// Count of bytes in page address.
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uint8_t i2c_page_count;
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#endif /* I2C_EEPROM_SUPPORT */
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#ifdef I2C_SLAVE_MODE
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uint8_t i2c_in_buffer[I2C_SLAVE_RX_BUFFER_SIZE];
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uint8_t i2c_out_buffer[I2C_SLAVE_TX_BUFFER_SIZE];
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#endif /* I2C_SLAVE_MODE */
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// Ringbuffer logic for buffer 'send'.
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#define BUFSIZE I2C_BUFFER_SIZE
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volatile uint8_t sendhead = 0;
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volatile uint8_t sendtail = 0;
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volatile uint8_t sendbuf[BUFSIZE];
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#include "ringbuffer.h"
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/**
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Inititalise the I2C/TWI subsystem.
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\param address Address the system should listen to in slave mode, unused
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when configured for master mode. In master mode, receiver
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address is given to the send command.
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This also sets the I2C address. In slave mode it's the address we listen on.
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In master mode it's the communication target address. As master one can talk
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to different devices. Call again i2c_init() for changing the target address,
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then. Doing so won't interrupt ongoing transmissions and overhead is small.
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*/
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void i2c_init(uint8_t address) {
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// In case this is a re-inititalisation,
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// don't interrupt an ongoing transmission.
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while (i2c_state & I2C_MODE_BUSY) {
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delay_us(10);
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}
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i2c_address = address;
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#ifdef I2C_MASTER_MODE
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#ifdef I2C_ENABLE_PULLUPS
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SET_INPUT(SCL);
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PULLUP_ON(SCL);
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SET_INPUT(SDA);
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PULLUP_ON(SDA);
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#endif /* I2C_ENABLE_PULLUPS */
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/**
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TWI Bit Rate register
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SCL_freq = CPU_freq / (16 + 2 * TWBR)
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See: page 235 of atmega328 datasheet.
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*/
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TWBR = ((F_CPU / I2C_BITRATE) - 16) / 2;
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/**
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TWI Status Register
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Lower two bits set the prescaler value.
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See: page 236 of atmega328 datasheet.
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*/
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TWSR = 0x00;
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#endif /* I2C_MASTER_MODE */
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#ifdef I2C_SLAVE_MODE
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TWAR = i2c_address; // We listen to broadcasts if lowest bit is set.
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TWCR = (0<<TWINT)|(0<<TWEA)|(0<<TWSTA)|(0<<TWSTO)|(1<<TWEN)|(1<<TWIE);
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#endif
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}
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/**
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Report wether I2C is busy.
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\return Wether I2C is currently busy, which means that eventual new
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transactions would have to wait.
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Idea is that non-crucial display writes check the bus before actually
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writing, so they avoid long waits. If i2c_busy() returns zero, the bus
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is free and writes won't cause a delay.
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*/
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uint8_t i2c_busy(void) {
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return (i2c_state & I2C_MODE_BUSY);
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}
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/**
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Send a byte to the I2C partner.
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\param data The byte to be buffered/sent.
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\param last_byte Wether this is the last byte of a transmission.
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This implementation assumes to talk to mostly one communications client. To
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set the target, or to change it between transmissions, call i2c_init().
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Unlike many other protocols (serial, SPI), I2C has an explicite transmission
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start and transmission end. Invoking code has to tell wether the given byte
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is the last byte of a transmission, so sending code can properly end it.
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This function has been tested to properly distinguish between individual
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transmissions separated by last_byte. Other than setting this flag, invoking
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code doesn't have to care about distinction, but may experience substantial
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delays (up to several milliseconds) if the bus is already busy with a
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distinct previous transmission.
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Data is buffered, so this returns quickly for small amounts of data. Large
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amounts don't get lost, but this function has to wait until sufficient
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previous data was sent.
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To avoid unexpected delays, invoking code can check for bus availability
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with i2c_busy().
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Note that calling code has to send bytes quickly enough to not drain the
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buffer. It looks like the I2C protocol doesn't, unlike e.g. SPI, allow
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to pause sending without dropping the transmission. Positive of this
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limitation is, one can end a transmisson by simply not writing for a while,
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until it's sure the buffer became empty.
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*/
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void i2c_write(uint8_t data, uint8_t last_byte) {
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// Drop characters until transmission end. Transmissions to the display
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// start with a command byte, so sending truncated transmissions is harmful.
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if (i2c_state & I2C_ERROR) {
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if (last_byte) {
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i2c_state &= ~I2C_ERROR;
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}
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return;
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}
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while (i2c_should_end || ! buf_canwrite(send)) {
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delay_us(10);
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}
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if ( ! (i2c_state & I2C_MODE_BUSY)) {
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// No transmission ongoing, start one.
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i2c_state = I2C_MODE_SAWP;
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TWCR = (1<<TWINT)|(0<<TWEA)|(1<<TWSTA)|(0<<TWSTO)|(1<<TWEN)|(1<<TWIE);
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i2c_state |= I2C_MODE_BUSY;
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}
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ATOMIC_START
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buf_push(send, data);
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i2c_should_end = last_byte;
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ATOMIC_END
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}
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/**
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This is the interrupt for all the I2C things.
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A few words about TWCR bits:
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Bit 7 (TWINT) is used to run TWI.
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Bit 6 (TWEA) is used to send ACK (if set) in cases of
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a) device's own slave address has been received;
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b) general call has been received;
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c) a data byte has been received.
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Bit 5 (TWSTA) is 1 if app wants to be a master, don't forget to
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clear this bit.
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Bit 4 (TWSTO) is generated STOP in master mode if set (cleared
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automaticly), recovered from error condition in slave
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mode if set.
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Bit 3 (TWWC) is write collision flag. Sets on try to writeto TWDR when
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TWINT is low.
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Bit 2 (TWEN) activates SDA/SCL pins if set. Set to 0 to disable TWI.
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Bit 1 (Reserved).
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Bit 0 (TWIE) enables TWI interrupt.
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*/
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//#define TWI_INTERRUPT_DEBUG
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#ifdef TWI_INTERRUPT_DEBUG
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#include "serial.h"
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#include "sendf.h"
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#endif
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ISR(TWI_vect) {
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uint8_t status = TWSR & TW_STATUS_MASK;
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#ifdef TWI_INTERRUPT_DEBUG
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serial_writechar('.');
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#endif
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switch (status) {
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case TW_START:
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// Start happens, send a target address.
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#ifdef TWI_INTERRUPT_DEBUG
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serial_writechar('1');
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#endif
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if ((i2c_state & I2C_MODE_MASK) == I2C_MODE_SARP) {
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i2c_address |= 0x01;
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} else {
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i2c_address &= 0xFE;
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}
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TWDR = i2c_address;
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TWCR = (1<<TWINT)|(I2C_MODE<<TWEA)|(0<<TWSTA)|(0<<TWSTO)|(1<<TWEN)|(1<<TWIE);
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break;
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case TW_REP_START:
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// Start happens, send a target address.
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#ifdef TWI_INTERRUPT_DEBUG
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serial_writechar('2');
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#endif
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if ((i2c_state & I2C_MODE_MASK) == I2C_MODE_ENHA) {
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i2c_address |= 0x01;
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} else {
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i2c_address &= 0xFE;
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}
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TWDR = i2c_address;
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TWCR = (1<<TWINT)|(I2C_MODE<<TWEA)|(0<<TWSTA)|(0<<TWSTO)|(1<<TWEN)|(1<<TWIE);
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break;
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case TW_MT_SLA_ACK:
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// SLA+W was sent, then ACK received.
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#ifdef TWI_INTERRUPT_DEBUG
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serial_writechar('3');
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#endif
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if ((i2c_state & I2C_MODE_MASK) == I2C_MODE_SAWP && buf_canread(send)) {
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buf_pop(send, TWDR);
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TWCR = (1<<TWINT)|(I2C_MODE<<TWEA)|(0<<TWSTA)|(0<<TWSTO)|(1<<TWEN)|(1<<TWIE);
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}
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#ifdef I2C_EEPROM_SUPPORT
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if ((i2c_state & I2C_MODE_MASK) == I2C_MODE_ENHA) {
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TWDR = i2c_page_address[i2c_page_index++];
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TWCR = (1<<TWINT)|(I2C_MODE<<TWEA)|(0<<TWSTA)|(0<<TWSTO)|(1<<TWEN)|(1<<TWIE);
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}
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#endif
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break;
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case TW_MT_DATA_ACK:
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// A byte was sent, got ACK.
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#ifdef TWI_INTERRUPT_DEBUG
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serial_writechar('4');
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#endif
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if ((i2c_state & I2C_MODE_MASK) == I2C_MODE_SAWP) {
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if (buf_canread(send)) {
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// Send the next byte.
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buf_pop(send, TWDR);
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TWCR = (1<<TWINT)|(I2C_MODE<<TWEA)|(0<<TWSTA)|(0<<TWSTO)|(1<<TWEN)|(1<<TWIE);
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} else {
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// Buffer drained because transmission is completed.
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i2c_state = 0;
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i2c_should_end = 0;
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// Send stop condition.
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TWCR = (1<<TWINT)|(I2C_MODE<<TWEA)|(0<<TWSTA)|(1<<TWSTO)|(1<<TWEN)|(0<<TWIE);
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}
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}
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#ifdef I2C_EEPROM_SUPPORT
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if ((i2c_state & I2C_MODE_MASK) == I2C_MODE_ENHA) {
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// It was a page address byte.
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if (i2c_page_index == i2c_page_count) {
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// It was the last byte of the page address.
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TWCR = (1<<TWINT)|(I2C_MODE<<TWEA)|(1<<TWSTA)|(0<<TWSTO)|(1<<TWEN)|(1<<TWIE);
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} else {
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// Send the next page address byte.
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TWDR = i2c_page_address[i2c_page_index++];
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TWCR = (1<<TWINT)|(I2C_MODE<<TWEA)|(0<<TWSTA)|(0<<TWSTO)|(1<<TWEN)|(1<<TWIE);
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}
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}
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#endif
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break;
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#ifdef I2C_READ_SUPPORT
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case TW_MR_SLA_ACK:
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// SLA+R was sent, got АСК, then received a byte.
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if (i2c_index + 1 == i2c_byte_count) {
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// Last byte fitting into the buffer. Request a byte, then send NACK
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// to slave and it will release the bus.
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TWCR = (1<<TWINT)|(0<<TWEA)|(0<<TWSTA)|(0<<TWSTO)|(1<<TWEN)|(1<<TWIE);
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} else {
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// Or just receive a byte and sent ACK.
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TWCR = (1<<TWINT)|(1<<TWEA)|(0<<TWSTA)|(0<<TWSTO)|(1<<TWEN)|(1<<TWIE);
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}
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break;
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case TW_MR_SLA_NACK:
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// SLA+R was sent, got NАСК, it seems the slave is busy.
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i2c_state |= I2C_ERROR_NO_ANSWER;
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// Send stop condition.
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TWCR = (1<<TWINT)|(I2C_MODE<<TWEA)|(0<<TWSTA)|(1<<TWSTO)|(1<<TWEN)|(0<<TWIE);
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break;
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case TW_MR_DATA_ACK:
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i2c_buffer[i2c_index++] = TWDR;
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// TODO: Add BUFFER OVERFLOW check.
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if (i2c_index + 1 == i2c_byte_count) {
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// Last byte wait the processing.
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TWCR = (1<<TWINT)|(0<<TWEA)|(0<<TWSTA)|(0<<TWSTO)|(1<<TWEN)|(1<<TWIE);
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} else {
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// Request the next byte.
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TWCR = (1<<TWINT)|(0<<TWEA)|(0<<TWSTA)|(0<<TWSTO)|(1<<TWEN)|(1<<TWIE);
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}
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break;
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case TW_MR_DATA_NACK:
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// Last byte received, send NACK to make the slave to release the bus.
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i2c_buffer[i2c_index] = TWDR;
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// Send stop condition.
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TWCR = (1<<TWINT)|(I2C_MODE<<TWEA)|(0<<TWSTA)|(1<<TWSTO)|(1<<TWEN)|(0<<TWIE);
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break;
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#endif /* I2C_READ_SUPPORT */
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#ifdef I2C_SLAVE_MODE
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case TW_SR_ARB_LOST_SLA_ACK:
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case TW_SR_ARB_LOST_GCALL_ACK:
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// Another master on the bus sent some bytes, receive them.
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i2c_state |= I2C_ERROR_LOW_PRIO;
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// Restore the transfer.
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i2c_index = 0;
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#ifdef I2C_EEPROM_SUPPORT
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i2c_page_index = 0;
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#endif
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case TW_SR_SLA_ACK:
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case TW_SR_GCALL_ACK:
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i2c_state |= I2C_MODE_BUSY; // Lock bus.
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i2c_index = 0;
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if (I2C_SLAVE_RX_BUFFER_SIZE == 1) {
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// We should take alone byte and send NACK.
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TWCR = (1<<TWINT)|(0<TWEA)|(0<<TWSTA)|(0<<TWSTO)|(1<<TWEN)|(1<<TWIE);
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} else {
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// Get a byte and send ACK.
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TWCR = (1<<TWINT)|(1<TWEA)|(0<<TWSTA)|(0<<TWSTO)|(1<<TWEN)|(1<<TWIE);
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}
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break;
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case TW_SR_DATA_ACK:
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case TW_SR_GCALL_DATA_ACK:
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i2c_in_buffer[i2c_index++] = TWDR;
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if (i2c_index == I2C_SLAVE_RX_BUFFER_SIZE - 1) {
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// Room for only one byte left, send NACK.
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TWCR = (1<<TWINT)|(0<TWEA)|(0<<TWSTA)|(0<<TWSTO)|(1<<TWEN)|(1<<TWIE);
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} else {
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// We have room for more bytes, send ACK.
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TWCR = (1<<TWINT)|(1<TWEA)|(0<<TWSTA)|(0<<TWSTO)|(1<<TWEN)|(1<<TWIE);
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}
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break;
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case TW_SR_DATA_NACK:
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case TW_SR_GCALL_DATA_NACK:
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i2c_in_buffer[i2c_index] = TWDR;
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// Send stop condition.
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TWCR = (1<<TWINT)|(I2C_MODE<<TWEA)|(0<<TWSTA)|(1<<TWSTO)|(1<<TWEN)|(0<<TWIE);
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break;
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case TW_SR_STOP:
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// We got a Restart. What we will do?
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// Here we can do additional logic but we don't need it at this time.
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// Just ignore it now.
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TWCR = (1<<TWINT)|(1<TWEA)|(0<<TWSTA)|(0<<TWSTO)|(1<<TWEN)|(1<<TWIE);
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break;
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case TW_ST_ARB_LOST_SLA_ACK:
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// Got own address on read from another master.
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i2c_state |= I2C_ERROR_LOW_PRIO | I2C_INTERRUPTED;
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// Reinit.
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i2c_index = 0;
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#ifdef I2C_EEPROM_SUPPORT
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i2c_page_index = 0;
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#endif
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case TW_ST_SLA_ACK:
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// We have got own address on read.
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i2c_index = 0;
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TWDR = i2c_out_buffer[i2c_index];
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if (I2C_SLAVE_TX_BUFFER_SIZE == 1) {
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// If it is last byte, we hope to receive NACK.
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TWCR = (1<<TWINT)|(0<TWEA)|(0<<TWSTA)|(0<<TWSTO)|(1<<TWEN)|(1<<TWIE);
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} else {
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// Wait for ACK.
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TWCR = (1<<TWINT)|(1<TWEA)|(0<<TWSTA)|(0<<TWSTO)|(1<<TWEN)|(1<<TWIE);
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}
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break;
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case TW_ST_DATA_ACK:
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// Send byte and got ACK, then send next byte to master.
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TWDR = i2c_out_buffer[++i2c_index];
|
||
if (I2C_SLAVE_TX_BUFFER_SIZE - 1 == i2c_index) {
|
||
// It was last byte, send it and wait for NACK.
|
||
TWCR = (1<<TWINT)|(0<TWEA)|(0<<TWSTA)|(0<<TWSTO)|(1<<TWEN)|(1<<TWIE);
|
||
} else {
|
||
// Send byte and wait for ACK.
|
||
TWCR = (1<<TWINT)|(1<TWEA)|(0<<TWSTA)|(0<<TWSTO)|(0<<TWEN)|(1<<TWIE);
|
||
}
|
||
break;
|
||
case TW_ST_DATA_NACK:
|
||
// We sent the last byte and received NACK or ACK (doesn't matter here).
|
||
if (i2c_state & I2C_INTERRUPTED) {
|
||
// There was interrupted master transfer.
|
||
i2c_state &= ~I2C_INTERRUPTED;
|
||
// Generate start as the bus became free.
|
||
TWCR = (1<<TWINT)|(1<TWEA)|(1<<TWSTA)|(0<<TWSTO)|(1<<TWEN)|(1<<TWIE);
|
||
} else {
|
||
// Send stop condition.
|
||
TWCR = (1<<TWINT)|(I2C_MODE<<TWEA)|(0<<TWSTA)|(1<<TWSTO)|(1<<TWEN)|(0<<TWIE);
|
||
}
|
||
break;
|
||
|
||
#endif /* I2C_SLAVE_MODE */
|
||
|
||
case TW_BUS_ERROR:
|
||
// A hardware error was detected.
|
||
#ifdef TWI_INTERRUPT_DEBUG
|
||
serial_writechar('5');
|
||
#endif
|
||
case TW_MT_SLA_NACK:
|
||
// SLA+W was sent, got NACK, so slave is busy or out of bus.
|
||
#ifdef TWI_INTERRUPT_DEBUG
|
||
serial_writechar('6');
|
||
#endif
|
||
case TW_MT_DATA_NACK:
|
||
// Byte was sent but got NACK, there are two possible reasons:
|
||
// - a slave stops transmission and it is ok, or
|
||
// - a slave became crazy.
|
||
#ifdef TWI_INTERRUPT_DEBUG
|
||
serial_writechar('7');
|
||
#endif
|
||
case TW_MT_ARB_LOST:
|
||
// Collision, identical to TW_MR_ARB_LOST.
|
||
// It looks like there is another master on the bus. Handle this like
|
||
// the other error conditions, because an eventual resend is handled in
|
||
// upper layers (display code).
|
||
#ifdef TWI_INTERRUPT_DEBUG
|
||
serial_writechar('8');
|
||
#endif
|
||
|
||
i2c_state |= I2C_ERROR | I2C_INTERRUPTED;
|
||
// Let i2c_write() continue.
|
||
i2c_should_end = 0;
|
||
// Drain the buffer.
|
||
while (buf_canread(send)) {
|
||
buf_pop(send, TWDR);
|
||
}
|
||
// Send stop condition.
|
||
TWCR = (1<<TWINT)|(I2C_MODE<<TWEA)|(0<<TWSTA)|(1<<TWSTO)|(1<<TWEN)|(0<<TWIE);
|
||
break;
|
||
|
||
default:
|
||
#ifdef TWI_INTERRUPT_DEBUG
|
||
sendf_P(serial_writechar, PSTR("(%sx)"), status);
|
||
#endif
|
||
break;
|
||
}
|
||
}
|
||
|
||
#endif /* I2C */
|