349 lines
14 KiB
C
349 lines
14 KiB
C
/**
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******************************************************************************
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* @file system_stm32f4xx.c
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* @author MCD Application Team
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* @version V2.1.0
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* @date 19-June-2014
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* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
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*
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* This file provides two functions and one global variable to be called from
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* user application:
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* - SystemInit(): This function is called at startup just after reset and
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* before branch to main program. This call is made inside
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* the "startup_stm32f4xx.s" file.
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*
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* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
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* by the user application to setup the SysTick
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* timer or configure other parameters.
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*
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* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
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* be called whenever the core clock is changed
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* during program execution.
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*
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* This file configures the system clock as follows:
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*-----------------------------------------------------------------------------
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* System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
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* | (external 8 MHz clock) | (internal 16 MHz)
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* | 2- PLL_HSE_XTAL |
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* | (external 8 MHz xtal) |
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*-----------------------------------------------------------------------------
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* SYSCLK(MHz) | 96 | 96
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*-----------------------------------------------------------------------------
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* AHBCLK (MHz) | 96 | 96
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*-----------------------------------------------------------------------------
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* APB1CLK (MHz) | 48 | 48
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*-----------------------------------------------------------------------------
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* APB2CLK (MHz) | 96 | 96
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*-----------------------------------------------------------------------------
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* USB capable (48 MHz precise clock) | YES | YES
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*-----------------------------------------------------------------------------
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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/*
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Notes for Teacup:
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Copied from $(MBED)/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/system_stm32f4xx.c.
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- Prefixed names of #include files with mbed- to match the names of the
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copies in the Teacup repo.
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- Wrapped the whole file in #ifdef __ARM_STM32F411__ to not cause conflicts with
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AVR builds.
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- Rebuild SystemInit() and SetSysClock() to get rid of most mbed-files. Please take a look into history.
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- Rework SetSysClock completely
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*/
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#ifdef __ARM_STM32F411__
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#include "cmsis-stm32f4xx.h"
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#include "arduino_stm32f411.h"
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#if !defined (HSE_VALUE)
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#define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz */
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#endif /* HSE_VALUE */
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#if !defined (HSI_VALUE)
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#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
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#endif /* HSI_VALUE */
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/*!< Uncomment the following line if you need to relocate your vector Table in
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Internal SRAM. */
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/* #define VECT_TAB_SRAM */
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#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
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This value must be a multiple of 0x200. */
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/******************************************************************************/
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/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
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#define USE_PLL_HSE_EXTC (1) /* Use external clock */
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#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
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/** @addtogroup STM32F4xx_System_Private_Variables
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* @{
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*/
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/* This variable is updated in three ways:
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1) by calling CMSIS function SystemCoreClockUpdate()
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2) by calling HAL API function HAL_RCC_GetHCLKFreq()
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3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
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Note: If you use this function to configure the system clock; then there
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is no need to call the 2 first functions listed above, since SystemCoreClock
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variable is updated automatically.
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*/
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uint32_t SystemCoreClock = 16000000;
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const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
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/**
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* @brief Setup the microcontroller system
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* Initialize the FPU setting, vector table location and External memory
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* configuration.
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* @param None
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* @retval None
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*/
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void SystemInit(void)
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{
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/* FPU settings ------------------------------------------------------------*/
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#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
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SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
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#endif
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/* Reset the RCC clock configuration to the default reset state ------------*/
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/* Set HSION bit */
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RCC->CR |= RCC_CR_HSION;
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/* Reset CFGR register */
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RCC->CFGR = 0x00000000;
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/* Reset HSEON, CSSON and PLLON bits */
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RCC->CR &= ~(RCC_CR_HSEON |
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RCC_CR_CSSON |
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RCC_CR_PLLON);
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/* Reset PLLCFGR register */
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RCC->PLLCFGR = 0x24003010;
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/* Reset HSEBYP bit */
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RCC->CR &= ~(RCC_CR_HSEBYP);
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/* Disable all interrupts */
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RCC->CIR = 0x00000000;
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SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
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/* Configure the System clock source, PLL Multiplier and Divider factors,
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AHB/APBx prescalers and Flash settings */
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SetSysClock();
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}
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/**
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* @brief Update SystemCoreClock variable according to Clock Register Values.
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* The SystemCoreClock variable contains the core clock (HCLK), it can
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* be used by the user application to setup the SysTick timer or configure
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* other parameters.
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*
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* @note Each time the core clock (HCLK) changes, this function must be called
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* to update SystemCoreClock variable value. Otherwise, any configuration
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* based on this variable will be incorrect.
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*
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* @note - The system frequency computed by this function is not the real
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* frequency in the chip. It is calculated based on the predefined
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* constant and the selected clock source:
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*
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* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
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*
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* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
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*
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* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
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* or HSI_VALUE(*) multiplied/divided by the PLL factors.
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*
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* (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
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* 16 MHz) but the real value may vary depending on the variations
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* in voltage and temperature.
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*
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* (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value
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* depends on the application requirements), user has to ensure that HSE_VALUE
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* is same as the real frequency of the crystal used. Otherwise, this function
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* may have wrong result.
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*
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* - The result of this function could be not correct when using fractional
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* value for HSE crystal.
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*
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* @param None
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* @retval None
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*/
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void SystemCoreClockUpdate(void)
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{
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uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
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/* Get SYSCLK source -------------------------------------------------------*/
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tmp = RCC->CFGR & RCC_CFGR_SWS;
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switch (tmp)
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{
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case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
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SystemCoreClock = HSI_VALUE;
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break;
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case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
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SystemCoreClock = HSE_VALUE;
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break;
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case RCC_CFGR_SWS_PLL: /* PLL used as system clock source */
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/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
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SYSCLK = PLL_VCO / PLL_P
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*/
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pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
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pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
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if (pllsource != 0)
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{
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/* HSE used as PLL clock source */
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pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
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}
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else
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{
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/* HSI used as PLL clock source */
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pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
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}
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pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
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SystemCoreClock = pllvco/pllp;
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break;
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default:
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SystemCoreClock = HSI_VALUE;
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break;
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}
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/* Compute HCLK frequency --------------------------------------------------*/
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/* Get HCLK prescaler */
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tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
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/* HCLK frequency */
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SystemCoreClock >>= tmp;
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}
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/**
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* @brief Configures the System clock source, PLL Multiplier and Divider factors,
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* AHB/APBx prescalers and Flash settings
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* @note This function should be called only once the RCC clock configuration
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* is reset to the default reset state (done in SystemInit() function).
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* @param None
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* @retval None
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*/
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void SetSysClock(void)
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{
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/* The voltage scaling allows optimizing the power consumption when the device is
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clocked below the maximum system frequency, to update the voltage scaling value
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regarding system frequency refer to product datasheet. */
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RCC->APB1ENR |= RCC_APB1ENR_PWREN;
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PWR->CR |= PWR_CR_VOS;
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/* Enable HSE oscillator and activate PLL with HSE as source */
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/*------------------------------- HSE Configuration ------------------------*/
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/* Reset HSEON and HSEBYP bits before configuring the HSE --------------*/
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RCC->CR &= ~(RCC_CR_HSEON);
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while(RCC->CR & RCC_CR_HSERDY);
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/* Set the new HSE configuration ---------------------------------------*/
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RCC->CR |= RCC_CR_HSEON;
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while(!(RCC->CR & RCC_CR_HSERDY));
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/*-------------------------------- PLL Configuration -----------------------*/
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/* Disable the main PLL. */
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RCC->CR &= ~(RCC_CR_PLLON);
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while(RCC->CR & RCC_CR_PLLRDY);
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/* Configure the main PLL clock source, multiplication and division factors. */
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// PLLM: VCO input clock = 2 MHz (8 MHz / 4)
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// PLLN: VCO output clock = 384 MHz (2 MHz * 192)
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// PLLP: PLLCLK = 96 MHz (384 MHz / 4)
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// PLLQ: USB clock = 48 MHz (384 MHz / 8) --> 48MHz is best choice for USB
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#if __SYSTEM_CLOCK == 96000000
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#define PLLM 4
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#define PLLN 192
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#define PLLP 4
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#define PLLQ 8
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#elif __SYSTEM_CLOCK == 100000000
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#define PLLM 4
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#define PLLN 200
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#define PLLP 4
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#define PLLQ 8
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#elif __SYSTEM_CLOCK == 108000000
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#warning You are running the controller out of specification!
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#define PLLM 4
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#define PLLN 216
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#define PLLP 4
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#define PLLQ 9
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#elif __SYSTEM_CLOCK == 125000000
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#warning You are running the controller out of specification!
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#define PLLM 4
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#define PLLN 250
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#define PLLP 4
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#define PLLQ 10
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#endif
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RCC->PLLCFGR = RCC_PLLCFGR_PLLSRC_HSE |
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((PLLM << 0) & RCC_PLLCFGR_PLLM) |
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((PLLN << 6) & RCC_PLLCFGR_PLLN) |
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(((PLLP/2 - 1) << 16) & RCC_PLLCFGR_PLLP) |
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((PLLQ << 24) & RCC_PLLCFGR_PLLQ);
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/* Enable the main PLL. */
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RCC->CR |= RCC_CR_PLLON;
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while(!(RCC->CR & RCC_CR_PLLRDY));
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/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
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must be correctly programmed according to the frequency of the CPU clock
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(HCLK) and the supply voltage of the device. */
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/* Increasing the CPU frequency */
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if(FLASH_ACR_LATENCY_3WS > (FLASH->ACR & FLASH_ACR_LATENCY))
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{
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/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
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FLASH->ACR &= ~(FLASH_ACR_LATENCY);
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FLASH->ACR |= FLASH_ACR_LATENCY_3WS;
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RCC->CFGR &= ~(RCC_CFGR_HPRE | RCC_CFGR_SW);
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RCC->CFGR |= RCC_CFGR_HPRE_DIV1 | RCC_CFGR_SW_PLL;
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}
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/* Decreasing the CPU frequency */
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else
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{
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RCC->CFGR &= ~(RCC_CFGR_HPRE | RCC_CFGR_SW);
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RCC->CFGR |= RCC_CFGR_HPRE_DIV1 | RCC_CFGR_SW_PLL;
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/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
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FLASH->ACR &= ~(FLASH_ACR_LATENCY);
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FLASH->ACR |= FLASH_ACR_LATENCY_3WS;
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}
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RCC->CFGR &= ~(RCC_CFGR_PPRE1 | RCC_CFGR_PPRE2);
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RCC->CFGR |= PPRE1_DIV | PPRE2_DIV;
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}
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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#endif
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