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According to avr-libc documentation, ISR() handles SREG its self.

This commit is contained in:
Markus Hitter 2013-10-20 22:20:33 +02:00
parent 3343cfc753
commit 0c100fe5f8
5 changed files with 0 additions and 63 deletions
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7
analog.c
View File

@ -77,9 +77,6 @@ void analog_init() {
This is where we read our analog value and store it in an array for later retrieval This is where we read our analog value and store it in an array for later retrieval
*/ */
ISR(ADC_vect, ISR_NOBLOCK) { ISR(ADC_vect, ISR_NOBLOCK) {
// save status register
uint8_t sreg_save = SREG;
// emulate free-running mode but be more deterministic about exactly which result we have, since this project has long-running interrupts // emulate free-running mode but be more deterministic about exactly which result we have, since this project has long-running interrupts
if (analog_mask > 0) { // at least one temp sensor uses an analog channel if (analog_mask > 0) { // at least one temp sensor uses an analog channel
// store next result // store next result
@ -104,10 +101,6 @@ ISR(ADC_vect, ISR_NOBLOCK) {
// After the mux has been set, start a new conversion // After the mux has been set, start a new conversion
ADCSRA |= MASK(ADSC); ADCSRA |= MASK(ADSC);
} }
// restore status register
MEMORY_BARRIER();
SREG = sreg_save;
} }
/*! Read analog value from saved result array /*! Read analog value from saved result array

21
intercom.c
View File

@ -140,9 +140,6 @@ ISR(USART1_RX_vect)
ISR(USART_RX_vect) ISR(USART_RX_vect)
#endif #endif
{ {
// save status register
uint8_t sreg_save = SREG;
// pull character // pull character
static uint8_t c; static uint8_t c;
@ -200,10 +197,6 @@ ISR(USART_RX_vect)
#endif #endif
} }
} }
// restore status register
MEMORY_BARRIER();
SREG = sreg_save;
} }
// finished transmitting interrupt- only enabled at end of packet // finished transmitting interrupt- only enabled at end of packet
@ -213,9 +206,6 @@ ISR(USART1_TX_vect)
ISR(USART_TX_vect) ISR(USART_TX_vect)
#endif #endif
{ {
// save status register
uint8_t sreg_save = SREG;
if (packet_pointer >= sizeof(intercom_packet_t)) { if (packet_pointer >= sizeof(intercom_packet_t)) {
disable_transmit(); disable_transmit();
packet_pointer = 0; packet_pointer = 0;
@ -226,10 +216,6 @@ ISR(USART_TX_vect)
UCSR0B &= ~MASK(TXCIE0); UCSR0B &= ~MASK(TXCIE0);
#endif #endif
} }
// restore status register
MEMORY_BARRIER();
SREG = sreg_save;
} }
// tx queue empty interrupt- send next byte // tx queue empty interrupt- send next byte
@ -239,9 +225,6 @@ ISR(USART1_UDRE_vect)
ISR(USART_UDRE_vect) ISR(USART_UDRE_vect)
#endif #endif
{ {
// save status register
uint8_t sreg_save = SREG;
#ifdef MOTHERBOARD #ifdef MOTHERBOARD
UDR1 = _tx.data[packet_pointer++]; UDR1 = _tx.data[packet_pointer++];
#else #else
@ -257,10 +240,6 @@ ISR(USART_UDRE_vect)
UCSR0B |= MASK(TXCIE0); UCSR0B |= MASK(TXCIE0);
#endif #endif
} }
// restore status register
MEMORY_BARRIER();
SREG = sreg_save;
} }
#endif /* TEMP_INTERCOM */ #endif /* TEMP_INTERCOM */

14
serial.c
View File

@ -113,9 +113,6 @@ ISR(USART_RX_vect)
ISR(USART0_RX_vect) ISR(USART0_RX_vect)
#endif #endif
{ {
// save status register
uint8_t sreg_save = SREG;
if (buf_canwrite(rx)) if (buf_canwrite(rx))
buf_push(rx, UDR0); buf_push(rx, UDR0);
else { else {
@ -137,10 +134,6 @@ ISR(USART0_RX_vect)
UCSR0B |= MASK(UDRIE0); UCSR0B |= MASK(UDRIE0);
} }
#endif #endif
// restore status register
MEMORY_BARRIER();
SREG = sreg_save;
} }
#pragma GCC diagnostic pop #pragma GCC diagnostic pop
@ -153,9 +146,6 @@ ISR(USART_UDRE_vect)
ISR(USART0_UDRE_vect) ISR(USART0_UDRE_vect)
#endif #endif
{ {
// save status register
uint8_t sreg_save = SREG;
#ifdef XONXOFF #ifdef XONXOFF
if (flowflags & FLOWFLAG_SEND_XON) { if (flowflags & FLOWFLAG_SEND_XON) {
UDR0 = ASCII_XON; UDR0 = ASCII_XON;
@ -171,10 +161,6 @@ ISR(USART0_UDRE_vect)
buf_pop(tx, UDR0); buf_pop(tx, UDR0);
else else
UCSR0B &= ~MASK(UDRIE0); UCSR0B &= ~MASK(UDRIE0);
// restore status register
MEMORY_BARRIER();
SREG = sreg_save;
} }
/* /*

14
timer.c
View File

@ -42,9 +42,6 @@ volatile uint8_t clock_flag_1s = 0;
/// comparator B is the system clock, happens every TICK_TIME /// comparator B is the system clock, happens every TICK_TIME
ISR(TIMER1_COMPB_vect) { ISR(TIMER1_COMPB_vect) {
// save status register
uint8_t sreg_save = SREG;
// set output compare register to the next clock tick // set output compare register to the next clock tick
OCR1B = (OCR1B + TICK_TIME) & 0xFFFF; OCR1B = (OCR1B + TICK_TIME) & 0xFFFF;
@ -70,19 +67,12 @@ ISR(TIMER1_COMPB_vect) {
} }
dda_clock(); dda_clock();
// restore status register
MEMORY_BARRIER();
SREG = sreg_save;
} }
#ifdef MOTHERBOARD #ifdef MOTHERBOARD
/// comparator A is the step timer. It has higher priority then B. /// comparator A is the step timer. It has higher priority then B.
ISR(TIMER1_COMPA_vect) { ISR(TIMER1_COMPA_vect) {
// save status register
uint8_t sreg_save = SREG;
// Check if this is a real step, or just a next_step_time "overflow" // Check if this is a real step, or just a next_step_time "overflow"
if (next_step_time < 65536) { if (next_step_time < 65536) {
// step! // step!
@ -114,10 +104,6 @@ ISR(TIMER1_COMPA_vect) {
next_step_time += 10000; next_step_time += 10000;
} }
// leave OCR1A as it was // leave OCR1A as it was
// restore status register
MEMORY_BARRIER();
SREG = sreg_save;
} }
#endif /* ifdef MOTHERBOARD */ #endif /* ifdef MOTHERBOARD */

7
watchdog.c
View File

@ -32,17 +32,10 @@ volatile uint8_t wd_flag = 0;
// } // }
ISR(WDT_vect) { ISR(WDT_vect) {
// save status register
uint8_t sreg_save = SREG;
// watchdog has tripped- no main loop activity for 0.5s, probably a bad thing // watchdog has tripped- no main loop activity for 0.5s, probably a bad thing
// if watchdog fires again, we will reset // if watchdog fires again, we will reset
// perhaps we should do something more intelligent in this interrupt? // perhaps we should do something more intelligent in this interrupt?
wd_flag |= 1; wd_flag |= 1;
// restore status register
MEMORY_BARRIER();
SREG = sreg_save;
} }
/// intialise watchdog /// intialise watchdog