According to avr-libc documentation, ISR() handles SREG its self.
This commit is contained in:
Markus Hitter
parent
3343cfc753
commit
0c100fe5f8
7
analog.c
7
analog.c
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@ -77,9 +77,6 @@ void analog_init() {
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This is where we read our analog value and store it in an array for later retrieval
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*/
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ISR(ADC_vect, ISR_NOBLOCK) {
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// save status register
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uint8_t sreg_save = SREG;
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// emulate free-running mode but be more deterministic about exactly which result we have, since this project has long-running interrupts
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if (analog_mask > 0) { // at least one temp sensor uses an analog channel
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// store next result
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@ -104,10 +101,6 @@ ISR(ADC_vect, ISR_NOBLOCK) {
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// After the mux has been set, start a new conversion
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ADCSRA |= MASK(ADSC);
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}
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// restore status register
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MEMORY_BARRIER();
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SREG = sreg_save;
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}
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/*! Read analog value from saved result array
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21
intercom.c
21
intercom.c
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@ -140,9 +140,6 @@ ISR(USART1_RX_vect)
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ISR(USART_RX_vect)
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#endif
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{
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// save status register
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uint8_t sreg_save = SREG;
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// pull character
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static uint8_t c;
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@ -200,10 +197,6 @@ ISR(USART_RX_vect)
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#endif
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}
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}
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// restore status register
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MEMORY_BARRIER();
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SREG = sreg_save;
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}
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// finished transmitting interrupt- only enabled at end of packet
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@ -213,9 +206,6 @@ ISR(USART1_TX_vect)
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ISR(USART_TX_vect)
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#endif
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{
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// save status register
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uint8_t sreg_save = SREG;
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if (packet_pointer >= sizeof(intercom_packet_t)) {
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disable_transmit();
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packet_pointer = 0;
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@ -226,10 +216,6 @@ ISR(USART_TX_vect)
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UCSR0B &= ~MASK(TXCIE0);
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#endif
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}
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// restore status register
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MEMORY_BARRIER();
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SREG = sreg_save;
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}
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// tx queue empty interrupt- send next byte
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@ -239,9 +225,6 @@ ISR(USART1_UDRE_vect)
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ISR(USART_UDRE_vect)
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#endif
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{
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// save status register
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uint8_t sreg_save = SREG;
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#ifdef MOTHERBOARD
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UDR1 = _tx.data[packet_pointer++];
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#else
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@ -257,10 +240,6 @@ ISR(USART_UDRE_vect)
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UCSR0B |= MASK(TXCIE0);
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#endif
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}
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// restore status register
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MEMORY_BARRIER();
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SREG = sreg_save;
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}
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#endif /* TEMP_INTERCOM */
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14
serial.c
14
serial.c
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@ -113,9 +113,6 @@ ISR(USART_RX_vect)
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ISR(USART0_RX_vect)
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#endif
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{
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// save status register
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uint8_t sreg_save = SREG;
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if (buf_canwrite(rx))
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buf_push(rx, UDR0);
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else {
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@ -137,10 +134,6 @@ ISR(USART0_RX_vect)
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UCSR0B |= MASK(UDRIE0);
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}
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#endif
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// restore status register
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MEMORY_BARRIER();
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SREG = sreg_save;
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}
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#pragma GCC diagnostic pop
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@ -153,9 +146,6 @@ ISR(USART_UDRE_vect)
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ISR(USART0_UDRE_vect)
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#endif
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{
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// save status register
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uint8_t sreg_save = SREG;
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#ifdef XONXOFF
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if (flowflags & FLOWFLAG_SEND_XON) {
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UDR0 = ASCII_XON;
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@ -171,10 +161,6 @@ ISR(USART0_UDRE_vect)
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buf_pop(tx, UDR0);
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else
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UCSR0B &= ~MASK(UDRIE0);
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// restore status register
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MEMORY_BARRIER();
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SREG = sreg_save;
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}
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/*
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14
timer.c
14
timer.c
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@ -42,9 +42,6 @@ volatile uint8_t clock_flag_1s = 0;
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/// comparator B is the system clock, happens every TICK_TIME
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ISR(TIMER1_COMPB_vect) {
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// save status register
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uint8_t sreg_save = SREG;
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// set output compare register to the next clock tick
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OCR1B = (OCR1B + TICK_TIME) & 0xFFFF;
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@ -70,19 +67,12 @@ ISR(TIMER1_COMPB_vect) {
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}
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dda_clock();
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// restore status register
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MEMORY_BARRIER();
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SREG = sreg_save;
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}
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#ifdef MOTHERBOARD
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/// comparator A is the step timer. It has higher priority then B.
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ISR(TIMER1_COMPA_vect) {
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// save status register
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uint8_t sreg_save = SREG;
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// Check if this is a real step, or just a next_step_time "overflow"
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if (next_step_time < 65536) {
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// step!
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@ -114,10 +104,6 @@ ISR(TIMER1_COMPA_vect) {
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next_step_time += 10000;
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}
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// leave OCR1A as it was
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// restore status register
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MEMORY_BARRIER();
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SREG = sreg_save;
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}
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#endif /* ifdef MOTHERBOARD */
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@ -32,17 +32,10 @@ volatile uint8_t wd_flag = 0;
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// }
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ISR(WDT_vect) {
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// save status register
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uint8_t sreg_save = SREG;
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// watchdog has tripped- no main loop activity for 0.5s, probably a bad thing
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// if watchdog fires again, we will reset
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// perhaps we should do something more intelligent in this interrupt?
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wd_flag |= 1;
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// restore status register
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MEMORY_BARRIER();
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SREG = sreg_save;
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}
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/// intialise watchdog
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