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STM32F411: easy change system clocks 

- 96MHz
- 100MHz
- 108MHz

100MHz is standard now. 108MHz was possible on a first test, but is not recommended for real systems!
This commit is contained in:
Nico Tonnhofer 2016-09-17 22:36:39 +02:00
parent dc9e016e2c
commit 0cfc503c4a
2 changed files with 15 additions and 1 deletions
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12
cmsis-system_stm32f4xx.c
View File

@ -342,10 +342,22 @@ void SetSysClock(void)
// PLLN_6/7: VCO output clock = 384 MHz (2 MHz * 192)
// PLLP_0: PLLCLK = 96 MHz (384 MHz / 4)
// PLLQ_3: USB clock = 48 MHz (384 MHz / 8) --> 48MHz is best choice for USB
#if __SYSTEM_CLOCK == 96000000
RCC->PLLCFGR = RCC_PLLCFGR_PLLSRC_HSE | RCC_PLLCFGR_PLLM_2 | \
RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | \
RCC_PLLCFGR_PLLP_0 | \
RCC_PLLCFGR_PLLQ_3;
#elif __SYSTEM_CLOCK == 100000000
RCC->PLLCFGR = RCC_PLLCFGR_PLLSRC_HSE | RCC_PLLCFGR_PLLM_2 | \
RCC_PLLCFGR_PLLN_3 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | \
RCC_PLLCFGR_PLLP_0 | \
RCC_PLLCFGR_PLLQ_3;
#elif __SYSTEM_CLOCK == 108000000
RCC->PLLCFGR = RCC_PLLCFGR_PLLSRC_HSE | RCC_PLLCFGR_PLLM_2 | \
RCC_PLLCFGR_PLLN_3 | RCC_PLLCFGR_PLLN_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | \
RCC_PLLCFGR_PLLP_0 | \
RCC_PLLCFGR_PLLQ_0 | RCC_PLLCFGR_PLLQ_3;
#endif
/* Enable the main PLL. */
RCC->CR |= RCC_CR_PLLON;

4
cmsis-system_stm32f4xx.h
View File

@ -62,7 +62,9 @@
extern "C" {
#endif
#define __SYSTEM_CLOCK 96000000
// #define __SYSTEM_CLOCK 96000000
#define __SYSTEM_CLOCK 100000000
// #define __SYSTEM_CLOCK 108000000 // Overclocking is not recommended!
/** @addtogroup STM32F4xx_System_Includes
* @{
*/