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STM32F411: simplify cmsis files for stm32f411 

Delete some macros from cmsis-file we will never use again.
Also replace magic numbers.
Add missing flag to allow -O0 (using R7 as register)
This commit is contained in:
Nico Tonnhofer 2017-02-05 15:01:11 +01:00
parent dea9cec217
commit 230572b1d0
5 changed files with 2826 additions and 3285 deletions
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1
Makefile-ARM
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@ -139,6 +139,7 @@ else ifeq ($(MCU), stm32f411)
CFLAGS += -mfloat-abi=hard CFLAGS += -mfloat-abi=hard
CFLAGS += -mlittle-endian CFLAGS += -mlittle-endian
CFLAGS += -D__FPU_PRESENT=1 CFLAGS += -D__FPU_PRESENT=1
CFLAGS += -fomit-frame-pointer
endif endif
# Other options ... # Other options ...
CFLAGS += -Wall CFLAGS += -Wall

24
arduino_stm32f411.h
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@ -20,18 +20,36 @@
#include "cmsis-stm32f4xx.h" #include "cmsis-stm32f4xx.h"
#define F_CPU __SYSTEM_CLOCK
/** Pins for UART, the serial port. /** Pins for UART, the serial port.
*/ */
#define RXD PA_3 #define RXD PA_3
#define TXD PA_2 #define TXD PA_2
/** Clock setup for APB1 and APB2 clock.
*/
#define F_CPU __SYSTEM_CLOCK
#define PPRE1_DIV (RCC_CFGR_PPRE1_DIV2) // 0x1000
#define PPRE2_DIV (RCC_CFGR_PPRE2_DIV1) // 0x0000
#if PPRE1_DIV > 0
#define APB1_DIV (1 << ((PPRE1_DIV >> 10) - 3))
#else
#define APB1_DIV (1)
#endif
#if PPRE2_DIV > 0
#define APB2_DIV (1 << ((PPRE2_DIV >> 13) - 3))
#else
#define APB2_DIV (1)
#endif
#define _APB1_CLOCK (__SYSTEM_CLOCK/APB1_DIV)
#define _APB2_CLOCK (__SYSTEM_CLOCK/APB2_DIV)
/** /**
We define only pins available on the Nucleo F411RE here. We define only pins available on the Nucleo F411RE here.
Use alphas for PORT and numerics for PIN, close to the design. Use alphas for PORT and numerics for PIN, close to the design.
*/ */
#define NO_TIMER ((TIM_TypeDef *) 0) #define NO_TIMER ((TIM_TypeDef *) 0)
#define PA_0_PIN 0 #define PA_0_PIN 0

5851
cmsis-stm32f4xx.h
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File diff suppressed because it is too large Load Diff

167
cmsis-system_stm32f4xx.c
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@ -76,22 +76,13 @@
- Wrapped the whole file in #ifdef __ARM_STM32F411__ to not cause conflicts with - Wrapped the whole file in #ifdef __ARM_STM32F411__ to not cause conflicts with
AVR builds. AVR builds.
- Rebuild SystemInit() and SetSysClock() to get rid of most mbed-files. Please take a look into history. - Rebuild SystemInit() and SetSysClock() to get rid of most mbed-files. Please take a look into history.
- Rework SetSysClock completely
*/ */
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32f4xx_system
* @{
*/
/** @addtogroup STM32F4xx_System_Private_Includes
* @{
*/
#ifdef __ARM_STM32F411__ #ifdef __ARM_STM32F411__
#include "cmsis-stm32f4xx.h" #include "cmsis-stm32f4xx.h"
#include "arduino_stm32f411.h"
#if !defined (HSE_VALUE) #if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz */ #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz */
@ -101,22 +92,6 @@
#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */ #endif /* HSI_VALUE */
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Private_Defines
* @{
*/
/*!< Uncomment the following line if you need to relocate your vector Table in /*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */ Internal SRAM. */
/* #define VECT_TAB_SRAM */ /* #define VECT_TAB_SRAM */
@ -124,22 +99,10 @@
This value must be a multiple of 0x200. */ This value must be a multiple of 0x200. */
/******************************************************************************/ /******************************************************************************/
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Private_Macros
* @{
*/
/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */ /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
#define USE_PLL_HSE_EXTC (1) /* Use external clock */ #define USE_PLL_HSE_EXTC (1) /* Use external clock */
#define USE_PLL_HSE_XTAL (1) /* Use external xtal */ #define USE_PLL_HSE_XTAL (1) /* Use external xtal */
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Private_Variables /** @addtogroup STM32F4xx_System_Private_Variables
* @{ * @{
*/ */
@ -154,24 +117,6 @@
uint32_t SystemCoreClock = 16000000; uint32_t SystemCoreClock = 16000000;
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
* @{
*/
uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Private_Functions
* @{
*/
/** /**
* @brief Setup the microcontroller system * @brief Setup the microcontroller system
* Initialize the FPU setting, vector table location and External memory * Initialize the FPU setting, vector table location and External memory
@ -187,19 +132,21 @@ void SystemInit(void)
#endif #endif
/* Reset the RCC clock configuration to the default reset state ------------*/ /* Reset the RCC clock configuration to the default reset state ------------*/
/* Set HSION bit */ /* Set HSION bit */
RCC->CR |= (uint32_t)0x00000001; RCC->CR |= RCC_CR_HSION;
/* Reset CFGR register */ /* Reset CFGR register */
RCC->CFGR = 0x00000000; RCC->CFGR = 0x00000000;
/* Reset HSEON, CSSON and PLLON bits */ /* Reset HSEON, CSSON and PLLON bits */
RCC->CR &= (uint32_t)0xFEF6FFFF; RCC->CR &= ~(RCC_CR_HSEON |
RCC_CR_CSSON |
RCC_CR_PLLON);
/* Reset PLLCFGR register */ /* Reset PLLCFGR register */
RCC->PLLCFGR = 0x24003010; RCC->PLLCFGR = 0x24003010;
/* Reset HSEBYP bit */ /* Reset HSEBYP bit */
RCC->CR &= (uint32_t)0xFFFBFFFF; RCC->CR &= ~(RCC_CR_HSEBYP);
/* Disable all interrupts */ /* Disable all interrupts */
RCC->CIR = 0x00000000; RCC->CIR = 0x00000000;
@ -209,7 +156,6 @@ void SystemInit(void)
/* Configure the System clock source, PLL Multiplier and Divider factors, /* Configure the System clock source, PLL Multiplier and Divider factors,
AHB/APBx prescalers and Flash settings */ AHB/APBx prescalers and Flash settings */
SetSysClock(); SetSysClock();
} }
/** /**
@ -257,13 +203,13 @@ void SystemCoreClockUpdate(void)
switch (tmp) switch (tmp)
{ {
case 0x00: /* HSI used as system clock source */ case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
SystemCoreClock = HSI_VALUE; SystemCoreClock = HSI_VALUE;
break; break;
case 0x04: /* HSE used as system clock source */ case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
SystemCoreClock = HSE_VALUE; SystemCoreClock = HSE_VALUE;
break; break;
case 0x08: /* PLL used as system clock source */ case RCC_CFGR_SWS_PLL: /* PLL used as system clock source */
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
SYSCLK = PLL_VCO / PLL_P SYSCLK = PLL_VCO / PLL_P
@ -312,57 +258,61 @@ void SetSysClock(void)
regarding system frequency refer to product datasheet. */ regarding system frequency refer to product datasheet. */
RCC->APB1ENR |= RCC_APB1ENR_PWREN; RCC->APB1ENR |= RCC_APB1ENR_PWREN;
MODIFY_REG(PWR->CR, PWR_CR_VOS, PWR_CR_VOS_1); PWR->CR |= PWR_CR_VOS;
/* Enable HSE oscillator and activate PLL with HSE as source */ /* Enable HSE oscillator and activate PLL with HSE as source */
/*------------------------------- HSE Configuration ------------------------*/ /*------------------------------- HSE Configuration ------------------------*/
/* Reset HSEON and HSEBYP bits before configuring the HSE --------------*/ /* Reset HSEON and HSEBYP bits before configuring the HSE --------------*/
RCC->CR &= ~(RCC_CR_HSEON); RCC->CR &= ~(RCC_CR_HSEON);
//__HAL_RCC_HSE_CONFIG(RCC_HSE_OFF);
/* Wait till HSE is disabled */
while(RCC->CR & RCC_CR_HSERDY); while(RCC->CR & RCC_CR_HSERDY);
/* Set the new HSE configuration ---------------------------------------*/ /* Set the new HSE configuration ---------------------------------------*/
RCC->CR |= RCC_CR_HSEON; RCC->CR |= RCC_CR_HSEON;
/* Wait till HSE is ready */
while(!(RCC->CR & RCC_CR_HSERDY)); while(!(RCC->CR & RCC_CR_HSERDY));
/*-------------------------------- PLL Configuration -----------------------*/ /*-------------------------------- PLL Configuration -----------------------*/
/* Disable the main PLL. */ /* Disable the main PLL. */
RCC->CR &= ~(RCC_CR_PLLON); RCC->CR &= ~(RCC_CR_PLLON);
/* Wait till PLL is ready */
while(RCC->CR & RCC_CR_PLLRDY); while(RCC->CR & RCC_CR_PLLRDY);
/* Configure the main PLL clock source, multiplication and division factors. */ /* Configure the main PLL clock source, multiplication and division factors. */
// PLLM_2: VCO input clock = 2 MHz (8 MHz / 4) // PLLM: VCO input clock = 2 MHz (8 MHz / 4)
// PLLN_6/7: VCO output clock = 384 MHz (2 MHz * 192) // PLLN: VCO output clock = 384 MHz (2 MHz * 192)
// PLLP_0: PLLCLK = 96 MHz (384 MHz / 4) // PLLP: PLLCLK = 96 MHz (384 MHz / 4)
// PLLQ_3: USB clock = 48 MHz (384 MHz / 8) --> 48MHz is best choice for USB // PLLQ: USB clock = 48 MHz (384 MHz / 8) --> 48MHz is best choice for USB
#if __SYSTEM_CLOCK == 96000000 #if __SYSTEM_CLOCK == 96000000
RCC->PLLCFGR = RCC_PLLCFGR_PLLSRC_HSE | RCC_PLLCFGR_PLLM_2 | \ #define PLLM 4
RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | \ #define PLLN 192
RCC_PLLCFGR_PLLP_0 | \ #define PLLP 4
RCC_PLLCFGR_PLLQ_3; #define PLLQ 8
#elif __SYSTEM_CLOCK == 100000000 #elif __SYSTEM_CLOCK == 100000000
RCC->PLLCFGR = RCC_PLLCFGR_PLLSRC_HSE | RCC_PLLCFGR_PLLM_2 | \ #define PLLM 4
RCC_PLLCFGR_PLLN_3 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | \ #define PLLN 200
RCC_PLLCFGR_PLLP_0 | \ #define PLLP 4
RCC_PLLCFGR_PLLQ_3; #define PLLQ 8
#elif __SYSTEM_CLOCK == 108000000 #elif __SYSTEM_CLOCK == 108000000
RCC->PLLCFGR = RCC_PLLCFGR_PLLSRC_HSE | RCC_PLLCFGR_PLLM_2 | \ #warning You are running the controller out of specification!
RCC_PLLCFGR_PLLN_3 | RCC_PLLCFGR_PLLN_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | \ #define PLLM 4
RCC_PLLCFGR_PLLP_0 | \ #define PLLN 216
RCC_PLLCFGR_PLLQ_0 | RCC_PLLCFGR_PLLQ_3; #define PLLP 4
#define PLLQ 9
#elif __SYSTEM_CLOCK == 125000000
#warning You are running the controller out of specification!
#define PLLM 4
#define PLLN 250
#define PLLP 4
#define PLLQ 10
#endif #endif
RCC->PLLCFGR = RCC_PLLCFGR_PLLSRC_HSE |
((PLLM << 0) & RCC_PLLCFGR_PLLM) |
((PLLN << 6) & RCC_PLLCFGR_PLLN) |
(((PLLP/2 - 1) << 16) & RCC_PLLCFGR_PLLP) |
((PLLQ << 24) & RCC_PLLCFGR_PLLQ);
/* Enable the main PLL. */ /* Enable the main PLL. */
RCC->CR |= RCC_CR_PLLON; RCC->CR |= RCC_CR_PLLON;
/* Wait till PLL is ready */
while(!(RCC->CR & RCC_CR_PLLRDY)); while(!(RCC->CR & RCC_CR_PLLRDY));
/* To correctly read data from FLASH memory, the number of wait states (LATENCY) /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
@ -373,39 +323,26 @@ void SetSysClock(void)
if(FLASH_ACR_LATENCY_3WS > (FLASH->ACR & FLASH_ACR_LATENCY)) if(FLASH_ACR_LATENCY_3WS > (FLASH->ACR & FLASH_ACR_LATENCY))
{ {
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, FLASH_ACR_LATENCY_3WS); FLASH->ACR &= ~(FLASH_ACR_LATENCY);
/*-------------------------- HCLK Configuration --------------------------*/ FLASH->ACR |= FLASH_ACR_LATENCY_3WS;
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_CFGR_HPRE_DIV1);
/*------------------------- SYSCLK Configuration ---------------------------*/ RCC->CFGR &= ~(RCC_CFGR_HPRE | RCC_CFGR_SW);
MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_CFGR_SW_PLL); RCC->CFGR |= RCC_CFGR_HPRE_DIV1 | RCC_CFGR_SW_PLL;
} }
/* Decreasing the CPU frequency */ /* Decreasing the CPU frequency */
else else
{ {
/*-------------------------- HCLK Configuration --------------------------*/ RCC->CFGR &= ~(RCC_CFGR_HPRE | RCC_CFGR_SW);
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_CFGR_HPRE_DIV1); RCC->CFGR |= RCC_CFGR_HPRE_DIV1 | RCC_CFGR_SW_PLL;
/*------------------------- SYSCLK Configuration -------------------------*/
MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_CFGR_SW_PLL);
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, FLASH_ACR_LATENCY_3WS); FLASH->ACR &= ~(FLASH_ACR_LATENCY);
FLASH->ACR |= FLASH_ACR_LATENCY_3WS;
} }
/*-------------------------- PCLK1 Configuration ---------------------------*/ RCC->CFGR &= ~(RCC_CFGR_PPRE1 | RCC_CFGR_PPRE2);
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_CFGR_PPRE1_DIV2); RCC->CFGR |= PPRE1_DIV | PPRE2_DIV;
/*-------------------------- PCLK2 Configuration ---------------------------*/
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, RCC_CFGR_PPRE2_DIV1);
} }
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
#endif #endif

68
cmsis-system_stm32f4xx.h
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@ -41,17 +41,10 @@
- Prefixed names of #include files with cmsis- to match the names of the - Prefixed names of #include files with cmsis- to match the names of the
copies in the Teacup repo. copies in the Teacup repo.
- Cleanup file
- Add different clock frequencies
*/ */
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32f4xx_system
* @{
*/
/** /**
* @brief Define to prevent recursive inclusion * @brief Define to prevent recursive inclusion
*/ */
@ -65,59 +58,15 @@
// #define __SYSTEM_CLOCK 96000000 // #define __SYSTEM_CLOCK 96000000
#define __SYSTEM_CLOCK 100000000 #define __SYSTEM_CLOCK 100000000
// #define __SYSTEM_CLOCK 108000000 // Overclocking is not recommended! // #define __SYSTEM_CLOCK 108000000 // Overclocking is not recommended!
/** @addtogroup STM32F4xx_System_Includes
* @{
*/
/** /*
* @} This variable is updated in by calling CMSIS function SystemCoreClockUpdate()
*/ */
/** @addtogroup STM32F4xx_System_Exported_types
* @{
*/
/* This variable is updated in three ways:
1) by calling CMSIS function SystemCoreClockUpdate()
2) by calling HAL API function HAL_RCC_GetSysClockFreq()
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
Note: If you use this function to configure the system clock; then there
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Exported_Constants
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Exported_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Exported_Functions
* @{
*/
extern void SystemInit(void); extern void SystemInit(void);
extern void SystemCoreClockUpdate(void); extern void SystemCoreClockUpdate(void);
extern void SetSysClock(void); extern void SetSysClock(void);
/**
* @}
*/
#ifdef __cplusplus #ifdef __cplusplus
} }
@ -125,11 +74,4 @@ extern void SetSysClock(void);
#endif /*__SYSTEM_STM32F4XX_H */ #endif /*__SYSTEM_STM32F4XX_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/