stm32: new startup and linker script
also add stm32f446 http://git.munts.com/arm-mcu/gcc/stm32f4/ rename lpc startup from 's' to 'S' to let the c preprocessor do its job stm32f4xx linker and startup file cmsis prefix just for naming files has nothing todo with cmsis anymore
This commit is contained in:
Nico Tonnhofer
parent
a4959ff0dd
commit
bd5bfb3d76
34
Makefile-ARM
34
Makefile-ARM
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@ -42,6 +42,7 @@
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MCU ?= lpc1114
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MCU ?= lpc1114
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# MCU ?= stm32f411
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# MCU ?= stm32f411
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# MCU ?= stm32f446
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# some size parameters. Not important for flashing and compiling.
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# some size parameters. Not important for flashing and compiling.
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ifeq ($(MCU), lpc1114)
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ifeq ($(MCU), lpc1114)
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@ -50,6 +51,9 @@ ifeq ($(MCU), lpc1114)
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else ifeq ($(MCU), stm32f411)
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else ifeq ($(MCU), stm32f411)
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FLASH_SIZE = 512
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FLASH_SIZE = 512
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RAM_SIZE = 128
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RAM_SIZE = 128
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else ifeq ($(MCU), stm32f446)
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FLASH_SIZE = 512
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RAM_SIZE = 128
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endif
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endif
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# CPU clock rate not defined here, but in the CMSIS headers.
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# CPU clock rate not defined here, but in the CMSIS headers.
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@ -85,7 +89,7 @@ F_CRYSTAL ?= 12000000
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ifeq ($(MCU), lpc1114)
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ifeq ($(MCU), lpc1114)
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UPLOADER ?= lpc21isp -control
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UPLOADER ?= lpc21isp -control
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UPLOAD_FILE = $(PROGRAM).hex
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UPLOAD_FILE = $(PROGRAM).hex
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else ifeq ($(MCU), stm32f411)
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else ifeq ($(findstring stm32, $(MCU)), stm32)
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UPLOADER ?= st-flash --reset write
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UPLOADER ?= st-flash --reset write
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UPLOAD_FILE = $(BUILDDIR)/$(PROGRAM).bin
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UPLOAD_FILE = $(BUILDDIR)/$(PROGRAM).bin
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endif
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endif
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@ -94,7 +98,7 @@ ifeq ($(MCU), lpc1114)
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UPLOADER_FLAGS = $(UPLOADER_PORT)
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UPLOADER_FLAGS = $(UPLOADER_PORT)
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UPLOADER_FLAGS += 115200
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UPLOADER_FLAGS += 115200
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UPLOADER_FLAGS += $(F_CRYSTAL)
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UPLOADER_FLAGS += $(F_CRYSTAL)
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else ifeq ($(MCU), stm32f411)
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else ifeq ($(findstring stm32, $(MCU)), stm32)
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UPLOADER_FLAGS = 0x8000000
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UPLOADER_FLAGS = 0x8000000
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endif
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endif
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@ -120,9 +124,9 @@ SOURCES = $(wildcard *.c)
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# Other target MCU specific adjustments:
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# Other target MCU specific adjustments:
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ifeq ($(MCU), lpc1114)
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ifeq ($(MCU), lpc1114)
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STARTUP_FILE = cmsis-startup_lpc11xx.s
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STARTUP_FILE = cmsis-startup_lpc11xx.S
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else ifeq ($(MCU), stm32f411)
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else ifeq ($(findstring stm32, $(MCU)), stm32)
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STARTUP_FILE = cmsis-startup_stm32f411xe.s
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STARTUP_FILE = cmsis-startup_stm32f4xx.S
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endif
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endif
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# Link time optimization is on by default
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# Link time optimization is on by default
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@ -135,7 +139,7 @@ ifeq ($(MCU), lpc1114)
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CFLAGS += -mthumb -mcpu=cortex-m0
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CFLAGS += -mthumb -mcpu=cortex-m0
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CFLAGS += -mtune=cortex-m0
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CFLAGS += -mtune=cortex-m0
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CFLAGS += -D__ARM_LPC1114__
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CFLAGS += -D__ARM_LPC1114__
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else ifeq ($(MCU), stm32f411)
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else ifeq ($(findstring stm32, $(MCU)), stm32)
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CFLAGS += -mthumb -mcpu=cortex-m4
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CFLAGS += -mthumb -mcpu=cortex-m4
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CFLAGS += -mtune=cortex-m4
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CFLAGS += -mtune=cortex-m4
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CFLAGS += -D__ARM_STM32F411__
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CFLAGS += -D__ARM_STM32F411__
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@ -144,6 +148,14 @@ else ifeq ($(MCU), stm32f411)
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CFLAGS += -mlittle-endian
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CFLAGS += -mlittle-endian
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CFLAGS += -D__FPU_PRESENT=1
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CFLAGS += -D__FPU_PRESENT=1
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CFLAGS += -fomit-frame-pointer
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CFLAGS += -fomit-frame-pointer
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CFLAGS += -nostartfiles
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endif
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ifeq ($(MCU), stm32f411)
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CFLAGS += -DSTM32F411xE
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CFLAGS += -D__SYSTEM_CLOCK=100000000
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else ifeq ($(MCU), stm32f446)
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CFLAGS += -DSTM32F446xx
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CFLAGS += -D__SYSTEM_CLOCK=180000000
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endif
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endif
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# Other options ...
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# Other options ...
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CFLAGS += -Wall
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CFLAGS += -Wall
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@ -160,8 +172,8 @@ LDFLAGS = --specs=nano.specs
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LDFLAGS += --specs=nosys.specs
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LDFLAGS += --specs=nosys.specs
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ifeq ($(MCU), lpc1114)
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ifeq ($(MCU), lpc1114)
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LDFLAGS += -T cmsis-lpc1114.ld
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LDFLAGS += -T cmsis-lpc1114.ld
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else ifeq ($(MCU), stm32f411)
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else ifeq ($(findstring stm32, $(MCU)), stm32)
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LDFLAGS += -T cmsis-stm32f411xe.ld
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LDFLAGS += -T cmsis-stm32f4xx.ld
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endif
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endif
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LDFLAGS += -Wl,--as-needed
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LDFLAGS += -Wl,--as-needed
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LDFLAGS += -Wl,--gc-sections
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LDFLAGS += -Wl,--gc-sections
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@ -176,9 +188,6 @@ LIBS = -lm
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all: $(PROGRAM).hex $(BUILDDIR)/$(PROGRAM).lst $(BUILDDIR)/$(PROGRAM).sym size
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all: $(PROGRAM).hex $(BUILDDIR)/$(PROGRAM).lst $(BUILDDIR)/$(PROGRAM).sym size
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# TODO: The echo is only for Gen7-ARM LPC1114. The stm flashes don't need this.
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# This message could confuse someone. Remove this message for stm or write some
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# friendly text for it.
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ifeq ($(MCU), lpc1114)
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ifeq ($(MCU), lpc1114)
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define upload_echo
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define upload_echo
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@echo
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@echo
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@ -188,11 +197,10 @@ define upload_echo
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@echo "Gen7-ARM, PIO0_1 is the Step pin of the Z stepper driver."
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@echo "Gen7-ARM, PIO0_1 is the Step pin of the Z stepper driver."
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@echo
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@echo
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endef
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endef
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else ifeq ($(MCU), stm32f411)
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else ifeq ($(findstring stm32, $(MCU)), stm32)
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define upload_echo
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define upload_echo
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@echo
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@echo
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@echo "Starting upload..."
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@echo "Starting upload..."
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@echo "This should normally take no time."
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@echo
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@echo
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endef
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endef
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endif
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endif
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@ -222,4 +222,3 @@ Reset_Handler:
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def_irq_default_handler DEF_IRQHandler
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def_irq_default_handler DEF_IRQHandler
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.end
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.end
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@ -1,459 +0,0 @@
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/**
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******************************************************************************
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* @file startup_stm32f411xe.s
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* @author MCD Application Team
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* @version V2.3.0
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* @date 02-March-2015
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* @brief STM32F411xExx Devices vector table for Atollic TrueSTUDIO toolchain.
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* This module performs:
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* - Set the initial SP
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* - Set the initial PC == Reset_Handler,
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* - Set the vector table entries with the exceptions ISR address
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* - Branches to main in the C library (which eventually
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* calls main()).
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* After Reset the Cortex-M4 processor is in Thread mode,
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* priority is Privileged, and the Stack is set to Main.
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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.syntax unified
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.cpu cortex-m4
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.fpu softvfp
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.thumb
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.global g_pfnVectors
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.global Default_Handler
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/* start address for the initialization values of the .data section.
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defined in linker script */
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.word _sidata
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/* start address for the .data section. defined in linker script */
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.word _sdata
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/* end address for the .data section. defined in linker script */
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.word _edata
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/* start address for the .bss section. defined in linker script */
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.word _sbss
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/* end address for the .bss section. defined in linker script */
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.word _ebss
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/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
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/**
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* @brief This is the code that gets called when the processor first
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* starts execution following a reset event. Only the absolutely
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* necessary set is performed, after which the application
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* supplied main() routine is called.
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* @param None
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* @retval : None
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*/
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.section .text.Reset_Handler
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.weak Reset_Handler
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.type Reset_Handler, %function
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Reset_Handler:
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ldr sp, =_estack /* set stack pointer */
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/* Copy the data segment initializers from flash to SRAM */
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movs r1, #0
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b LoopCopyDataInit
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CopyDataInit:
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ldr r3, =_sidata
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ldr r3, [r3, r1]
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str r3, [r0, r1]
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adds r1, r1, #4
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LoopCopyDataInit:
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ldr r0, =_sdata
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ldr r3, =_edata
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adds r2, r0, r1
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cmp r2, r3
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bcc CopyDataInit
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ldr r2, =_sbss
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b LoopFillZerobss
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/* Zero fill the bss segment. */
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FillZerobss:
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movs r3, #0
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str r3, [r2], #4
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LoopFillZerobss:
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ldr r3, = _ebss
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cmp r2, r3
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bcc FillZerobss
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/* Call the clock system intitialization function.*/
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bl SystemInit
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/* Call static constructors */
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//bl __libc_init_array
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/* Call the application's entry point.*/
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//bl main
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// Calling the crt0 'cold-start' entry point. There __libc_init_array is called
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// and when existing hardware_init_hook() and software_init_hook() before
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// starting main(). software_init_hook() is available and has to be called due
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// to initializsation when using rtos.
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bl _start
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bx lr
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.size Reset_Handler, .-Reset_Handler
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/**
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* @brief This is the code that gets called when the processor receives an
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* unexpected interrupt. This simply enters an infinite loop, preserving
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* the system state for examination by a debugger.
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* @param None
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* @retval None
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*/
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.section .text.Default_Handler,"ax",%progbits
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Default_Handler:
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Infinite_Loop:
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b Infinite_Loop
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.size Default_Handler, .-Default_Handler
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/******************************************************************************
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*
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* The minimal vector table for a Cortex M3. Note that the proper constructs
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* must be placed on this to ensure that it ends up at physical address
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* 0x0000.0000.
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*
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*******************************************************************************/
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.section .isr_vector,"a",%progbits
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.type g_pfnVectors, %object
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.size g_pfnVectors, .-g_pfnVectors
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g_pfnVectors:
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.word _estack
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.word Reset_Handler
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.word NMI_Handler
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.word HardFault_Handler
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.word MemManage_Handler
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.word BusFault_Handler
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.word UsageFault_Handler
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.word 0
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.word 0
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.word 0
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.word 0
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.word SVC_Handler
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.word DebugMon_Handler
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.word 0
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.word PendSV_Handler
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.word SysTick_Handler
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/* External Interrupts */
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.word WWDG_IRQHandler /* Window WatchDog */
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.word PVD_IRQHandler /* PVD through EXTI Line detection */
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.word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
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.word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
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.word FLASH_IRQHandler /* FLASH */
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.word RCC_IRQHandler /* RCC */
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.word EXTI0_IRQHandler /* EXTI Line0 */
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.word EXTI1_IRQHandler /* EXTI Line1 */
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.word EXTI2_IRQHandler /* EXTI Line2 */
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.word EXTI3_IRQHandler /* EXTI Line3 */
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.word EXTI4_IRQHandler /* EXTI Line4 */
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.word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
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.word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
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.word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
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.word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
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.word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
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.word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
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.word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
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.word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word EXTI9_5_IRQHandler /* External Line[9:5]s */
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.word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */
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.word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */
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.word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
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.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
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.word TIM2_IRQHandler /* TIM2 */
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.word TIM3_IRQHandler /* TIM3 */
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.word TIM4_IRQHandler /* TIM4 */
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.word I2C1_EV_IRQHandler /* I2C1 Event */
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.word I2C1_ER_IRQHandler /* I2C1 Error */
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.word I2C2_EV_IRQHandler /* I2C2 Event */
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.word I2C2_ER_IRQHandler /* I2C2 Error */
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.word SPI1_IRQHandler /* SPI1 */
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.word SPI2_IRQHandler /* SPI2 */
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.word USART1_IRQHandler /* USART1 */
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.word USART2_IRQHandler /* USART2 */
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.word 0 /* Reserved */
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.word EXTI15_10_IRQHandler /* External Line[15:10]s */
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.word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
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.word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
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.word 0 /* Reserved */
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.word SDIO_IRQHandler /* SDIO */
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.word TIM5_IRQHandler /* TIM5 */
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.word SPI3_IRQHandler /* SPI3 */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
|
|
||||||
.word 0 /* Reserved */
|
|
||||||
.word 0 /* Reserved */
|
|
||||||
.word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
|
|
||||||
.word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
|
|
||||||
.word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
|
|
||||||
.word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
|
|
||||||
.word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
|
|
||||||
.word 0 /* Reserved */
|
|
||||||
.word 0 /* Reserved */
|
|
||||||
.word 0 /* Reserved */
|
|
||||||
.word 0 /* Reserved */
|
|
||||||
.word 0 /* Reserved */
|
|
||||||
.word 0 /* Reserved */
|
|
||||||
.word OTG_FS_IRQHandler /* USB OTG FS */
|
|
||||||
.word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
|
|
||||||
.word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
|
|
||||||
.word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
|
|
||||||
.word USART6_IRQHandler /* USART6 */
|
|
||||||
.word I2C3_EV_IRQHandler /* I2C3 event */
|
|
||||||
.word I2C3_ER_IRQHandler /* I2C3 error */
|
|
||||||
.word 0 /* Reserved */
|
|
||||||
.word 0 /* Reserved */
|
|
||||||
.word 0 /* Reserved */
|
|
||||||
.word 0 /* Reserved */
|
|
||||||
.word 0 /* Reserved */
|
|
||||||
.word 0 /* Reserved */
|
|
||||||
.word 0 /* Reserved */
|
|
||||||
.word FPU_IRQHandler /* FPU */
|
|
||||||
.word 0 /* Reserved */
|
|
||||||
.word 0 /* Reserved */
|
|
||||||
.word SPI4_IRQHandler /* SPI4 */
|
|
||||||
.word SPI5_IRQHandler /* SPI5 */
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
*
|
|
||||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
|
||||||
* As they are weak aliases, any function with the same name will override
|
|
||||||
* this definition.
|
|
||||||
*
|
|
||||||
*******************************************************************************/
|
|
||||||
.weak NMI_Handler
|
|
||||||
.thumb_set NMI_Handler,Default_Handler
|
|
||||||
|
|
||||||
.weak HardFault_Handler
|
|
||||||
.thumb_set HardFault_Handler,Default_Handler
|
|
||||||
|
|
||||||
.weak MemManage_Handler
|
|
||||||
.thumb_set MemManage_Handler,Default_Handler
|
|
||||||
|
|
||||||
.weak BusFault_Handler
|
|
||||||
.thumb_set BusFault_Handler,Default_Handler
|
|
||||||
|
|
||||||
.weak UsageFault_Handler
|
|
||||||
.thumb_set UsageFault_Handler,Default_Handler
|
|
||||||
|
|
||||||
.weak SVC_Handler
|
|
||||||
.thumb_set SVC_Handler,Default_Handler
|
|
||||||
|
|
||||||
.weak DebugMon_Handler
|
|
||||||
.thumb_set DebugMon_Handler,Default_Handler
|
|
||||||
|
|
||||||
.weak PendSV_Handler
|
|
||||||
.thumb_set PendSV_Handler,Default_Handler
|
|
||||||
|
|
||||||
.weak SysTick_Handler
|
|
||||||
.thumb_set SysTick_Handler,Default_Handler
|
|
||||||
|
|
||||||
.weak WWDG_IRQHandler
|
|
||||||
.thumb_set WWDG_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak PVD_IRQHandler
|
|
||||||
.thumb_set PVD_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak TAMP_STAMP_IRQHandler
|
|
||||||
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak RTC_WKUP_IRQHandler
|
|
||||||
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak FLASH_IRQHandler
|
|
||||||
.thumb_set FLASH_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak RCC_IRQHandler
|
|
||||||
.thumb_set RCC_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak EXTI0_IRQHandler
|
|
||||||
.thumb_set EXTI0_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak EXTI1_IRQHandler
|
|
||||||
.thumb_set EXTI1_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak EXTI2_IRQHandler
|
|
||||||
.thumb_set EXTI2_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak EXTI3_IRQHandler
|
|
||||||
.thumb_set EXTI3_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak EXTI4_IRQHandler
|
|
||||||
.thumb_set EXTI4_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA1_Stream0_IRQHandler
|
|
||||||
.thumb_set DMA1_Stream0_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA1_Stream1_IRQHandler
|
|
||||||
.thumb_set DMA1_Stream1_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA1_Stream2_IRQHandler
|
|
||||||
.thumb_set DMA1_Stream2_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA1_Stream3_IRQHandler
|
|
||||||
.thumb_set DMA1_Stream3_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA1_Stream4_IRQHandler
|
|
||||||
.thumb_set DMA1_Stream4_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA1_Stream5_IRQHandler
|
|
||||||
.thumb_set DMA1_Stream5_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA1_Stream6_IRQHandler
|
|
||||||
.thumb_set DMA1_Stream6_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak ADC_IRQHandler
|
|
||||||
.thumb_set ADC_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak EXTI9_5_IRQHandler
|
|
||||||
.thumb_set EXTI9_5_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak TIM1_BRK_TIM9_IRQHandler
|
|
||||||
.thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak TIM1_UP_TIM10_IRQHandler
|
|
||||||
.thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak TIM1_TRG_COM_TIM11_IRQHandler
|
|
||||||
.thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak TIM1_CC_IRQHandler
|
|
||||||
.thumb_set TIM1_CC_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak TIM2_IRQHandler
|
|
||||||
.thumb_set TIM2_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak TIM3_IRQHandler
|
|
||||||
.thumb_set TIM3_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak TIM4_IRQHandler
|
|
||||||
.thumb_set TIM4_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak I2C1_EV_IRQHandler
|
|
||||||
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak I2C1_ER_IRQHandler
|
|
||||||
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak I2C2_EV_IRQHandler
|
|
||||||
.thumb_set I2C2_EV_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak I2C2_ER_IRQHandler
|
|
||||||
.thumb_set I2C2_ER_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak SPI1_IRQHandler
|
|
||||||
.thumb_set SPI1_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak SPI2_IRQHandler
|
|
||||||
.thumb_set SPI2_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak USART1_IRQHandler
|
|
||||||
.thumb_set USART1_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak USART2_IRQHandler
|
|
||||||
.thumb_set USART2_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak EXTI15_10_IRQHandler
|
|
||||||
.thumb_set EXTI15_10_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak RTC_Alarm_IRQHandler
|
|
||||||
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak OTG_FS_WKUP_IRQHandler
|
|
||||||
.thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA1_Stream7_IRQHandler
|
|
||||||
.thumb_set DMA1_Stream7_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak SDIO_IRQHandler
|
|
||||||
.thumb_set SDIO_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak TIM5_IRQHandler
|
|
||||||
.thumb_set TIM5_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak SPI3_IRQHandler
|
|
||||||
.thumb_set SPI3_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA2_Stream0_IRQHandler
|
|
||||||
.thumb_set DMA2_Stream0_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA2_Stream1_IRQHandler
|
|
||||||
.thumb_set DMA2_Stream1_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA2_Stream2_IRQHandler
|
|
||||||
.thumb_set DMA2_Stream2_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA2_Stream3_IRQHandler
|
|
||||||
.thumb_set DMA2_Stream3_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA2_Stream4_IRQHandler
|
|
||||||
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak OTG_FS_IRQHandler
|
|
||||||
.thumb_set OTG_FS_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA2_Stream5_IRQHandler
|
|
||||||
.thumb_set DMA2_Stream5_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA2_Stream6_IRQHandler
|
|
||||||
.thumb_set DMA2_Stream6_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA2_Stream7_IRQHandler
|
|
||||||
.thumb_set DMA2_Stream7_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak USART6_IRQHandler
|
|
||||||
.thumb_set USART6_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak I2C3_EV_IRQHandler
|
|
||||||
.thumb_set I2C3_EV_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak I2C3_ER_IRQHandler
|
|
||||||
.thumb_set I2C3_ER_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak FPU_IRQHandler
|
|
||||||
.thumb_set FPU_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak SPI4_IRQHandler
|
|
||||||
.thumb_set SPI4_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak SPI5_IRQHandler
|
|
||||||
.thumb_set SPI5_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
||||||
|
|
||||||
|
|
@ -0,0 +1,289 @@
|
||||||
|
// Startup for STM32F4xx Cortex-M4 ARM MCU
|
||||||
|
|
||||||
|
// Copyright (C)2013-2018, Philip Munts, President, Munts AM Corp.
|
||||||
|
// Copyright (C)2019, Nico Tonnhofer
|
||||||
|
//
|
||||||
|
// Redistribution and use in source and binary forms, with or without
|
||||||
|
// modification, are permitted provided that the following conditions are met:
|
||||||
|
//
|
||||||
|
// * Redistributions of source code must retain the above copyright notice,
|
||||||
|
// this list of conditions and the following disclaimer.
|
||||||
|
//
|
||||||
|
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||||
|
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||||
|
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||||
|
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||||
|
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||||
|
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||||
|
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
// POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
|
||||||
|
.syntax unified
|
||||||
|
.thumb
|
||||||
|
.section .startup, "x"
|
||||||
|
|
||||||
|
// Export these symbols
|
||||||
|
|
||||||
|
.global _startup
|
||||||
|
.global _vectors
|
||||||
|
|
||||||
|
// Import these symbols
|
||||||
|
|
||||||
|
.extern __text_end__
|
||||||
|
.extern __data_beg__
|
||||||
|
.extern __data_end__
|
||||||
|
.extern __bss_beg__
|
||||||
|
.extern __bss_end__
|
||||||
|
.extern __stack_end__
|
||||||
|
.extern __ctors_start__
|
||||||
|
.extern __ctors_end__
|
||||||
|
.extern main
|
||||||
|
.extern _exit
|
||||||
|
|
||||||
|
//=============================================================================
|
||||||
|
|
||||||
|
// Use Default_handler for all exceptions and interrupts, unless another
|
||||||
|
// handler is provided elsewhere.
|
||||||
|
|
||||||
|
.macro IRQ handler
|
||||||
|
.word \handler
|
||||||
|
.weak \handler
|
||||||
|
.set \handler, Default_Handler
|
||||||
|
.endm
|
||||||
|
|
||||||
|
//=============================================================================
|
||||||
|
|
||||||
|
// Exception vector table--Common to all Cortex-M4
|
||||||
|
|
||||||
|
_vectors: .word __stack_end__
|
||||||
|
.word _startup
|
||||||
|
IRQ NMI_Handler
|
||||||
|
IRQ HardFault_Handler
|
||||||
|
IRQ MemManage_Handler
|
||||||
|
IRQ BusFault_Handler
|
||||||
|
IRQ UsageFault_Handler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
IRQ SVC_Handler
|
||||||
|
IRQ DebugMon_Handler
|
||||||
|
.word 0
|
||||||
|
IRQ PendSV_Handler
|
||||||
|
IRQ SysTick_Handler
|
||||||
|
|
||||||
|
// Hardware interrupts specific to the STM32F411RE
|
||||||
|
|
||||||
|
IRQ WWDG_IRQHandler
|
||||||
|
IRQ PVD_IRQHandler
|
||||||
|
IRQ TAMP_STAMP_IRQHandler
|
||||||
|
IRQ RTC_WKUP_IRQHandler
|
||||||
|
IRQ FLASH_IRQHandler
|
||||||
|
IRQ RCC_IRQHandler
|
||||||
|
IRQ EXTI0_IRQHandler
|
||||||
|
IRQ EXTI1_IRQHandler
|
||||||
|
IRQ EXTI2_IRQHandler
|
||||||
|
IRQ EXTI3_IRQHandler
|
||||||
|
IRQ EXTI4_IRQHandler
|
||||||
|
IRQ DMA1_Stream0_IRQHandler
|
||||||
|
IRQ DMA1_Stream1_IRQHandler
|
||||||
|
IRQ DMA1_Stream2_IRQHandler
|
||||||
|
IRQ DMA1_Stream3_IRQHandler
|
||||||
|
IRQ DMA1_Stream4_IRQHandler
|
||||||
|
IRQ DMA1_Stream5_IRQHandler
|
||||||
|
IRQ DMA1_Stream6_IRQHandler
|
||||||
|
IRQ ADC_IRQHandler
|
||||||
|
#ifdef STM32F446xx
|
||||||
|
IRQ CAN1_TX_IRQHandler
|
||||||
|
IRQ CAN1_RX0_IRQHandler
|
||||||
|
IRQ CAN1_RX1_IRQHandler
|
||||||
|
IRQ CAN1_SCE_IRQHandler
|
||||||
|
#else
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
#endif
|
||||||
|
IRQ EXTI9_5_IRQHandler
|
||||||
|
IRQ TIM1_BRK_TIM9_IRQHandler
|
||||||
|
IRQ TIM1_UP_TIM10_IRQHandler
|
||||||
|
IRQ TIM1_TRG_COM_TIM11_IRQHandler
|
||||||
|
IRQ TIM1_CC_IRQHandler
|
||||||
|
IRQ TIM2_IRQHandler
|
||||||
|
IRQ TIM3_IRQHandler
|
||||||
|
IRQ TIM4_IRQHandler
|
||||||
|
IRQ I2C1_EV_IRQHandler
|
||||||
|
IRQ I2C1_ER_IRQHandler
|
||||||
|
IRQ I2C2_EV_IRQHandler
|
||||||
|
IRQ I2C2_ER_IRQHandler
|
||||||
|
IRQ SPI1_IRQHandler
|
||||||
|
IRQ SPI2_IRQHandler
|
||||||
|
IRQ USART1_IRQHandler
|
||||||
|
IRQ USART2_IRQHandler
|
||||||
|
#ifdef STM32F446xx
|
||||||
|
IRQ USART3_IRQHandler
|
||||||
|
#else
|
||||||
|
.word 0
|
||||||
|
#endif
|
||||||
|
IRQ EXTI15_10_IRQHandler
|
||||||
|
IRQ RTC_Alarm_IRQHandler
|
||||||
|
#ifdef STM32F446xx
|
||||||
|
IRQ OTG_FS_WKUP_IRQHandler
|
||||||
|
IRQ TIM8_BRK_TIM12_IRQHandler
|
||||||
|
IRQ TIM8_UP_TIM13_IRQHandler
|
||||||
|
IRQ TIM8_TRG_COM_TIM14_IRQHandler
|
||||||
|
IRQ TIM8_CC_IRQHandler
|
||||||
|
#else
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
#endif
|
||||||
|
IRQ DMA1_Stream7_IRQHandler
|
||||||
|
#ifdef STM32F446xx
|
||||||
|
IRQ FMC_IRQHandler
|
||||||
|
#else
|
||||||
|
.word 0
|
||||||
|
#endif
|
||||||
|
IRQ SDIO_IRQHandler
|
||||||
|
IRQ TIM5_IRQHandler
|
||||||
|
IRQ SPI3_IRQHandler
|
||||||
|
#ifdef STM32F446xx
|
||||||
|
IRQ UART4_IRQHandler
|
||||||
|
IRQ UART5_IRQHandler
|
||||||
|
IRQ TIM6_DAC_IRQHandler
|
||||||
|
IRQ TIM7_IRQHandler
|
||||||
|
#else
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
#endif
|
||||||
|
IRQ DMA2_Stream0_IRQHandler
|
||||||
|
IRQ DMA2_Stream1_IRQHandler
|
||||||
|
IRQ DMA2_Stream2_IRQHandler
|
||||||
|
IRQ DMA2_Stream3_IRQHandler
|
||||||
|
IRQ DMA2_Stream4_IRQHandler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
#ifdef STM32F446xx
|
||||||
|
IRQ CAN2_TX_IRQHandler
|
||||||
|
IRQ CAN2_RX0_IRQHandler
|
||||||
|
IRQ CAN2_RX1_IRQHandler
|
||||||
|
IRQ CAN2_SCE_IRQHandler
|
||||||
|
#else
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
#endif
|
||||||
|
IRQ OTG_FS_IRQHandler
|
||||||
|
IRQ DMA2_Stream5_IRQHandler
|
||||||
|
IRQ DMA2_Stream6_IRQHandler
|
||||||
|
IRQ DMA2_Stream7_IRQHandler
|
||||||
|
IRQ USART6_IRQHandler
|
||||||
|
IRQ I2C3_EV_IRQHandler
|
||||||
|
IRQ I2C3_ER_IRQHandler
|
||||||
|
#ifdef STM32F446xx
|
||||||
|
IRQ OTG_HS_EP1_OUT_IRQHandler
|
||||||
|
IRQ OTG_HS_EP1_IN_IRQHandler
|
||||||
|
IRQ OTG_HS_WKUP_IRQHandler
|
||||||
|
IRQ OTG_HS_IRQHandler
|
||||||
|
IRQ DCMI_IRQHandler
|
||||||
|
#else
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
#endif
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
IRQ FPU_IRQHandler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
IRQ SPI4_IRQHandler
|
||||||
|
IRQ SPI5_IRQHandler
|
||||||
|
|
||||||
|
//=============================================================================
|
||||||
|
|
||||||
|
// Default exception handler--does nothing but return
|
||||||
|
|
||||||
|
.thumb_func
|
||||||
|
Default_Handler: bx lr
|
||||||
|
|
||||||
|
//=============================================================================
|
||||||
|
|
||||||
|
// Reset vector: Set up environment to call C main()
|
||||||
|
|
||||||
|
.thumb_func
|
||||||
|
_startup:
|
||||||
|
|
||||||
|
// Copy initialized data from flash to RAM
|
||||||
|
|
||||||
|
copy_data: ldr r1, DATA_BEG
|
||||||
|
ldr r2, TEXT_END
|
||||||
|
ldr r3, DATA_END
|
||||||
|
subs r3, r3, r1 // Length of initialized data
|
||||||
|
beq zero_bss // Skip if none
|
||||||
|
|
||||||
|
copy_data_loop: ldrb r4, [r2], #1 // Read byte from flash
|
||||||
|
strb r4, [r1], #1 // Store byte to RAM
|
||||||
|
subs r3, r3, #1 // Decrement counter
|
||||||
|
bgt copy_data_loop // Repeat until done
|
||||||
|
|
||||||
|
// Zero uninitialized data (bss)
|
||||||
|
|
||||||
|
zero_bss: ldr r1, BSS_BEG
|
||||||
|
ldr r3, BSS_END
|
||||||
|
subs r3, r3, r1 // Length of uninitialized data
|
||||||
|
beq call_ctors // Skip if none
|
||||||
|
|
||||||
|
mov r2, #0
|
||||||
|
|
||||||
|
zero_bss_loop: strb r2, [r1], #1 // Store zero
|
||||||
|
subs r3, r3, #1 // Decrement counter
|
||||||
|
bgt zero_bss_loop // Repeat until done
|
||||||
|
|
||||||
|
// Call C++ constructors. The compiler and linker together populate the .ctors
|
||||||
|
// code section with the addresses of the constructor functions.
|
||||||
|
|
||||||
|
call_ctors: ldr r0, CTORS_BEG
|
||||||
|
ldr r1, CTORS_END
|
||||||
|
subs r1, r1, r0 // Length of ctors section
|
||||||
|
beq call_main // Skip if no constructors
|
||||||
|
|
||||||
|
ctors_loop: ldr r2, [r0], #4 // Load next constructor address
|
||||||
|
push {r0,r1} // Save registers
|
||||||
|
blx r2 // Call constructor
|
||||||
|
pop {r0,r1} // Restore registers
|
||||||
|
subs r1, r1, #4 // Decrement counter
|
||||||
|
bgt ctors_loop // Repeat until done
|
||||||
|
|
||||||
|
// Call main()
|
||||||
|
|
||||||
|
call_main: mov r0, #0 // argc=0
|
||||||
|
mov r1, #0 // argv=NULL
|
||||||
|
|
||||||
|
bl SystemInit // Call SystemInit()
|
||||||
|
bl main // Call C main()
|
||||||
|
bl _exit // Call _exit() if main() returns
|
||||||
|
|
||||||
|
//=============================================================================
|
||||||
|
|
||||||
|
// These are filled in by the linker
|
||||||
|
|
||||||
|
.align 4
|
||||||
|
TEXT_END: .word __text_end__
|
||||||
|
DATA_BEG: .word __data_beg__
|
||||||
|
DATA_END: .word __data_end__
|
||||||
|
BSS_BEG: .word __bss_beg__
|
||||||
|
BSS_END: .word __bss_end__
|
||||||
|
CTORS_BEG: .word __ctors_start__
|
||||||
|
CTORS_END: .word __ctors_end__
|
||||||
|
|
||||||
|
.end
|
||||||
|
|
@ -1,153 +0,0 @@
|
||||||
/* Linker script to configure memory regions. */
|
|
||||||
MEMORY
|
|
||||||
{
|
|
||||||
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K
|
|
||||||
RAM (rwx) : ORIGIN = 0x20000198, LENGTH = 128k - 0x198
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Linker script to place sections and symbol values. Should be used together
|
|
||||||
* with other linker script that defines memory regions FLASH and RAM.
|
|
||||||
* It references following symbols, which must be defined in code:
|
|
||||||
* Reset_Handler : Entry of reset handler
|
|
||||||
*
|
|
||||||
* It defines following symbols, which code can use without definition:
|
|
||||||
* __exidx_start
|
|
||||||
* __exidx_end
|
|
||||||
* __etext
|
|
||||||
* __data_start__
|
|
||||||
* __preinit_array_start
|
|
||||||
* __preinit_array_end
|
|
||||||
* __init_array_start
|
|
||||||
* __init_array_end
|
|
||||||
* __fini_array_start
|
|
||||||
* __fini_array_end
|
|
||||||
* __data_end__
|
|
||||||
* __bss_start__
|
|
||||||
* __bss_end__
|
|
||||||
* __end__
|
|
||||||
* end
|
|
||||||
* __HeapLimit
|
|
||||||
* __StackLimit
|
|
||||||
* __StackTop
|
|
||||||
* __stack
|
|
||||||
* _estack
|
|
||||||
*/
|
|
||||||
ENTRY(Reset_Handler)
|
|
||||||
|
|
||||||
SECTIONS
|
|
||||||
{
|
|
||||||
.text :
|
|
||||||
{
|
|
||||||
KEEP(*(.isr_vector))
|
|
||||||
*(.text*)
|
|
||||||
KEEP(*(.init))
|
|
||||||
KEEP(*(.fini))
|
|
||||||
|
|
||||||
/* .ctors */
|
|
||||||
*crtbegin.o(.ctors)
|
|
||||||
*crtbegin?.o(.ctors)
|
|
||||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
|
|
||||||
*(SORT(.ctors.*))
|
|
||||||
*(.ctors)
|
|
||||||
|
|
||||||
/* .dtors */
|
|
||||||
*crtbegin.o(.dtors)
|
|
||||||
*crtbegin?.o(.dtors)
|
|
||||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
|
|
||||||
*(SORT(.dtors.*))
|
|
||||||
*(.dtors)
|
|
||||||
|
|
||||||
*(.rodata*)
|
|
||||||
|
|
||||||
KEEP(*(.eh_frame*))
|
|
||||||
} > FLASH
|
|
||||||
|
|
||||||
.ARM.extab :
|
|
||||||
{
|
|
||||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
|
||||||
} > FLASH
|
|
||||||
|
|
||||||
__exidx_start = .;
|
|
||||||
.ARM.exidx :
|
|
||||||
{
|
|
||||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
|
||||||
} > FLASH
|
|
||||||
__exidx_end = .;
|
|
||||||
|
|
||||||
__etext = .;
|
|
||||||
_sidata = .;
|
|
||||||
|
|
||||||
.data : AT (__etext)
|
|
||||||
{
|
|
||||||
__data_start__ = .;
|
|
||||||
_sdata = .;
|
|
||||||
*(vtable)
|
|
||||||
*(.data*)
|
|
||||||
|
|
||||||
. = ALIGN(4);
|
|
||||||
/* preinit data */
|
|
||||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
|
||||||
KEEP(*(.preinit_array))
|
|
||||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
|
||||||
|
|
||||||
. = ALIGN(4);
|
|
||||||
/* init data */
|
|
||||||
PROVIDE_HIDDEN (__init_array_start = .);
|
|
||||||
KEEP(*(SORT(.init_array.*)))
|
|
||||||
KEEP(*(.init_array))
|
|
||||||
PROVIDE_HIDDEN (__init_array_end = .);
|
|
||||||
|
|
||||||
|
|
||||||
. = ALIGN(4);
|
|
||||||
/* finit data */
|
|
||||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
|
||||||
KEEP(*(SORT(.fini_array.*)))
|
|
||||||
KEEP(*(.fini_array))
|
|
||||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
|
||||||
|
|
||||||
KEEP(*(.jcr*))
|
|
||||||
. = ALIGN(4);
|
|
||||||
/* All data end */
|
|
||||||
__data_end__ = .;
|
|
||||||
_edata = .;
|
|
||||||
|
|
||||||
} > RAM
|
|
||||||
|
|
||||||
.bss :
|
|
||||||
{
|
|
||||||
. = ALIGN(4);
|
|
||||||
__bss_start__ = .;
|
|
||||||
_sbss = .;
|
|
||||||
*(.bss*)
|
|
||||||
*(COMMON)
|
|
||||||
. = ALIGN(4);
|
|
||||||
__bss_end__ = .;
|
|
||||||
_ebss = .;
|
|
||||||
} > RAM
|
|
||||||
|
|
||||||
.heap (COPY):
|
|
||||||
{
|
|
||||||
__end__ = .;
|
|
||||||
end = __end__;
|
|
||||||
*(.heap*)
|
|
||||||
__HeapLimit = .;
|
|
||||||
} > RAM
|
|
||||||
|
|
||||||
/* .stack_dummy section doesn't contains any symbols. It is only
|
|
||||||
* used for linker to calculate size of stack sections, and assign
|
|
||||||
* values to stack symbols later */
|
|
||||||
.stack_dummy (COPY):
|
|
||||||
{
|
|
||||||
*(.stack*)
|
|
||||||
} > RAM
|
|
||||||
|
|
||||||
/* Set stack top to end of RAM, and stack limit move down by
|
|
||||||
* size of stack_dummy section */
|
|
||||||
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
|
|
||||||
_estack = __StackTop;
|
|
||||||
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
|
|
||||||
PROVIDE(__stack = __StackTop);
|
|
||||||
|
|
||||||
/* Check if data + heap + stack exceeds RAM limit */
|
|
||||||
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
|
|
||||||
}
|
|
||||||
10650
cmsis-stm32f4xx.h
10650
cmsis-stm32f4xx.h
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,84 @@
|
||||||
|
/* Linker script for STM32F411RE Cortex-M4 ARM MCU */
|
||||||
|
|
||||||
|
/* Copyright (C)2013-2018, Philip Munts, President, Munts AM Corp. */
|
||||||
|
/* */
|
||||||
|
/* Redistribution and use in source and binary forms, with or without */
|
||||||
|
/* modification, are permitted provided that the following conditions are met: */
|
||||||
|
/* */
|
||||||
|
/* * Redistributions of source code must retain the above copyright notice, */
|
||||||
|
/* this list of conditions and the following disclaimer. */
|
||||||
|
/* */
|
||||||
|
/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" */
|
||||||
|
/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE */
|
||||||
|
/* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE */
|
||||||
|
/* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE */
|
||||||
|
/* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR */
|
||||||
|
/* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF */
|
||||||
|
/* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS */
|
||||||
|
/* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN */
|
||||||
|
/* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) */
|
||||||
|
/* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE */
|
||||||
|
/* POSSIBILITY OF SUCH DAMAGE. */
|
||||||
|
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
flash (rx) : ORIGIN = 0x08000000, LENGTH = 512K
|
||||||
|
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 128K
|
||||||
|
}
|
||||||
|
|
||||||
|
__rom_start__ = ORIGIN(flash);
|
||||||
|
__rom_size__ = LENGTH(flash);
|
||||||
|
__ram_start__ = ORIGIN(ram);
|
||||||
|
__ram_size__ = LENGTH(ram);
|
||||||
|
__ram_end__ = __ram_start__ + __ram_size__;
|
||||||
|
__stack_end__ = __ram_end__; /* Top of RAM */
|
||||||
|
__stack_size__ = 16K;
|
||||||
|
__stack_start__ = __stack_end__ - __stack_size__;
|
||||||
|
__heap_start__ = __bss_end__; /* Between bss and stack */
|
||||||
|
__heap_end__ = __stack_start__;
|
||||||
|
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
. = 0;
|
||||||
|
|
||||||
|
.text : {
|
||||||
|
KEEP(*(.startup)) /* Startup code */
|
||||||
|
*(.text*) /* Program code */
|
||||||
|
KEEP(*(.rodata*)) /* Read only data */
|
||||||
|
*(.glue_7)
|
||||||
|
*(.glue_7t)
|
||||||
|
*(.eh_frame)
|
||||||
|
. = ALIGN(4);
|
||||||
|
__ctors_start__ = .;
|
||||||
|
KEEP(*(.init_array)) /* C++ constructors */
|
||||||
|
KEEP(*(.ctors)) /* C++ constructors */
|
||||||
|
__ctors_end__ = .;
|
||||||
|
. = ALIGN(16);
|
||||||
|
__text_end__ = .;
|
||||||
|
} >flash
|
||||||
|
|
||||||
|
.data : ALIGN(16) {
|
||||||
|
__data_beg__ = .; /* Used in crt0.S */
|
||||||
|
*(.data*) /* Initialized data */
|
||||||
|
__data_end__ = .; /* Used in crt0.S */
|
||||||
|
} >ram AT > flash
|
||||||
|
|
||||||
|
.bss (NOLOAD) : ALIGN(16) {
|
||||||
|
__bss_beg__ = .; /* Used in crt0.S */
|
||||||
|
*(.bss*) /* Uninitialized data */
|
||||||
|
*(COMMON) /* Common data */
|
||||||
|
__bss_end__ = .; /* Used in crt0.S */
|
||||||
|
} >ram
|
||||||
|
|
||||||
|
/* C++ exception unwinding stuff--needed by some toolchains */
|
||||||
|
|
||||||
|
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >flash
|
||||||
|
|
||||||
|
__exidx_start = .;
|
||||||
|
.ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } >flash
|
||||||
|
__exidx_end = .;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Firmware entry point */
|
||||||
|
|
||||||
|
ENTRY(_vectors)
|
||||||
|
|
@ -282,27 +282,56 @@ void SetSysClock(void)
|
||||||
// PLLP: PLLCLK = 96 MHz (384 MHz / 4)
|
// PLLP: PLLCLK = 96 MHz (384 MHz / 4)
|
||||||
// PLLQ: USB clock = 48 MHz (384 MHz / 8) --> 48MHz is best choice for USB
|
// PLLQ: USB clock = 48 MHz (384 MHz / 8) --> 48MHz is best choice for USB
|
||||||
#if __SYSTEM_CLOCK == 96000000
|
#if __SYSTEM_CLOCK == 96000000
|
||||||
|
#if !defined(STM32F411xE) && !defined(STM32F446xx)
|
||||||
|
#warning You are running the controller out of specification! 96 MHz!
|
||||||
|
#endif
|
||||||
#define PLLM 4
|
#define PLLM 4
|
||||||
#define PLLN 192
|
#define PLLN 192
|
||||||
#define PLLP 4
|
#define PLLP 4
|
||||||
#define PLLQ 8
|
#define PLLQ 8
|
||||||
|
#define LATENCY FLASH_ACR_LATENCY_3WS
|
||||||
#elif __SYSTEM_CLOCK == 100000000
|
#elif __SYSTEM_CLOCK == 100000000
|
||||||
|
#if !defined(STM32F411xE) && !defined(STM32F446xx)
|
||||||
|
#warning You are running the controller out of specification! 100 MHz!
|
||||||
|
#endif
|
||||||
#define PLLM 4
|
#define PLLM 4
|
||||||
#define PLLN 200
|
#define PLLN 200
|
||||||
#define PLLP 4
|
#define PLLP 4
|
||||||
#define PLLQ 8
|
#define PLLQ 8
|
||||||
|
#define LATENCY FLASH_ACR_LATENCY_3WS
|
||||||
#elif __SYSTEM_CLOCK == 108000000
|
#elif __SYSTEM_CLOCK == 108000000
|
||||||
#warning You are running the controller out of specification!
|
#if !defined(STM32F446xx)
|
||||||
|
#warning You are running the controller out of specification! 108 MHz!
|
||||||
|
#endif
|
||||||
#define PLLM 4
|
#define PLLM 4
|
||||||
#define PLLN 216
|
#define PLLN 216
|
||||||
#define PLLP 4
|
#define PLLP 4
|
||||||
#define PLLQ 9
|
#define PLLQ 9
|
||||||
|
#define LATENCY FLASH_ACR_LATENCY_3WS
|
||||||
#elif __SYSTEM_CLOCK == 125000000
|
#elif __SYSTEM_CLOCK == 125000000
|
||||||
#warning You are running the controller out of specification!
|
#if !defined(STM32F446xx)
|
||||||
|
#warning You are running the controller out of specification! 125 MHz!
|
||||||
|
#endif
|
||||||
#define PLLM 4
|
#define PLLM 4
|
||||||
#define PLLN 250
|
#define PLLN 250
|
||||||
#define PLLP 4
|
#define PLLP 4
|
||||||
#define PLLQ 10
|
#define PLLQ 10
|
||||||
|
#define LATENCY FLASH_ACR_LATENCY_4WS
|
||||||
|
#elif __SYSTEM_CLOCK == 84000000
|
||||||
|
#define PLLM 4
|
||||||
|
#define PLLN 168
|
||||||
|
#define PLLP 4
|
||||||
|
#define PLLQ 7
|
||||||
|
#define LATENCY FLASH_ACR_LATENCY_2WS
|
||||||
|
#elif __SYSTEM_CLOCK == 180000000
|
||||||
|
#if !defined(STM32F446xx)
|
||||||
|
#warning You are running the controller out of specification! 180 MHz!
|
||||||
|
#endif
|
||||||
|
#define PLLM 4
|
||||||
|
#define PLLN 180
|
||||||
|
#define PLLP 2
|
||||||
|
#define PLLQ 8
|
||||||
|
#define LATENCY FLASH_ACR_LATENCY_5WS
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
RCC->PLLCFGR = RCC_PLLCFGR_PLLSRC_HSE |
|
RCC->PLLCFGR = RCC_PLLCFGR_PLLSRC_HSE |
|
||||||
|
|
@ -320,11 +349,11 @@ void SetSysClock(void)
|
||||||
(HCLK) and the supply voltage of the device. */
|
(HCLK) and the supply voltage of the device. */
|
||||||
|
|
||||||
/* Increasing the CPU frequency */
|
/* Increasing the CPU frequency */
|
||||||
if(FLASH_ACR_LATENCY_3WS > (FLASH->ACR & FLASH_ACR_LATENCY))
|
if(LATENCY > (FLASH->ACR & FLASH_ACR_LATENCY))
|
||||||
{
|
{
|
||||||
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
||||||
FLASH->ACR &= ~(FLASH_ACR_LATENCY);
|
FLASH->ACR &= ~(FLASH_ACR_LATENCY);
|
||||||
FLASH->ACR |= FLASH_ACR_LATENCY_3WS;
|
FLASH->ACR |= LATENCY;
|
||||||
|
|
||||||
RCC->CFGR &= ~(RCC_CFGR_HPRE | RCC_CFGR_SW);
|
RCC->CFGR &= ~(RCC_CFGR_HPRE | RCC_CFGR_SW);
|
||||||
RCC->CFGR |= RCC_CFGR_HPRE_DIV1 | RCC_CFGR_SW_PLL;
|
RCC->CFGR |= RCC_CFGR_HPRE_DIV1 | RCC_CFGR_SW_PLL;
|
||||||
|
|
@ -337,7 +366,7 @@ void SetSysClock(void)
|
||||||
|
|
||||||
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
||||||
FLASH->ACR &= ~(FLASH_ACR_LATENCY);
|
FLASH->ACR &= ~(FLASH_ACR_LATENCY);
|
||||||
FLASH->ACR |= FLASH_ACR_LATENCY_3WS;
|
FLASH->ACR |= LATENCY;
|
||||||
}
|
}
|
||||||
|
|
||||||
RCC->CFGR &= ~(RCC_CFGR_PPRE1 | RCC_CFGR_PPRE2);
|
RCC->CFGR &= ~(RCC_CFGR_PPRE1 | RCC_CFGR_PPRE2);
|
||||||
|
|
|
||||||
|
|
@ -56,7 +56,7 @@
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
// #define __SYSTEM_CLOCK 96000000
|
// #define __SYSTEM_CLOCK 96000000
|
||||||
#define __SYSTEM_CLOCK 100000000
|
// #define __SYSTEM_CLOCK 100000000
|
||||||
// #define __SYSTEM_CLOCK 108000000 // Overclocking is not recommended!
|
// #define __SYSTEM_CLOCK 108000000 // Overclocking is not recommended!
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue