ARM: move system definitions from .c to .h.
More precisely, from mbed-system_LPC11xx.c to mbed-system_LPC11xx.h. This way these definitions are available elsewhere in the code.
This commit is contained in:
Markus Hitter
parent
52e2585f13
commit
e2df7733ee
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@ -37,219 +37,18 @@
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- Silenced this warning:
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- Silenced this warning:
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system_LPC11xx.c:344:21: warning: unused variable 'i'
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system_LPC11xx.c:344:21: warning: unused variable 'i'
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by declaring i directly where it's used and renaming the other to 'j'.
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by declaring i directly where it's used and renaming the other to 'j'.
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- Moved definitions to system_LPC11xx.h to have them available elsewhere.
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Replaced by this marker:
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// Moved definitions from here to system_LPC11xx.h.
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and replaced #include <stdint.h> with #include "mbed-system_LPC11xx.h"
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*/
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*/
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#ifdef __ARMEL__
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#ifdef __ARMEL__
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#include <stdint.h>
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#include "mbed-system_LPC11xx.h"
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#include "mbed-LPC11xx.h"
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#include "mbed-LPC11xx.h"
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/*
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// Moved definitions from here to system_LPC11xx.h.
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//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
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*/
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/*--------------------- Clock Configuration ----------------------------------
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//
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// <e> Clock Configuration
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// <h> System Oscillator Control Register (SYSOSCCTRL)
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// <o1.0> BYPASS: System Oscillator Bypass Enable
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// <i> If enabled then PLL input (sys_osc_clk) is fed
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// <i> directly from XTALIN and XTALOUT pins.
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// <o1.9> FREQRANGE: System Oscillator Frequency Range
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// <i> Determines frequency range for Low-power oscillator.
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// <0=> 1 - 20 MHz
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// <1=> 15 - 25 MHz
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// </h>
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//
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// <h> Watchdog Oscillator Control Register (WDTOSCCTRL)
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// <o2.0..4> DIVSEL: Select Divider for Fclkana
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// <i> wdt_osc_clk = Fclkana/ (2 * (1 + DIVSEL))
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// <0-31>
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// <o2.5..8> FREQSEL: Select Watchdog Oscillator Analog Output Frequency (Fclkana)
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// <0=> Undefined
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// <1=> 0.5 MHz
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// <2=> 0.8 MHz
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// <3=> 1.1 MHz
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// <4=> 1.4 MHz
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// <5=> 1.6 MHz
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// <6=> 1.8 MHz
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// <7=> 2.0 MHz
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// <8=> 2.2 MHz
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// <9=> 2.4 MHz
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// <10=> 2.6 MHz
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// <11=> 2.7 MHz
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// <12=> 2.9 MHz
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// <13=> 3.1 MHz
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// <14=> 3.2 MHz
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// <15=> 3.4 MHz
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// </h>
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//
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// <h> System PLL Control Register (SYSPLLCTRL)
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// <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
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// <i> F_clkin must be in the range of 10 MHz to 25 MHz
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// <i> F_CCO must be in the range of 156 MHz to 320 MHz
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// <o3.0..4> MSEL: Feedback Divider Selection
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// <i> M = MSEL + 1
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// <0-31>
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// <o3.5..6> PSEL: Post Divider Selection
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// <0=> P = 1
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// <1=> P = 2
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// <2=> P = 4
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// <3=> P = 8
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// </h>
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//
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// <h> System PLL Clock Source Select Register (SYSPLLCLKSEL)
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// <o4.0..1> SEL: System PLL Clock Source
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// <0=> IRC Oscillator
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// <1=> System Oscillator
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// <2=> Reserved
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// <3=> Reserved
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// </h>
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//
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// <h> Main Clock Source Select Register (MAINCLKSEL)
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// <o5.0..1> SEL: Clock Source for Main Clock
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// <0=> IRC Oscillator
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// <1=> Input Clock to System PLL
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// <2=> WDT Oscillator
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// <3=> System PLL Clock Out
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// </h>
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//
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// <h> System AHB Clock Divider Register (SYSAHBCLKDIV)
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// <o6.0..7> DIV: System AHB Clock Divider
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// <i> Divides main clock to provide system clock to core, memories, and peripherals.
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// <i> 0 = is disabled
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// <0-255>
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// </h>
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// </e>
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*/
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#define CLOCK_SETUP 1
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#define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000
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#define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000
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#define SYSPLLCTRL_Val 0x00000023 // Reset: 0x000
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#define SYSPLLCLKSEL_Val 0x00000000 // Reset: 0x000 // Define as using IRC
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#define MAINCLKSEL_Val 0x00000003 // Reset: 0x000 // Define as using System PLL clock out
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#define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001
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/*
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//-------- <<< end of configuration section >>> ------------------------------
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*/
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/*----------------------------------------------------------------------------
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Check the register settings
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*----------------------------------------------------------------------------*/
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#define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
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#define CHECK_RSVD(val, mask) (val & mask)
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/* Clock Configuration -------------------------------------------------------*/
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#if (CHECK_RSVD((SYSOSCCTRL_Val), ~0x00000003))
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#error "SYSOSCCTRL: Invalid values of reserved bits!"
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#endif
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#if (CHECK_RSVD((WDTOSCCTRL_Val), ~0x000001FF))
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#error "WDTOSCCTRL: Invalid values of reserved bits!"
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#endif
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#if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 2))
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#error "SYSPLLCLKSEL: Value out of range!"
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#endif
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#if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x000001FF))
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#error "SYSPLLCTRL: Invalid values of reserved bits!"
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#endif
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#if (CHECK_RSVD((MAINCLKSEL_Val), ~0x00000003))
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#error "MAINCLKSEL: Invalid values of reserved bits!"
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#endif
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#if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255))
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#error "SYSAHBCLKDIV: Value out of range!"
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#endif
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/*----------------------------------------------------------------------------
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DEFINES
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*----------------------------------------------------------------------------*/
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/*----------------------------------------------------------------------------
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Define clocks
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*----------------------------------------------------------------------------*/
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#define __XTAL (12000000UL) /* Oscillator frequency */
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#define __SYS_OSC_CLK ( __XTAL) /* Main oscillator frequency */
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#define __IRC_OSC_CLK (12000000UL) /* Internal RC oscillator frequency */
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#define __FREQSEL ((WDTOSCCTRL_Val >> 5) & 0x0F)
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#define __DIVSEL (((WDTOSCCTRL_Val & 0x1F) << 1) + 2)
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#if (CLOCK_SETUP) /* Clock Setup */
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#if (__FREQSEL == 0)
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#define __WDT_OSC_CLK ( 0) /* undefined */
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#elif (__FREQSEL == 1)
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#define __WDT_OSC_CLK ( 500000 / __DIVSEL)
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#elif (__FREQSEL == 2)
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#define __WDT_OSC_CLK ( 800000 / __DIVSEL)
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#elif (__FREQSEL == 3)
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#define __WDT_OSC_CLK (1100000 / __DIVSEL)
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#elif (__FREQSEL == 4)
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#define __WDT_OSC_CLK (1400000 / __DIVSEL)
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#elif (__FREQSEL == 5)
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#define __WDT_OSC_CLK (1600000 / __DIVSEL)
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#elif (__FREQSEL == 6)
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#define __WDT_OSC_CLK (1800000 / __DIVSEL)
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#elif (__FREQSEL == 7)
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#define __WDT_OSC_CLK (2000000 / __DIVSEL)
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#elif (__FREQSEL == 8)
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#define __WDT_OSC_CLK (2200000 / __DIVSEL)
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#elif (__FREQSEL == 9)
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#define __WDT_OSC_CLK (2400000 / __DIVSEL)
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#elif (__FREQSEL == 10)
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#define __WDT_OSC_CLK (2600000 / __DIVSEL)
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#elif (__FREQSEL == 11)
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#define __WDT_OSC_CLK (2700000 / __DIVSEL)
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#elif (__FREQSEL == 12)
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#define __WDT_OSC_CLK (2900000 / __DIVSEL)
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#elif (__FREQSEL == 13)
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#define __WDT_OSC_CLK (3100000 / __DIVSEL)
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#elif (__FREQSEL == 14)
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#define __WDT_OSC_CLK (3200000 / __DIVSEL)
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#else
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#define __WDT_OSC_CLK (3400000 / __DIVSEL)
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#endif
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/* sys_pllclkin calculation */
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#if ((SYSPLLCLKSEL_Val & 0x03) == 0)
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#define __SYS_PLLCLKIN (__IRC_OSC_CLK)
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#elif ((SYSPLLCLKSEL_Val & 0x03) == 1)
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#define __SYS_PLLCLKIN (__SYS_OSC_CLK)
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#else
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#define __SYS_PLLCLKIN (0)
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#endif
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#define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1))
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/* main clock calculation */
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#if ((MAINCLKSEL_Val & 0x03) == 0)
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#define __MAIN_CLOCK (__IRC_OSC_CLK)
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#elif ((MAINCLKSEL_Val & 0x03) == 1)
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#define __MAIN_CLOCK (__SYS_PLLCLKIN)
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#elif ((MAINCLKSEL_Val & 0x03) == 2)
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#if (__FREQSEL == 0)
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#error "MAINCLKSEL: WDT Oscillator selected but FREQSEL is undefined!"
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#else
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#define __MAIN_CLOCK (__WDT_OSC_CLK)
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#endif
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#elif ((MAINCLKSEL_Val & 0x03) == 3)
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#define __MAIN_CLOCK (__SYS_PLLCLKOUT)
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#else
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#define __MAIN_CLOCK (0)
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#endif
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#define __SYSTEM_CLOCK (__MAIN_CLOCK / SYSAHBCLKDIV_Val)
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#else
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#define __SYSTEM_CLOCK (__IRC_OSC_CLK)
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#endif // CLOCK_SETUP
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/*----------------------------------------------------------------------------
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/*----------------------------------------------------------------------------
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Clock Variable definitions
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Clock Variable definitions
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@ -9,9 +9,9 @@
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* Copyright (C) 2009-2010 ARM Limited. All rights reserved.
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* Copyright (C) 2009-2010 ARM Limited. All rights reserved.
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*
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*
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* @par
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* @par
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* ARM Limited (ARM) is supplying this software for use with Cortex-M
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* ARM Limited (ARM) is supplying this software for use with Cortex-M
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* processor based microcontrollers. This file can be freely distributed
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* processor based microcontrollers. This file can be freely distributed
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* within development tools that are supporting such ARM based processors.
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* within development tools that are supporting such ARM based processors.
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*
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*
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* @par
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* @par
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* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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@ -32,6 +32,11 @@
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- Prefixed names of #include files with mbed- to match the names of the
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- Prefixed names of #include files with mbed- to match the names of the
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copies in the Teacup repo.
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copies in the Teacup repo.
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- Moved all the definitions from system_LPC11xx.h to here to have them
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available elsewhere. It's the section between
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// From system_LPC11xx.c start.
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and
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// From system_LPC11xx.c start.
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*/
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*/
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@ -44,6 +49,215 @@ extern "C" {
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#include <stdint.h>
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#include <stdint.h>
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// From system_LPC11xx.c start.
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/*
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//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
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*/
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/*--------------------- Clock Configuration ----------------------------------
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//
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// <e> Clock Configuration
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// <h> System Oscillator Control Register (SYSOSCCTRL)
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// <o1.0> BYPASS: System Oscillator Bypass Enable
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// <i> If enabled then PLL input (sys_osc_clk) is fed
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// <i> directly from XTALIN and XTALOUT pins.
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// <o1.9> FREQRANGE: System Oscillator Frequency Range
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// <i> Determines frequency range for Low-power oscillator.
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// <0=> 1 - 20 MHz
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// <1=> 15 - 25 MHz
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// </h>
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//
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// <h> Watchdog Oscillator Control Register (WDTOSCCTRL)
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// <o2.0..4> DIVSEL: Select Divider for Fclkana
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// <i> wdt_osc_clk = Fclkana/ (2 * (1 + DIVSEL))
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// <0-31>
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// <o2.5..8> FREQSEL: Select Watchdog Oscillator Analog Output Frequency (Fclkana)
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// <0=> Undefined
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// <1=> 0.5 MHz
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// <2=> 0.8 MHz
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// <3=> 1.1 MHz
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// <4=> 1.4 MHz
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// <5=> 1.6 MHz
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// <6=> 1.8 MHz
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// <7=> 2.0 MHz
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// <8=> 2.2 MHz
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// <9=> 2.4 MHz
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// <10=> 2.6 MHz
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// <11=> 2.7 MHz
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// <12=> 2.9 MHz
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// <13=> 3.1 MHz
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// <14=> 3.2 MHz
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// <15=> 3.4 MHz
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// </h>
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//
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// <h> System PLL Control Register (SYSPLLCTRL)
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// <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
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// <i> F_clkin must be in the range of 10 MHz to 25 MHz
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// <i> F_CCO must be in the range of 156 MHz to 320 MHz
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// <o3.0..4> MSEL: Feedback Divider Selection
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// <i> M = MSEL + 1
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// <0-31>
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// <o3.5..6> PSEL: Post Divider Selection
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// <0=> P = 1
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// <1=> P = 2
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// <2=> P = 4
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// <3=> P = 8
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// </h>
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//
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// <h> System PLL Clock Source Select Register (SYSPLLCLKSEL)
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// <o4.0..1> SEL: System PLL Clock Source
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// <0=> IRC Oscillator
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// <1=> System Oscillator
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// <2=> Reserved
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// <3=> Reserved
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// </h>
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//
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// <h> Main Clock Source Select Register (MAINCLKSEL)
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// <o5.0..1> SEL: Clock Source for Main Clock
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// <0=> IRC Oscillator
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// <1=> Input Clock to System PLL
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// <2=> WDT Oscillator
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// <3=> System PLL Clock Out
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// </h>
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//
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// <h> System AHB Clock Divider Register (SYSAHBCLKDIV)
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// <o6.0..7> DIV: System AHB Clock Divider
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// <i> Divides main clock to provide system clock to core, memories, and peripherals.
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// <i> 0 = is disabled
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// <0-255>
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// </h>
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// </e>
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*/
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#define CLOCK_SETUP 1
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#define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000
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#define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000
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#define SYSPLLCTRL_Val 0x00000023 // Reset: 0x000
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#define SYSPLLCLKSEL_Val 0x00000000 // Reset: 0x000 // Define as using IRC
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#define MAINCLKSEL_Val 0x00000003 // Reset: 0x000 // Define as using System PLL clock out
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#define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001
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/*
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//-------- <<< end of configuration section >>> ------------------------------
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*/
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/*----------------------------------------------------------------------------
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Check the register settings
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*----------------------------------------------------------------------------*/
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#define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
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#define CHECK_RSVD(val, mask) (val & mask)
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||||||
|
/* Clock Configuration -------------------------------------------------------*/
|
||||||
|
#if (CHECK_RSVD((SYSOSCCTRL_Val), ~0x00000003))
|
||||||
|
#error "SYSOSCCTRL: Invalid values of reserved bits!"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (CHECK_RSVD((WDTOSCCTRL_Val), ~0x000001FF))
|
||||||
|
#error "WDTOSCCTRL: Invalid values of reserved bits!"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 2))
|
||||||
|
#error "SYSPLLCLKSEL: Value out of range!"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x000001FF))
|
||||||
|
#error "SYSPLLCTRL: Invalid values of reserved bits!"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (CHECK_RSVD((MAINCLKSEL_Val), ~0x00000003))
|
||||||
|
#error "MAINCLKSEL: Invalid values of reserved bits!"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255))
|
||||||
|
#error "SYSAHBCLKDIV: Value out of range!"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/*----------------------------------------------------------------------------
|
||||||
|
DEFINES
|
||||||
|
*----------------------------------------------------------------------------*/
|
||||||
|
|
||||||
|
/*----------------------------------------------------------------------------
|
||||||
|
Define clocks
|
||||||
|
*----------------------------------------------------------------------------*/
|
||||||
|
#define __XTAL (12000000UL) /* Oscillator frequency */
|
||||||
|
#define __SYS_OSC_CLK ( __XTAL) /* Main oscillator frequency */
|
||||||
|
#define __IRC_OSC_CLK (12000000UL) /* Internal RC oscillator frequency */
|
||||||
|
|
||||||
|
|
||||||
|
#define __FREQSEL ((WDTOSCCTRL_Val >> 5) & 0x0F)
|
||||||
|
#define __DIVSEL (((WDTOSCCTRL_Val & 0x1F) << 1) + 2)
|
||||||
|
|
||||||
|
#if (CLOCK_SETUP) /* Clock Setup */
|
||||||
|
#if (__FREQSEL == 0)
|
||||||
|
#define __WDT_OSC_CLK ( 0) /* undefined */
|
||||||
|
#elif (__FREQSEL == 1)
|
||||||
|
#define __WDT_OSC_CLK ( 500000 / __DIVSEL)
|
||||||
|
#elif (__FREQSEL == 2)
|
||||||
|
#define __WDT_OSC_CLK ( 800000 / __DIVSEL)
|
||||||
|
#elif (__FREQSEL == 3)
|
||||||
|
#define __WDT_OSC_CLK (1100000 / __DIVSEL)
|
||||||
|
#elif (__FREQSEL == 4)
|
||||||
|
#define __WDT_OSC_CLK (1400000 / __DIVSEL)
|
||||||
|
#elif (__FREQSEL == 5)
|
||||||
|
#define __WDT_OSC_CLK (1600000 / __DIVSEL)
|
||||||
|
#elif (__FREQSEL == 6)
|
||||||
|
#define __WDT_OSC_CLK (1800000 / __DIVSEL)
|
||||||
|
#elif (__FREQSEL == 7)
|
||||||
|
#define __WDT_OSC_CLK (2000000 / __DIVSEL)
|
||||||
|
#elif (__FREQSEL == 8)
|
||||||
|
#define __WDT_OSC_CLK (2200000 / __DIVSEL)
|
||||||
|
#elif (__FREQSEL == 9)
|
||||||
|
#define __WDT_OSC_CLK (2400000 / __DIVSEL)
|
||||||
|
#elif (__FREQSEL == 10)
|
||||||
|
#define __WDT_OSC_CLK (2600000 / __DIVSEL)
|
||||||
|
#elif (__FREQSEL == 11)
|
||||||
|
#define __WDT_OSC_CLK (2700000 / __DIVSEL)
|
||||||
|
#elif (__FREQSEL == 12)
|
||||||
|
#define __WDT_OSC_CLK (2900000 / __DIVSEL)
|
||||||
|
#elif (__FREQSEL == 13)
|
||||||
|
#define __WDT_OSC_CLK (3100000 / __DIVSEL)
|
||||||
|
#elif (__FREQSEL == 14)
|
||||||
|
#define __WDT_OSC_CLK (3200000 / __DIVSEL)
|
||||||
|
#else
|
||||||
|
#define __WDT_OSC_CLK (3400000 / __DIVSEL)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* sys_pllclkin calculation */
|
||||||
|
#if ((SYSPLLCLKSEL_Val & 0x03) == 0)
|
||||||
|
#define __SYS_PLLCLKIN (__IRC_OSC_CLK)
|
||||||
|
#elif ((SYSPLLCLKSEL_Val & 0x03) == 1)
|
||||||
|
#define __SYS_PLLCLKIN (__SYS_OSC_CLK)
|
||||||
|
#else
|
||||||
|
#define __SYS_PLLCLKIN (0)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1))
|
||||||
|
|
||||||
|
/* main clock calculation */
|
||||||
|
#if ((MAINCLKSEL_Val & 0x03) == 0)
|
||||||
|
#define __MAIN_CLOCK (__IRC_OSC_CLK)
|
||||||
|
#elif ((MAINCLKSEL_Val & 0x03) == 1)
|
||||||
|
#define __MAIN_CLOCK (__SYS_PLLCLKIN)
|
||||||
|
#elif ((MAINCLKSEL_Val & 0x03) == 2)
|
||||||
|
#if (__FREQSEL == 0)
|
||||||
|
#error "MAINCLKSEL: WDT Oscillator selected but FREQSEL is undefined!"
|
||||||
|
#else
|
||||||
|
#define __MAIN_CLOCK (__WDT_OSC_CLK)
|
||||||
|
#endif
|
||||||
|
#elif ((MAINCLKSEL_Val & 0x03) == 3)
|
||||||
|
#define __MAIN_CLOCK (__SYS_PLLCLKOUT)
|
||||||
|
#else
|
||||||
|
#define __MAIN_CLOCK (0)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define __SYSTEM_CLOCK (__MAIN_CLOCK / SYSAHBCLKDIV_Val)
|
||||||
|
|
||||||
|
#else
|
||||||
|
#define __SYSTEM_CLOCK (__IRC_OSC_CLK)
|
||||||
|
#endif // CLOCK_SETUP
|
||||||
|
// From system_LPC11xx.c end.
|
||||||
|
|
||||||
|
|
||||||
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
|
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -64,7 +278,7 @@ extern void SystemInit (void);
|
||||||
* @param none
|
* @param none
|
||||||
* @return none
|
* @return none
|
||||||
*
|
*
|
||||||
* @brief Updates the SystemCoreClock with current core Clock
|
* @brief Updates the SystemCoreClock with current core Clock
|
||||||
* retrieved from cpu registers.
|
* retrieved from cpu registers.
|
||||||
*/
|
*/
|
||||||
extern void SystemCoreClockUpdate (void);
|
extern void SystemCoreClockUpdate (void);
|
||||||
|
|
|
||||||
|
|
@ -14,6 +14,7 @@
|
||||||
#if defined TEACUP_C_INCLUDE && defined __ARMEL__
|
#if defined TEACUP_C_INCLUDE && defined __ARMEL__
|
||||||
|
|
||||||
#include "arduino.h"
|
#include "arduino.h"
|
||||||
|
#include "mbed-LPC11xx.h"
|
||||||
|
|
||||||
#ifdef XONXOFF
|
#ifdef XONXOFF
|
||||||
#error XON/XOFF protocol not yet implemented for ARM. \
|
#error XON/XOFF protocol not yet implemented for ARM. \
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue